Boundary Scan

Outline
• Definition
• Boundary-scan Architecture
• Boundary scan cell
• Scan and BIST support with boundary scan
• Boundary-Scan Control Architectures
 Internal Vs External Scan
• External scan
– Stitch system input/output pins into a shift register
– Enable control of system input and observe system output
– Aka boundary scan

Courtesy: Professor James Chien-Mo Li

 Why Boundary scan
• 1. Board-level test and diagnosis
• 2. Test on-board interconnect among chips
• 3. Test on-chip system logic
 Board-level test and diagnosis
• All chips are stitched into one JTAG scan chain
Test on-board interconnect among
chips
 Test on-chip system logic
• On-chip - system assembled on board
• To test a chip already assembled on board we cannot use ATE
 Boundary Scan
• Aka IEEE 1149.1 (or) Joint Test Action Group (JTAG) standard
• Most successful test standard ever approved by the IEEE
• Initially targeting board-level testing for digital circuits,
• Now this standard been adopted by industry for use in most large IC chips
• Has been used to access many other applications, power management,
clock control, debugging, verification, and chip reconfiguration
• IEEE 1149.6
– An extended boundary-scan standard for the I/O protocol of high-
speed networks
– Further enhances the applicability of boundary scan
 DIGITAL BOUNDARY SCAN (IEEE Std. 1149.1)
• Standard 1149.1 defines a test access protocol and a boundary-scan
architecture for
– Digital integrated circuits and the digital portions of mixed
analog/digital ICs
Name boundary scan is due to
Insertion of a boundary-scan cell to each I/O
pin of the original circuit
Chaining of these cells into a shift register
(boundary-scan register)
Chips complying with this standard can be readily
integrated into a PCB
I/O accessible through the boundary-scan
registers
 DIGITAL BOUNDARY SCAN
• A board containing four ICs for
which the boundary-scan
registers are interconnected
into a single boundary-scan
chain

• Through this chain the I/Os of

each chip are controllable and
observable via serial scan and
Capture/Update operations
 Boundary-scan Architecture (BSA)
• A test access port (TAP)
– Define the bus protocol of BS
– TDI, TDO, TMS, and test clock
(TCK)
– One optional terminal TRST
• TAP controller (TAPC) 16-state, FSM
– controls each step of the
boundary-scan operations
• Registers
– Test data registers
• Boundary-scan register
• Bypass register (mandatory)
– Instruction register (IR)
• Instruction decoder
• Internal logic (Original circuit of chip)
 JTAG Architecture
• JTAG Components
– 1. Test Access Port (TAP)
– 2. TAP controller
– 3. Registers
• Instruction Register, Boundary Scan Register, Bypass Register…
– 4. Instruction Decoder

Courtesy: Professor James Chien-Mo Li

 Boundary-scan Architecture
• Test access port defines the bus protocol of the boundary scan
• TAP controller 16-state, FSM
– controls each step of the boundary-scan operations
• Instruction to be carried out by the boundary-scan architecture serially
loaded into the instruction register through test data input (TDI) pin
• The test signals to configure the boundary-scan-related test hardware for
the current test instruction are provided by the associated decoder
• Test data registers are used to store test data or some system-related
information (such as the chip ID, company name, etc.)
 Boundary-scan Architecture
• In addition to the hardware components, IEEE Std. 1149.1 also
defines a set of test instructions,
– Four mandatory ones (BYPASS, SAMPLE, PRELOAD, and
EXTEST)
– Several optional ones, including INTEST, RUNBIST, CLAMP,
IDCODE, USERCODE, and HIGHZ.
– It also allows the users to define their own instructions
 Test procedure using Boundary scan
• 1. A boundary-scan test instruction is shifted into the IR through TDI
• 2. The instruction is decoded by the decoder to generate the required
control signals so as to properly configure the test logic
• 3. A test pattern is shifted into the selected data register through the TDI
and then applied to the logic to be tested
• 4. The test response is captured into some data register
• 5. Captured response is shifted out through the TDO for observation and,
at the same time, a new test pattern can be scanned in through the TDI.
• 6. Steps 3 to 5 are repeated until all test patterns are shifted in and
applied, and all test responses are shifted out
Boundary-scan circuitry in a chip
 Test Access Port
Test clock input (TCK)
• Synchronize the test operations
– between various parts of a chip or
– between different chips on a PCB
• This input must be independent of the system clocks
• Facilitating online system monitoring for a design
– the shifting and capturing of test data can be executed concurrently
with normal system operation
 Test Access Port
• Test data input (TDI)
– Input to allow test instructions and test data to be serially loaded into
the instruction register and the various test data registers
– Values presented at TDI are clocked into the selected register on a
rising edge of TCK.

• Test data output (TDO)

– Output to allow various test data to be driven out
– Changes in the state of the signal driven through TDO should occur
only on the falling edge of TCK
 Test Access Port
• Test mode select (TMS)
– Sole test control input to the TAP controller
– All boundary-scan test operations (shifting, capturing, and updating of
test data) are controlled by the test sequence applied to this input
– Signals presented at TMS are sampled by the TAP controller on the
rising edge of TCK
• Test reset (TRST∗)
– Optional pin used to reset the TAP controller
– If the TRST∗ pin is implemented, the TAP controller can be
asynchronously reset to the Test–Logic–Reset controller state
– This in turn will reset other boundary-scan logic to the state required
by the Test–Logic–Reset state
 Data Registers and Boundary-Scan Cells
• Standard 1149.1 specifies several test data registers
• Two mandatory test data registers
– Boundary-scan register (BSR)
– Bypass register
• Other registers, (device identification register and design-specific test data
registers) can be added optionally
• BSR is the collection of the boundary-scan cells (BSCs)
• Inserted at the I/O pins of the circuit
A typical boundary-scan cell (BSC)

R1 – Capture Flip flop

R2 – Update Flip flop
 Boundary-scan cell (BSC)
• BSC can be used as either an input or output cell
• As an input BSC,
– IN signal line corresponds to a chip input pad,
– OUT signal line is tied to an input of the internal logic
• As an output BSC
– IN corresponds to output of the internal logic
– OUT is tied to an output pad
• Data driven on the OUT signal are controlled by the Mode signal
– Mode = 0 (normal mode operation)
• Data passes from IN directly to OUT (cell is transparent to functional
logic)
– Mode = 1 (Test mode)
• Test data driven by R2 FF pass through the multiplexer to the OUT
signal
 Boundary-scan cell (BSC)
• Three main test operations—Capture, Shift, and Update
• Controlled by three output signals of the TAP controller: ClockDR, ShiftDR,
and UpdateDR
• Capture operation
– ShiftDR is set to 0
– One clock pulse is applied to ClockDR
– Test data at IN will be captured into the
D-FF (R1)
• Shift operation
– ShiftDR is set to 1
– Clock pulses are applied to ClockDR such that test data can be shifted
in from SI and the test response can be scanned out through SO
– The boundary-scan register is formed by connecting the SO of the
previous cell to the SI of the next cell
 Boundary-scan cell (BSC)
• Capture and Shift operations can also be executed when the cell is in the
normal mode operation
• Update operation
– Data stored in R1 are propagated to R2 by applying a clock pulse to
UpdateDR
– If the Mode is set to 1 at this time, then the output of R2 is connected
to OUT
 Bypass register
Single-bit register that is used to bypass a chip when it is not involved in
the current test operation
Significantly reduce test time required to shift in/out test data through
the long TDI–TDO path.
 TAP Controller (TAPC)
• Control JTAG operation
• 16-state, finite-state machine
• TAPC can change state only on the rising edge of TCK
• The next state is determined by the logic level of TMS (Input)
• The output signals of TAPC determine the test operation to be carried out
• Control signals produced by TAPC
– ClockDR, ShiftDR, UpdateDR
– ClockIR, ShiftIR, UpdateIR
– Select, TCK, and Enable
– Reset∗ (optional)
 TAPC
• The main functions of the TAPC
– Resetting the boundary-scan architecture
– Providing control signals to load instructions into the
instruction register
– Providing signals to perform test functions such as
Capture and Update (application) of test data
– Providing control signals to shift test data from TDI to TDO
 State diagram of TAPC
• The 16 states can be divided
into three parts
• First part (the 2 states at left)
contains the reset and the
“Run-Test/Idle” states
• Second part (the 7 states in
the middle) control the
operations of the data
register
• Third part (the 7 states at
right) control the operations
of instruction register
 TAPC States
Test–Logic–Reset
• Boundary-scan circuitry is disabled
• System operates in its normal mode
• TAPC enters this state whenever a 0 signal is applied to the TRST∗ port
• TAPC can also be synchronously reset;
– Whatever state the TAP controller is in, it will return to this state if a
logic 1 is applied to TMS for five consecutive TCK cycles (i.e., five rising
edges of TCK)
Run-Test/Idle
– The boundary-scan circuitry is waiting for some test operations
synchronized with the TCK (such as BIST) to complete
 TAPC States
• Select-DR-Scan
– Temporary state in preparation for entering the data register
manipulation column
• Capture-DR
– Data can be loaded in parallel to the data registers selected by the
current instruction
– Current test results and normal operation status are captured
• Shift-DR
– Test data are scanned in series through the data registers selected by
the current instruction
– Upon entering this state, the TAP controller will stay in this state as
long as TMS = 0
– For each clock cycle, one bit of test data will be shifted into (out of)
the selected data register through TDI (TDO)
 TAPC States
• Exit-DR
– Also a temporary state
– All parallel-loaded (from the CaptureDR state) or shifted (from the
Shift-DR state) data are held in the selected data register in this state
in preparation to enter the update or pause state
• Pause-DR
– The boundary-scan logic pauses its function here to wait for some
external operations
Example,
– When a long sequence of test data is to be loaded to the chips under
test
– The external tester may have to reload the data from time to time
– This state allows the BSA to wait for more data to shift in/out
 TAPC States
• Exit2-DR
– This state either indicates completion of the current capturing/shifting
operation and allows the TAPC to enter the update state (or)
– Represents the end of the Pause-DR operation, allowing the TAP
controller to go back to the Shift-DR state for more data to shift in/out
• Update-DR
– In this state, data are latched onto the parallel output of the selected
test data registers from the shift register path on the falling edge of
TCK
– Example, the test data stored in the first stage of boundary-scan cells
(R1) are loaded to the second stage (R2) in this state
 JTAG Registers
• Data Register (DR)
– Bypass Register (BR)
– Boundary Scan Register (BSR)
• Instruction Register (IR)

• Registers share same TDI/TDO

Courtesy: Professor James Chien-Mo Li

 Bypass Register
• Purpose: provide short cut from TDI to TDO
• One-bit FF: shift data from TDI to TDO when ShiftDR=1

Courtesy: Professor James Chien-Mo Li

 Bypass Register
• BR provides a single-bit shortcut through the chip
– Shorten boundary scan chain to chip under test
• Example: three chips
– Go through three chips: 24 clocks
– Bypass chip#1: 1+8+8=17 clocks
– Reduce 29% test time
• BR Saves Test Time
 Boundary Scan Registers, BSR
• Purpose : Control system I/O pins; Observe system I/O pins
• BSR consists of Boundary Scan Cells (BSC) Input BSC, Output BSC

Courtesy: Professor James Chien-Mo Li

 Input Boundary Scan Cell, BSC
• Each input BSC has
– 2 FF: capture/scan FF, output FF
– 2 control signals: ShiftDR, Mode
– 2 clocks: ClockDR, UpdateDR

Courtesy: Professor James Chien-Mo Li

Input BSC Operation #1: Normal
Input BSC Operation #2: Scan
Input BSC Operation #3: Update
 Input BSC Operation #4: Capture

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 Output BSC
• Very similar structure to input BSC
• Different direction

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 Instruction Register (IR)
• Used to store the instruction to be executed
How to Load Instruction?
• Initialize JTAG:TMS=1→1→1→1→1
– Test-Logic-Reset state
• Select IR: TMS=0→1→1→0→0
– ShiftIR state
• Load instruction: TMS = 0……0
– keep in ShiftIR state
– Instruction shifted in via TDI
• Finish: TMS = 1→1→0
– back to Run-Test-Idle state
 JTAG Instruction Set
• Four mandatory boundary-scan test instructions
– SAMPLE, PRELOAD, BYPASS, and EXTEST
• How to Load Instruction?
• Apply TMS sequence
– Initialize JTAG: 1→1→1→1→1
– Load instruction: 0→1→1→0→0→0……0→1→1→0
• Number of zeros = Total length of Instruct. Reg.
• JTAG specified Instruction codes
– EXTEST=000…(all zeros)
– BYPASS=111…(all ones)
• Instruction code is shifted in via TDI
 EXTEST
• Purpose: External test
– Test external off-chip wire interconnections among chips
• Step1: Scan in chip#1: shiftDR=1, clockDR…
• Step2: Update chip#1: updateDR
• Step3: Capture chip#2: shiftDR=0, clockDR
• Step4: Scan out chip#2: shiftDR=1, clockDR… Courtesy: Professor James Chien-Mo Li
• Mode always = 1
 Bypass Instruction
• The BYPASS instruction is used to “bypass” the boundary-scan
registers on unused chips
• Prevent long Shift operations
– Bypass scan data from TDI to TDO of a chip
 SAMPLE
• Step1: Capture: ShiftDR=0, ClockDR
• Step2: Scan out: ShiftDR=1, ClockDR …
• Mode = 0 to isolate system logic Courtesy: Professor James Chien-Mo Li
• Does not interfere with normal operation of system logic
 PRELOAD
• Step1: Scan in: ShiftDR=1, ClockDR…
• Step2: Update: UpdateDR
• Mode = 0 to isolate system logic

Courtesy: Professor James Chien-Mo Li

 Optional Instruction
• INTEST
– Selects Boundary scan register
– Internal test of system logic
• RUNBIST
– Runs built-in self-test (BIST)
• IDCODE
– Selects device identification register
 INTEST
• Test on-chip system logic
• Step 1: Scan in: ShiftDR=1 ClockDR …
• Step 2: Update Input BSR: UpdateDR
• Step 3: Capture Output BSR: ShiftDR=0 ClockDR
• Step 4: Scan out: ShiftDR=1 ClockDR …
• Mode = 1

Courtesy: Professor James Chien-Mo Li

 Summary
• JTAG IEEE 1149.1 standard
– Boundary scan for board-level testing
• Components
– TAP ports, TAP controller
– Registers (BSR/BR/IR), Instruction decoder
• Instructions
– Mandatory: EXTEST, BYPASS, SAMPLE/PRELOAD
– Optional: INTEST, RUNBIST, IDCODE …
• JTAG area overhead is small
– Has been widely adopted by industry
– Automatic compiler is widely available
Scan and BIST support with boundary scan
 Board and System-Level Boundary-Scan
Control Architectures
• Problem the designer faces is how to provide test data and
control signals to chips on a board or system
• There exist several test architectures for this purpose
 Single-ring architecture with shared TMS
• All boundary-scan registers of chips are
daisy-chained together
• TMS signal is broadcast to all chips
– All chips will always execute the same
Capture, Shift, or Update operation

• Different chips may still receive different test

instructions through the long TDI–TDO chain
• Example
– Some chips may receive the BYPASS
instruction while others receive the
EXTEST instruction
 Single-ring architecture with separate TMS
• Each chip receives its own TMS signal
• Can provide different instructions to
different chips as well as operate the chips
with different control signals
• Virtually all chips can be tested
independently

• Easy to implement
• Sufficient to test chips on a single board
 Single-ring architecture
• For a system or backplane that contains a number of boards where each
board contains ICs with boundary-scan architectures
– single-ring configuration may become inefficient due to the long and
often cumbersome scan chain that has to pass through all chips in all
boards

• This architecture also runs into problems when boards are removed or
added, as some type of jumper or bridge is required when a board is
removed; otherwise, the chain will be broken
 Star (multi-ring) Architecture
• In the star-architecture, every board in the system gets a dedicated
set of boundary-scan data and control signals
• Though test for chips in each board can be efficiently carried out as
if only a single board exists, such an approach requires a larger
number of (connection) traces in the backplane
• The advantage of the ring and star architectures is that they do not
require any additional components or new protocols beyond what
is required by the boundary-scan specification
• This makes them straightforward to implement, but in a large
multiple-board system they are often too cumbersome to use.
Star (multi-ring) Architecture
 Multidrop architecture
• Uses only one set of 1149.1
data and control signals
• Wired in parallel to each board
in the system
• An addressable gateway device
must be implemented on each
board
– To ensure that boundary-
scan operations are applied
to only one board at a time
• The multidrop architecture is
the one used most in industry;