UNIVERSITY OF SANTO TOMAS

ECE21117: SWITCHING CIRCUITS AND LOGIC DESIGN

MODULE 6A
CLK
DESIGN OF DIGITAL SYSTEMS:
SYNCHRONOUS SEQUENTIAL
LOGIC CIRCUIT DESIGN

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SEQUENTIAL LOGIC CIRCUITS

SEQUENTIAL vs. COMBINATIONAL LOGIC CIRCUIT
The output of a Combinational Logic Circuit depends ONLY
and IMMEDIATELY on their inputs. Hence, it has no memory
element.
ADDERS MULTIPLEXERS DECODERS
SUBTRACTERS DEMULTIPLEXERS ENCODERS

On the other hand, Sequential Logic Circuits, act as storage

elements and have memory.
REGISTERS COUNTERS
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SEQUENTIAL LOGIC CIRCUITS

SEQUENTIAL CIRCUIT BLOCK DIAGRAM

Fig. 3. Block Diagram of a Sequential Circuit

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SEQUENTIAL LOGIC CIRCUITS

TYPES OF SEQUENTIAL CIRCUIT
1. Synchronous Sequential Circuit
This circuit employs signals that affect the storage elements at
only discrete instants of time. Synchronization is achieved by a
timing device called a clock generator.

2. Asynchronous Sequential Circuit

This circuit depends upon the input signals at any instant of
time and the order in which inputs change.

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SEQUENTIAL LOGIC CIRCUITS

TYPES OF SEQUENTIAL CIRCUIT
1. Synchronous Sequential Circuit

The clock pulses or CLK determine

the computational activity that will
occur within the circuit and what
changes will take place affecting
the storage elements and outputs.
Fig. 4. Block Diagram of a Synchronous
Sequential Circuit

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SEQUENTIAL LOGIC CIRCUITS

FORMS OF TRIGGERING OR CLOCKING
1. Level Clocking
This is a type of triggering wherein the output of the flip flop
responds during the high (or low) level of the clock signal.
CLK 1

1
D
0
Fig. 5. Example of a Timing Diagram
Determine Q For a Positive Level Clocked D Latch
1

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SEQUENTIAL LOGIC CIRCUITS

FORMS OF TRIGGERING OR CLOCKING
2. Edge Triggering
This is a type of triggering wherein the flip flop produces
output only on the rising (or falling) edge of the clock signal.
CLK 1

1
D
0
Fig. 6. Example of a Timing Diagram
Determine Q For a Positive Edge Triggered D Flip Flop
1

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SEQUENTIAL LOGIC CIRCUITS

FORMS OF TRIGGERING OR CLOCKING
1. Level Clocking

Fig 7a. Positive Level Clocking Fig 7b. Negative Level Clocking

2. Edge Triggering

Fig 7c. Positive Edge Triggering Fig 7d. Negative Edge Triggering
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SEQUENTIAL LOGIC CIRCUITS

REVIEW ON FLIP-FLOPS
Flip Flops are synchronous bistable devices. Its content
remains in one of the two possible states until triggered into
another.
1. SR FLIP FLOP 3. D FLIP FLOP
2. JK FLIP FLOP 4. T FLIP FLOP
It is said to be synchronous because its output changes state
only at a specified point (either leading or trailing edge) on the
triggering input called clock or clk.
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SEQUENTIAL LOGIC CIRCUITS

REVIEW ON FLIP-FLOPS
1. SR Flip Flop Table 1. Characteristic Table of
SR Flip Flop

Q(t) S R Q(t+1)
0 0 0 0
0 0 1 0
Fig 8. Schematic Symbol of a 0 1 0 1
Positive Edge Triggered SR Flip Flop
0 1 1 ind
1 0 0 1
𝑸 𝒕 + 𝟏 = 𝑺 + 𝑸𝑹′ 1 0 1 0
Eqn. 1. Characteristic Equation 1 1 0 1
Of SR Flip Flop 1 1 1 ind
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SEQUENTIAL LOGIC CIRCUITS

REVIEW ON FLIP-FLOPS
Table 2. Characteristic Table of
2. JK Flip Flop JK Flip Flop

Q(t) J K Q(t+1)
0 0 0 0
0 0 1 0
Fig 9. Schematic Symbol of a 0 1 0 1
Positive Edge Triggered JK Flip Flop
0 1 1 1
1 0 0 1
𝑸 𝒕 + 𝟏 = 𝑱𝑸′ + 𝑲′ 𝑸 1 0 1 0
Eqn. 2. Characteristic Equation 1 1 0 1
Of JK Flip Flop 1 1 1 0
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SEQUENTIAL LOGIC CIRCUITS

REVIEW ON FLIP-FLOPS
Table 3. Characteristic Table of
3. D Flip Flop D Flip Flop

Q(t) D Q(t+1)
0 0 0
0 1 1
Fig 10. Schematic Symbol of a 1 0 0
Positive Edge Triggered D Flip Flop
1 1 1

𝑸 𝒕+𝟏 =𝑫
Eqn. 3. Characteristic Equation
Of D Flip Flop

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SEQUENTIAL LOGIC CIRCUITS

REVIEW ON FLIP-FLOPS
Table 4. Characteristic Table of
4. T Flip Flop T Flip Flop

Q(t) T Q(t+1)
0 0 0
0 1 1
Fig 11. Schematic Symbol of a 1 0 1
Positive Edge Triggered T Flip Flop
1 1 0

𝑸 𝒕 + 𝟏 = 𝑻𝑸′ + 𝑻′ 𝑸
Eqn. 4. Characteristic Equation
Of T Flip Flop

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SEQUENTIAL LOGIC CIRCUITS

REVIEW ON FLIP-FLOPS

What is an EXCITATION TABLE and why is it important in the

design process?

An excitation table lists the required inputs for a given change

of state.
This is important in the design process to determine the flip
flop input conditions that will cause the required transition.
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SEQUENTIAL LOGIC CIRCUITS

REVIEW ON FLIP-FLOPS

What is an EXCITATION TABLE and why is it important in the

design process?
Table 5. Excitation Table of SR Flip Flop Table 6. Excitation Table of JK Flip Flop

Q(t) Q(t+1) S R Q(t) Q(t+1) J K

0 0 0 x 0 0 0 x
0 1 1 0 0 1 1 x
1 0 0 1 1 0 x 1
1 1 x 0 1 1 x 0

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SEQUENTIAL LOGIC CIRCUITS

REVIEW ON FLIP-FLOPS

What is an EXCITATION TABLE and why is it important in the

design process?
Table 7. Excitation Table of D Flip Flop Table 8. Excitation Table of T Flip Flop

Q(t) Q(t+1) D Q(t) Q(t+1) T

0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0

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SEQUENTIAL LOGIC CIRCUITS

DESIGN MODELLING

The relationship that exists among the inputs, outputs,

present states, and next states can be specified by any of the
following:
1. STATE DIAGRAM
2. STATE TABLE
3. STATE EQUATION

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SEQUENTIAL LOGIC CIRCUITS

DESIGN MODELLING
0/0 0/0
1. State Diagram
1/1
A state diagram is a graphical 00 10

representation wherein a state is

represented by a circle; and the 1/0 0/0

transition between states is

indicated by directed lines (or arcs) 01
0/0
11

connecting the circles.

1/0 1/0
Fig 12. Sample State Diagram
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SEQUENTIAL LOGIC CIRCUITS

DESIGN MODELLING
Table 9. Equivalent State Table from the Previous Diagram
2. State Table Present Input Next Output
State State
A state table is a
A(t) B(t) x A(t+1) B(t+1) y
tabulated representation 0 0 0 0 0 0
which consists of input, 0 0 1 0 1 0
present state, next state, 0 1 0 1 1 0

and output. 0 1 1 0 1 0
1 0 0 1 0 0

STATE STATE 1 0 1 0 0 1
1 1 0 1 0 0
DIAGRAM TABLE
1 1 1 1 1 0
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SEQUENTIAL LOGIC CIRCUITS

DESIGN MODELLING
Table 9. Equivalent State Table from the Previous Diagram
2. State Table Present Input Next Output
Table 10. Another Way to Write a State State
State Table (for State Reduction) A(t) B(t) x A(t+1) B(t+1) y
Present Next Output 0 0 0 0 0 0
State State
0 0 1 0 1 0
A(t) B(t) x=0 x=1 x=0 x=1
0 1 0 1 1 0
00 00 01 0 0
0 1 1 0 1 0
01 11 01 0 0
1 0 0 1 0 0
10 10 00 0 1
1 0 1 0 0 1
11 10 11 0 0
1 1 0 1 0 0
1 1 1 1 1 0
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SEQUENTIAL LOGIC CIRCUITS

DESIGN MODELLING

3. State Equation
A state equation is an expression that specifies the conditions
of flip flop’s next state transition as function of the present state
and input variables. Other name for Characteristic Equation.

𝑸 𝒕 + 𝟏 = 𝑭{𝑸 𝒕 , 𝒙𝟏, 𝒙𝟐, … , 𝒙𝒏}

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SEQUENTIAL LOGIC CIRCUITS

DESIGN APPROACH
Sample Problem No. 1 0/1

Based on the given state 00

diagram, design a sequential 1/0 0/0

circuit using JK Flip Flop.

1/1 01 11 1/0

0/0 0/1
10

Fig 13. State Diagram for

Sample Problem No. 1 1/1

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SEQUENTIAL LOGIC CIRCUITS

DESIGN APPROACH
STEP 1: 0/1

Identify the given. This can 00

be in a form of a word description 1/0 0/0

of the circuit behavior and may be

1/1 01 11 1/0
accompanied by a state diagram, a
timing diagram, or other pertinent 0/0 0/1
information. 10

1/1

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SEQUENTIAL LOGIC CIRCUITS

DESIGN APPROACH
Table 11. Equivalent State Table of Sample Problem No. 1
STEP 2: Present Input Next Output
State State
Obtain the state table.
A(t) B(t) x A(t+1) B(t+1) y
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 1
1 0 0 1 1 1
1 0 1 1 0 1
1 1 0 0 0 0
1 1 1 1 1 0
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SEQUENTIAL LOGIC CIRCUITS

DESIGN APPROACH
STEP 3: Table 12. Another Way to Write a
State Table (for State Reduction)
The number of states may Present Next Output
be reduced by State Reduction State State
Method. A(t) B(t) x=0 x=1 x=0 x=1
NOTE: 00 00 01 1 0
01 10 01 0 1
Two states are said to be equivalent if,
10 11 10 1 1
for each member of the set of inputs, they give
exactly the same output and send the circuit 11 00 11 0 0
either to the same state or to an equivalent
state.
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SEQUENTIAL LOGIC CIRCUITS

DESIGN APPROACH
STEP 4:
Derive the circuit excitation and output tables based on the
type of flip flop to be used. To do this, determine how many flip
flops are to be used.

𝑵 = 𝟐𝒏 where:
n = number of bits or flip flops to be used
Eqn. 5. Relationship of the N = total number of states
number of bits and number of
states

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Table 13. Circuit Excitation and Output Table Using JK Flip Flop
PRESENT
PRESENT NEXT
NEXT
INPUT
INPUT FLIP
FLIP FLOP INPUTS
FLOP INPUTS OUTPUT
OUTPUT
STATE
STATE STATE
STATE

A(t) B(t) x A(t+1)

A(t+1) B(t+1)
B(t+1) JA KAA JB KBB y
0 0 0 0 0 0 x 0 x 1
0 0 1 0 1 0 x 1 x 0
0 1 0 1 0 1 x x 1 0
0 1 1 0 1 0 x x 0 1
1 0 0 1 1 x 0 1 x 1
1 0 1 1 0 x 0 0 x 1
1 1 0 0 0 x 1 x 1 0
1 1 1 1 1 x 0 x 0 0
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SEQUENTIAL LOGIC CIRCUITS

DESIGN APPROACH

STEP 5:
Using k-map or any other simplification method, derive the
circuit output functions and the flip flop input functions or
equations. Do this for both the flip flop inputs and output/s.

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Bx Bx
A 00 01 11 10 A 00 01 11 10
0 1 0 1 x x
1 x x x x 1 1 x x Bx
A 00 01 11 10
𝑱𝑨 = 𝑩𝒙′ 𝑱𝑩 = 𝑨′ 𝒙 + 𝑨𝒙′ = 𝑨 ⊕ 𝒙 0 1 1

Bx Bx 1 1 1
A 00 01 11 10 A 00 01 11 10
0 x x x x 0 x x 1 𝒚 = 𝑨′𝑩𝒙 + 𝑩′ 𝒙′ + 𝑨𝑩′
1 1 1 x x 1 Output Equation

𝑲𝑨 = 𝑩𝒙′ 𝑲𝑩 = 𝒙′
JK Flip Flop Input Equations
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SEQUENTIAL LOGIC CIRCUITS

DESIGN APPROACH
STEP 6: Draw the sequential logic circuit.

Fig 14. Equivalent Sequential Logic

Circuit Design of Sample
Problem No. 1
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SEQUENTIAL LOGIC CIRCUITS

DESIGN APPROACH
Summary of Design Approach
STEP 1: Identify the given.
STEP 2: Obtain the state table.
STEP 3: Reduce number of states if possible.
STEP 4: Derive the circuit excitation and output tables
based on the type of flip flop to be used
STEP 5: Derive the circuit output functions and the flip
flop input functions.
STEP 6: Draw the circuit.
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SEQUENTIAL LOGIC CIRCUITS

DESIGN APPROACH

Alternate Solution:
STEP 1: Use the characteristic equation of JK Flip-flop.
STEP 2: No need for excitation table.
STEP 3: No need for K-map to determine the input to FF
equations.

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SEQUENTIAL LOGIC CIRCUITS

DESIGN APPROACH
0/1
Seatwork No. 1
00
Based on the given state 1/0 0/0
diagram, design a sequential
circuit using D Flip Flop. 1/1 01 11 1/0

0/0 0/1
10

Fig 13. State Diagram for

Seatwork No. 1 1/1
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SEQUENTIAL LOGIC CIRCUITS

DESIGN APPROACH

Assignment No. 1
Design a sequential circuit with two T Flip Flops, A and B, and
two inputs, E and x. If E=0, the circuit remains in the same state
regardless of the value of x. When E=1 and x=1, the circuit goes
through the state transitions from 00 to 01 to 10 to 11 back to 00,
and repeats. When E=1 and x=0, the circuit goes through the state
transition from 00 to 11 to 10 to 01 back to 00, and repeats.

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SEQUENTIAL LOGIC CIRCUITS

STATE REDUCTION AND ASSIGNMENT
State Reduction Algorithms are concerned with procedures
for reducing the number of states in state table, while keeping the
external input-output requirements unchanged.
NOTE:
Two states are said to be equivalent if, for each member of the set of inputs, they
give exactly the same output and send the circuit either to the same state or to an
equivalent state.

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SEQUENTIAL LOGIC CIRCUITS

STATE REDUCTION AND ASSIGNMENT

Sample Problem No. 2

Based on the given state diagram:
a) Generate the input-output sequence
b) Reduce the number of states in the given table
c) Regenerate the output sequence using the
reduced table or state diagram
d) Draw the reduced state diagram
NOTE:
Consider the input sequence 01010110100 starting Fig 15. State Diagram for Sample
from a. Problem No. 2

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SEQUENTIAL LOGIC CIRCUITS

STATE REDUCTION AND ASSIGNMENT
a) Generate the input-output sequence
NOTE:
Consider the input sequence 01010110100
starting from a.

State a a b c d e f f g f g a
Input 0 1 0 1 0 1 1 0 1 0 0
output 0 0 0 0 0 1 1 0 1 0 0

Fig 15. State Diagram for Sample

Problem No. 2

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SEQUENTIAL LOGIC CIRCUITS

STATE REDUCTION AND ASSIGNMENT
Table 14. Equivalent State Table of
b) Reduce the number of states in the Sample Problem No. 2
given table Present Next Output
State State
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
d=f e a f 0 1
f g f 0 1
e=g
g a f 0 1
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SEQUENTIAL LOGIC CIRCUITS

STATE REDUCTION AND ASSIGNMENT
Table 14. Equivalent State Table of
b) Reduce the number of states in the Sample Problem No. 2
given table Present Next Output
State State
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
d=f e a f 0 1
f g f 0 1
e=g
g a f 0 1
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SEQUENTIAL LOGIC CIRCUITS

STATE REDUCTION AND ASSIGNMENT
Table 15. Reduced State Table of
b) and d) Reduce the number of states Sample Problem No. 2
in the given table and draw the reduced Present Next Output
diagram State State
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
EFFECT: From a total of 7 states (or consumption of 3 FFs), the number of
Fig 16. Reduced State Diagram for states is reduced to 5 states. However, 3 FFs are still needed.
Sample Problem No. 2
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SEQUENTIAL LOGIC CIRCUITS

STATE REDUCTION AND ASSIGNMENT
c) Regenerate the output sequence using the
reduced table or state diagram
NOTE:
Consider the input sequence 01010110100 starting
from a.
State a a b c d e f f g f g a
Input 0 1 0 1 0 1 1 0 1 0 0
output 0 0 0 0 0 1 1 0 1 0 0

State a a b c d e d d e d e a Fig 16. Reduced State Diagram for

Input 0 1 0 1 0 1 1 0 1 0 0 Sample Problem No. 2
output 0 0 0 0 0 1 1 0 1 0 0
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SEQUENTIAL LOGIC CIRCUITS

STATE REDUCTION AND ASSIGNMENT
Table 15. State Table for Seatwork No. 2

Seatwork No. 2 Present Next State Output

State x=0 x=1 x=0 x=1
Based on the given state table:
a) Generate the input-output sequence a f b 0 0
b) Reduce the number of states in the given table b d c 0 0
c) Regenerate the output sequence using the reduced c f e 0 0
table or state diagram
d g a 1 0
d) Draw the reduced state diagram
e d c 0 0
e) Design a sequential logic circuit from the reduced
state diagram. Use D Flip Flop for the design. f f b 1 1
NOTE: g g h 0 1
Consider the input sequence 01110010011 starting from h g a 1 0
a.
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SEQUENTIAL LOGIC CIRCUITS

STATE REDUCTION AND ASSIGNMENT

Present Next State Output

State x=0 x=1 x=0 x=1
a f b 0 0
State
b d c 0 0 a

c f e 0 0 Input
0 1 1 1 0 0 1 0 0 1 1
d g a 1 0
e d c 0 0 Output

f f b 1 1
g g h 0 1
h g a 1 0

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SEQUENTIAL LOGIC CIRCUITS

STATE REDUCTION AND ASSIGNMENT

Present Next State Output Present Next State Output

State x=0 x=1 x=0 x=1 State x=0 x=1 x=0 x=1
a f b 0 0
b d c 0 0
c f e 0 0
d g a 1 0
e d c 0 0
f f b 1 1
g g h 0 1
h g a 1 0

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SEQUENTIAL LOGIC CIRCUITS

STATE REDUCTION AND ASSIGNMENT

Present Next State Output

State x=0 x=1 x=0 x=1 State
a
a f b 0 0
Input
b d a 0 0 0 1 1 1 0 0 1 0 0 1 1
d g a 1 0 Output
f f b 1 1
g g d 0 1

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SEQUENTIAL LOGIC CIRCUITS

STATE REDUCTION AND ASSIGNMENT

Present Next State Output

State x=0 x=1 x=0 x=1
a f b 0 0
b d a 0 0
d g a 1 0
f f b 1 1
g g d 0 1

Note:
a → 000 b → 001
d → 011 f → 101
g → 110

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Present State Input Next State Flip Flop Inputs Output

A(t) B(t) C(t) x A(t+1) B(t+1) C(t+1) DA DB DC y
0 0 0 0
NS Output
PS 0 0 0 1
x=0 x=1 x=0 x=1 0 0 1 0
0 0 1 1
000 101 001 0 0
0 1 0 0
001 011 000 0 0 0 1 0 1

011 110 000 1 0 0 1 1 0

0 1 1 1
101 101 001 1 1 1 0 0 0
110 110 011 0 1 1 0 0 1
1 0 1 0
1 0 1 1
Note: 1 1 0 0
a → 000 b → 001 1 1 0 1
d → 011 f → 101 1 1 1 0
g → 110 1 1 1 1

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SEQUENTIAL LOGIC CIRCUITS

STATE REDUCTION AND ASSIGNMENT

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Present State Input Next State Flip Flop Inputs Output

A(t) B(t) C(t) x A(t+1) B(t+1) C(t+1) DA DB DC y

0 0 0 0
NS Output
0 0 0 1
PS
x=0 x=1 x=0 x=1 0 0 1 0
0 0 1 1
000 101 001 0 0
0 1 0 0
001 011 000 0 0 0 1 0 1
0 1 1 0
011 110 000 1 0
0 1 1 1
101 101 001 1 1 1 0 0 0

110 110 011 0 1 1 0 0 1

1 0 1 0
1 0 1 1
Note: 1 1 0 0
a → 000 b → 001 1 1 0 1
d → 011 f → 101
1 1 1 0
g → 110
1 1 1 1

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SEQUENTIAL LOGIC CIRCUITS

STATE REDUCTION AND ASSIGNMENT

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SEQUENTIAL LOGIC CIRCUITS

REGISTERS AND COUNTERS

Registers are composed of group of flip flops, each one shares

a common clock and is capable of storing one bit of information or
modify stored binary word.
Counters, on the other hand, are registers that go through a
predetermined sequence of binary states. It counts the number of
clock pulses arriving at its input.

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4-bit Buffer Register
When RESET = 0, the 4-bit Register is forced to reset. When
RESET = 1, Q3Q2Q1Q0  X3X2X1X0 is stored through Parallel Loading.
X3 X2 X1 X0

Q3 D3 Q2 D2 Q1 D1 Q0 D0

CLK CLK CLK CLK

R R R R

RESET

Fig 17. 4-bit Buffer Register

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4-bit Controlled Buffer Register
X3 X2 X1 X0

LOAD
When LOAD = 0, data will
be retained.
When LOAD = 1,
Q3Q2Q1Q0  X3X2X1X0 is
Q3 D3 Q2 D2 Q1 D1 Q0 D0
stored through Parallel
CLK CLK CLK CLK
Loading.
R R R R

RESET
Fig 18. 4-bit Controlled Buffer Register
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Shift Registers (Shift Left)

Storing of word in the shift register is done through Serial
Loading, wherein one bit is entered per clock pulse.
Q3 D3 Q2 D2 Q1 D1 Q0 D0 Xin

CLK CLK CLK CLK

R R R R

RESET

Fig 19. Shift Left Register

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Shift Registers (Shift Right)
Storing of word in the shift register is done through Serial Loading,
wherein one bit is entered per clock pulse.

Q3 D3 Q2 D2 Q1 D1 Q0 D0
Xin

CLK CLK CLK CLK

R R R R

RESET

Fig 20. Shift Right Register

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4-bit Controlled Shift Register
SHL
Xin
When SHL = 0, data will
be retained.
When SHL = 1, X3X2X1X0 is
stored through Serial
Q3 D3 Q2 D2 Q1 D1 Q0 D0
Loading.
CLK CLK CLK CLK

R R R R

RESET
Fig 21. 4-bit Controlled Shift Register
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4-bit Shift Register with Broadside Load
X3 X2 X1 X0

LOAD
SHL
Xin

Q3 D3 Q2 D2 Q1 D1 Q0 D0

CLK CLK CLK CLK

R R R R

RESET

Fig 22. 4-bit Shift Register with Broadside Load

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Design of Binary Counters

The design of binary counters
are typically done using either T or
JK Flip Flop.

Fig 23. State Diagram of a 3-bit

Binary Counter
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Table 16. State Table for a 3-bit Binary Counter

Flip Flop
Present State Next State
Inputs

Q2(t) Q1(t) Q0(t) Q2(t+1) Q1(t+1) Q0(t+1) T2 T1 T0

0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
Fig 23. State Diagram of a 3-bit 1 1 0 1 1 1 0 0 1
Binary Counter
1 1 1 0 0 0 1 1 1

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Q2 T2 Q1 T1 Q0 T0 HIGH

CLK CLK CLK

R R R

RESET

Fig 24. 3-bit Binary Counter Circuit

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Sample Problem No. 3

Design a mod-6 synchronous counter using T Flip Flops.

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Flip Flop
Present State Next State
Inputs

Q2(t) Q1(t) Q0(t) Q2(t+1) Q1(t+1) Q0(t+1) T2 T1 T0

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Assignment No. 2
Design a 3-bit counter with the following repeated sequence:
0, 1, 3, 5, 7. Use JK Flip Flops.

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4-bit Binary Ripple Counter
Count pulse is only applied at the FF holding the LSB. All T flip
flops are always in toggle but not at the same time. When 1111 is
reached, the counter goes back to 0000.
HIGH

Q3 T3 Q2 T2 Q1 T1 Q0 T0

CLK CLK CLK CLK COUNT

PULSE
R R R R

RESET
Fig 25. 4-bit Binary Ripple Counter
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Controlled Ripple Counter

COUNT

Q3 J3 Q2 J2 Q1 J1 Q0 J0

K3 K2 K1 K0

Fig 26. Controlled Ripple Counter

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4-bit Binary Synchronous Counter Q0 is always in toggle
Q1 will toggle when Q0 is 1
Q2 will toggle when Q1Q0 is 1
Q3 will toggle when Q2Q1Q0 is 1

Q3 J3 Q2 J2 Q1 J1 Q0 J0 HIGH

CLK CLK CLK CLK

R K3 R K2 R K1 R K0

RESET

Fig 27. 4-bit Binary Synchronous Counter

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Controlled Synchronous Counter
COUNT

Q3 J3 Q2 J2 Q1 J1 Q0 J0

K3 K2 K1 K0

CLR’

Fig 28. Controlled Synchronous Counter

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4-bit Ring Counter
This is a type of counter that resembles a shift register which is
initiated in such that only one of its flip-flops is at high state while the rest
are in low state.

Q3 D3 Q2 D2 Q1 D1 Q0 PR D0

CLK CLK CLK CLK

R R R

RESET

Fig 29. 4-bit Ring Counter

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Modulo-10 Counter (Decade Counter)

Fig 30. Decade Counter

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P3 P2 P1 P0
Presettable
Counter
LOAD

HIGH

Q3 J3 Q2 J2 Q1 J1 Q0 J0

Fig 31. K3 K2 K1 K0
Presettable
Counter

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Sample Problem No. 4

A ripple counter has 16 flip-flops, each with a propagation
delay time of 25 ns.
a) If the count is Q = 0111 1111 1111 1111, how long after the
next active clock edge before
Q = 1000 0000 0000 0000?
b) What is the maximum decimal count for the said counter?

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Assignment No. 3
Design a 4-bit synchronous counter with D flip-flops.

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ECE21117 MODULE 6
REFERENCES

o Digital Design by Morris Mano

o Digital Computer Electronics by Malvino and Brown
o Computer Systems Organization and Architecture by John D. Carpinelli
o Digital design : With an introduction to the Verilog HDL / M. Morris Mano, Michael D. Ciletti
o Lecture Notes of Angelo R dela Cruz, Kanny Krizzy D. Serrano, Cristine Jin D.S. Estrada

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