Synthesis

Tool Commands
Version S-2021.06-SP2, September 2021
Synthesis Tool Commands Version S-2021.06-SP2

Copyright Notice and Proprietary Information

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2
Synthesis Tool Commands Version S-2021.06-SP2

Contents

acs_get_parent_partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 ..........

acs_read_hdl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 ..........
acs_report_user_messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ...........
add_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 ..........
add_parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ...........
add_pg_pin_to_db . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 ..........
add_pg_pin_to_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 ..........
add_port_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 ..........
add_power_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 ..........
add_pst_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ...........
add_row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 ..........
add_state_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ...........
add_supply_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 ...........
add_to_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 ..........
add_to_rp_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 ..........
alias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
..........
alib_analyze_libs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 ..........
all_active_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ...........
all_clock_gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ...........
all_clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 ..........
all_connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ...........
all_critical_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ..........
all_critical_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ...........
all_designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 ..........
all_dont_touch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 ..........
all_drc_violated_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 ..........
all_fanin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 ..........
all_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 ..........
all_high_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ...........
all_ideal_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ...........
all_inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 ..........
all_isolation_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 ..........
all_level_shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ...........
all_macro_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 ...........
all_outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 ..........
all_physical_only_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 ...........
all_registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 ..........
all_rp_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 ..........
all_rp_hierarchicals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 ...........
all_rp_inclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 ...........

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Synthesis Tool Commands Version S-2021.06-SP2

all_rp_instantiations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 ..........

all_rp_references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 ..........
all_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 ..........
all_self_gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 ...........
all_test_modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 ...........
all_threestate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 ..........
all_tieoff_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 ...........
all_upf_repeater_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 ..........
analyze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 ...........
analyze_datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 ...........
analyze_datapath_extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 ..........
analyze_dw_power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 ...........
analyze_minpwr_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 ..........
analyze_mv_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 ..........
analyze_mv_feasibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 ..........
analyze_rtl_congestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 ...........
append_to_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 ..........
apply_clock_gate_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 ..........
apply_power_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 ...........
apropos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 ..........
as_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 ...........
associate_supply_set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 ...........
balance_buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 ..........
balance_registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 ...........
break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179..........
capture_detailed_script_runtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 ..........
cd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
..........
cell_of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
...........
change_link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 ..........
change_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 ...........
change_selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 ..........
characterize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 ..........
check_bindings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 ...........
check_block_abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 ..........
check_bsd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 ..........
check_budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 ...........
check_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 ...........
check_error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 ..........
check_implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 ..........
check_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 ..........
check_license . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 ...........
check_mv_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 ...........
check_rp_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 ..........
check_scan_def . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 ..........
check_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 ...........

Contents 4
Synthesis Tool Commands Version S-2021.06-SP2

check_synlib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 ...........

check_target_library_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 ..........
check_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 ..........
check_tlu_plus_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 ...........
check_upf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250...........
clean_buffer_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 ..........
close_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
..........
close_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255 ..........
collections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
...........
compare_collections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 ...........
compare_delay_calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 ..........
compare_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 ..........
compare_supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 ..........
compile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
...........
compile_exploration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 ..........
compile_prefer_runtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 ..........
compile_ultra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 ..........
compute_polygons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 ..........
connect_logic_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 ..........
connect_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 ..........
connect_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 ..........
connect_supply_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 ..........
continue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
..........
convert_from_polygon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 ..........
convert_pg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 ..........
convert_to_polygon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 ..........
copy_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 ...........
copy_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 ...........
copy_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
..........
copy_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 ...........
cputime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
...........
create_auto_path_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 ...........
create_block_abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 ..........
create_bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 ..........
create_bsd_patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 ...........
create_buffer_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 ..........
create_bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330 ..........
create_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333..........
create_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 ..........
create_command_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 ..........
create_core_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 ...........
create_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 ...........
create_dft_netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345 ..........
create_die_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 ..........
create_failsafe_fsm_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 ...........

Contents 5
Synthesis Tool Commands Version S-2021.06-SP2

create_failsafe_fsm_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350 ..........

create_generated_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 ...........
create_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
..........
create_link_block_abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360 ..........
create_logic_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 ...........
create_logic_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364 ..........
create_missing_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365 ..........
create_multibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368 ..........
create_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372 ..........
create_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
..........
create_net_search_pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 ..........
create_net_shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 ...........
create_operating_conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383 ..........
create_pin_guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385 ..........
create_placement_blockage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 ..........
create_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
...........
create_power_domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393 ..........
create_power_state_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 ...........
create_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399 ..........
create_pst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
...........
create_qor_snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404 ..........
create_qtm_constraint_arc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 ...........
create_qtm_delay_arc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410 ..........
create_qtm_drive_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 ...........
create_qtm_generated_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 ...........
create_qtm_insertion_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 ...........
create_qtm_load_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420 ..........
create_qtm_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422 ..........
create_qtm_path_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424 ..........
create_qtm_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 ...........
create_register_bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429 ..........
create_route_guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431 ..........
create_rp_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 ...........
create_safety_core_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .440 ..........
create_safety_core_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 ...........
create_safety_error_code_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 ...........
create_safety_error_code_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 ...........
create_safety_register_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 ...........
create_safety_register_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451 ..........
create_scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .454 ..........
create_site_row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .456 ..........
create_supply_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .459 ..........
create_supply_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 ...........
create_supply_set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .463 ..........
create_terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 ...........

Contents 6
Synthesis Tool Commands Version S-2021.06-SP2

create_test_protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 ...........

create_track . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470 ..........
create_user_shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 ...........
create_via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 ...........
create_via_master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .481 ..........
create_via_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 ...........
create_voltage_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 ...........
create_wiring_keepouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .489 ..........
cross_probing_filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .491 ..........
current_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .493 ..........
current_design_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 ...........
current_dft_partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .496 ..........
current_instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 ...........
current_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501...........
current_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 ...........
current_scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 ...........
current_test_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .507 ..........
cut_row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509...........
date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
..........
dc_allocate_budgets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 ...........
decrypt_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .516 ..........
define_design_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .518 ..........
define_dft_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 ...........
define_dft_partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 ...........
define_libcell_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .527 ..........
define_name_maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .529 ..........
define_name_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 ...........
define_power_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542 ..........
define_preserve_user_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .544 ..........
define_proc_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .546 ..........
define_routing_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 ...........
define_scaling_lib_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .558 ..........
define_test_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 ...........
define_user_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564 ..........
delete_operating_conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 ..........
derive_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .569 ..........
describe_state_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .571 ..........
dft_drc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .574
..........
disconnect_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 ...........
distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .579 ..........
drive_of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
...........
duplicate_logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .583 ..........
echo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .586
..........
elaborate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588...........
enable_redirect_bg_commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 ...........

Contents 7
Synthesis Tool Commands Version S-2021.06-SP2

enable_write_lib_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .593 ..........

encrypt_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .595 ..........
error_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .597 ..........
estimate_fp_black_boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 ...........
exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .602
..........
extend_mw_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .603 ..........
extract_physical_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .605 ..........
extract_rc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .609 ..........
filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
...........
filter_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .614 ..........
find . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .617
..........
find_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .623 ..........
fix_mv_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 ...........
foreach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .628 ..........
foreach_in_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .630 ..........
generate_mv_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 ...........
generate_rtl_upf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 ...........
get_alternative_lib_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 ...........
get_always_on_logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .640 ..........
get_app_var . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .642 ..........
get_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .645 ..........
get_bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 ...........
get_buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .651 ..........
get_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 ...........
get_clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 ..........
get_clusters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .661 ..........
get_command_option_values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .663 ..........
get_cross_probing_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .665 ..........
get_defined_commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 ...........
get_design_lib_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 ...........
get_designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .672 ..........
get_dft_hierarchical_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .675 ..........
get_die_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .678 ..........
get_dont_touch_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .680 ..........
get_dont_touch_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .682 ..........
get_flat_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .684 ..........
get_flat_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 ...........
get_flat_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 ...........
get_generated_clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .694 ..........
get_gui_stroke_bindings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .697 ..........
get_latch_loop_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 ...........
get_lib_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .701 ..........
get_lib_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .703 ..........
get_lib_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .706 ..........
get_libs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 ...........

Contents 8
Synthesis Tool Commands Version S-2021.06-SP2

get_license . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
...........
get_magnet_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 ...........
get_matching_nets_for_pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .716 ..........
get_message_ids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 ...........
get_message_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .721 ..........
get_multibits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
...........
get_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .725
..........
get_object_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .730 ..........
get_path_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 ..........
get_physical_hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 ...........
get_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .735
..........
get_placement_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 ...........
get_placement_blockages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .739 ..........
get_polygon_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 ...........
get_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
...........
get_power_derate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .746 ..........
get_power_domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 ...........
get_power_switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 ...........
get_references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .754 ..........
get_related_supply_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .756 ..........
get_route_zrt_common_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 ...........
get_route_zrt_global_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 ...........
get_rp_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .762 ..........
get_safety_core_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 ...........
get_safety_core_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .766 ..........
get_safety_error_code_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .767 ..........
get_safety_error_code_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .768 ..........
get_safety_register_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .769 ..........
get_safety_register_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 ...........
get_scan_cell_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 ...........
get_scan_cells_of_chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .773 ..........
get_scan_chain_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .775 ..........
get_scan_chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 ..........
get_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 ...........
get_selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .780..........
get_shift_register_chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .783 ..........
get_site_rows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785 ...........
get_supply_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 ...........
get_supply_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .791 ..........
get_switching_activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 ...........
get_terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .796 ..........
get_timing_paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .799 ..........
get_tracks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
...........
get_via_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .809 ..........
get_zero_interconnect_delay_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .811 ..........

Contents 9
Synthesis Tool Commands Version S-2021.06-SP2

getenv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
...........
group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .814
..........
group_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 ...........
group_variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .822 ..........
gui_add_annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .824 ..........
gui_bin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .828
..........
gui_change_highlight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .833 ..........
gui_close_window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .835 ..........
gui_create_attrgroup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .837 ..........
gui_create_category_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 ...........
gui_create_menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .842 ..........
gui_create_pref_category . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 ...........
gui_create_pref_key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 ...........
gui_create_schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 ..........
gui_create_task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .852 ..........
gui_create_task_item . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 ...........
gui_create_tk_palette_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .856 ..........
gui_create_tk_task_page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 ...........
gui_create_toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .860 ..........
gui_create_toolbar_item . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 ...........
gui_create_window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864 ...........
gui_delete_attrgroup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 ...........
gui_delete_menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .869 ..........
gui_delete_toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .871 ..........
gui_delete_toolbar_item . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873 ...........
gui_eval_command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .875 ..........
gui_execute_menu_item . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .877 ..........
gui_exist_pref_category . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .879 ..........
gui_exist_pref_key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .880 ..........
gui_exist_window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 ...........
gui_get_annotations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 ...........
gui_get_bucket_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885 ...........
gui_get_bucket_option_list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887 ...........
gui_get_cell_block_marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .888 ..........
gui_get_current_task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .890 ..........
gui_get_current_task_item . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891 ...........
gui_get_current_task_page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .892 ..........
gui_get_current_window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .893 ..........
gui_get_highlight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .896 ..........
gui_get_highlight_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898 ...........
gui_get_map_list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .900 ..........
gui_get_map_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901 ...........
gui_get_map_option_list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .903 ..........
gui_get_menu_roots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 ...........
gui_get_mouse_tool_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905 ...........

Contents 10
Synthesis Tool Commands Version S-2021.06-SP2

gui_get_pref_keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .906 ..........

gui_get_pref_value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907 ...........
gui_get_region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .909 ..........
gui_get_setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910 ...........
gui_get_task_list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912 ...........
gui_get_task_page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 ...........
gui_get_toolbar_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .915 ..........
gui_get_window_ids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916 ...........
gui_get_window_pref_categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918 ...........
gui_get_window_pref_keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .920 ..........
gui_get_window_pref_value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922 ...........
gui_get_window_types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924 ...........
gui_hide_palette . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926 ...........
gui_hide_toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928 ...........
gui_inspect_violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .930 ..........
gui_list_attrgroups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .932 ..........
gui_list_category_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934 ...........
gui_list_cell_block_marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937 ...........
gui_load_cell_density_mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938 ...........
gui_load_hierarchy_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .939 ..........
gui_load_pin_density_mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .941 ..........
gui_load_voltage_area_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .942 ..........
gui_mouse_tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .943 ..........
gui_overlay_layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .945 ..........
gui_query_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .947 ..........
gui_remove_all_annotations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 ..........
gui_remove_all_rulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .952 ..........
gui_remove_annotations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .953 ..........
gui_remove_category_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955 ...........
gui_remove_cell_block_marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957 ...........
gui_remove_pref_key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959 ...........
gui_remove_ruler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .960 ..........
gui_report_hotkeys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962 ...........
gui_report_task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964 ...........
gui_schematic_add_logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966 ...........
gui_schematic_remove_logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968 ...........
gui_scroll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .970
..........
gui_select_vmbucket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .972 ..........
gui_set_active_window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .974 ..........
gui_set_bucket_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .976 ..........
gui_set_cell_block_marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .978 ..........
gui_set_current_task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .980 ..........
gui_set_highlight_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 ...........
gui_set_hotkey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 ...........
gui_set_layout_user_command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .986 ..........

Contents 11
Synthesis Tool Commands Version S-2021.06-SP2

gui_set_map_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988 ...........

gui_set_mouse_tool_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .990 ..........
gui_set_pref_value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992 ...........
gui_set_region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .994 ..........
gui_set_setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996 ...........
gui_set_task_list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998 ...........
gui_set_timing_table_paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .999 ..........
gui_set_window_pref_key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1001 ..........
gui_show_file_in_editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1003 ..........
gui_show_man_page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004 ...........
gui_show_map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006 ...........
gui_show_palette . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1008 ..........
gui_show_toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010 ...........
gui_show_url_in_browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012 ...........
gui_show_window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1013 ..........
gui_start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1015 ..........
gui_stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1017 ..........
gui_update_attrgroup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018 ...........
gui_update_pref_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020 ...........
gui_view_port_history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021 ...........
gui_violation_schematic_add_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1024 ..........
gui_wave_add_signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026 ...........
gui_write_layout_image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1028 ..........
gui_write_window_image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030 ...........
gui_zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1032 ..........
gui_zoom_all_layouts_to_current_view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1034 ..........
help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
...........
history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037...........
identify_clock_gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1040 ..........
identify_register_banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1043 ..........
if . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1047
..........
import_ndm_block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1049 ..........
index_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1051 ..........
infer_switching_activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053 ...........
insert_buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1056 ..........
insert_clock_gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061 ...........
insert_dft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064 ...........
insert_isolation_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1070 ..........
insert_mv_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073 ...........
is_false . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1075 ..........
is_true . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077...........
lib2saif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1079 ..........
license_users . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1081 ..........
link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1083
..........
list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
...........

Contents 12
Synthesis Tool Commands Version S-2021.06-SP2

list_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1089 ..........

list_commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1092 ..........
list_designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094 ...........
list_dont_touch_types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096 ...........
list_duplicate_designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1098 ..........
list_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100
...........
list_hdl_blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1102 ..........
list_instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1104 ..........
list_libs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1107
..........
list_licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1109 ..........
list_size_only_types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1111 ..........
list_test_models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1113 ..........
list_test_modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115 ..........
lminus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117...........
load_of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1119 ..........
load_upf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1121 ..........
ls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
...........
magnet_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126 ...........
man . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
..........
map_isolation_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1131 ..........
map_level_shifter_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1133 ..........
map_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135 ...........
map_retention_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137 ...........
mark_safety_core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139 ...........
mark_safety_error_code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1140 ..........
mark_safety_register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1141 ..........
mem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1142 ..........
merge_saif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1144 ..........
move_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 ...........
mw_cel_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1149 ..........
name_format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1151 ..........
open_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1153 ..........
open_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1155 ..........
optimize_netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157 ...........
optimize_registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1158 ..........
parallel_execute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163 ...........
parse_proc_arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1165 ..........
preview_dft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167 ...........
print_message_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1175 ..........
print_suppressed_messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1177 ..........
print_variable_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178 ...........
printenv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180...........
printvar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1182..........
proc_args . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1184 ..........
proc_body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186 ...........

Contents 13
Synthesis Tool Commands Version S-2021.06-SP2

propagate_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1188 ..........

propagate_switching_activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1193 ..........
propagate_user_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1195 ..........
push_down_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1197 ..........
pwd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
...........
query_cell_instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1200 ..........
query_cell_mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1202 ..........
query_map_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1204 ..........
query_net_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1206 ..........
query_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 ...........
query_port_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211 ...........
query_port_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213 ..........
query_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215 ...........
query_pst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1217 ..........
query_pst_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1219 ..........
query_qor_snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221 ...........
quit! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234
...........
quit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1235
..........
read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1236
..........
read_bsdl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1237 ..........
read_cell_expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239 ...........
read_db . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1241 ..........
read_ddc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242 ...........
read_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1244..........
read_floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251 ...........
read_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253
...........
read_ocvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1255 ..........
read_parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257 ...........
read_pin_map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260 ...........
read_saif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262...........
read_scan_def . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1266 ..........
read_sdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268 ...........
read_sdf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1273 ..........
read_sverilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1276 ..........
read_tech_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277 ...........
read_test_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279 ...........
read_test_protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1281 ..........
read_verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1284 ..........
read_vhdl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1286 ..........
rebuild_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1287 ..........
redirect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1289
..........
remove_annotated_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1294 ..........
remove_annotated_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1297 ...........
remove_annotated_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299 ...........
remove_annotations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301 ...........

Contents 14
Synthesis Tool Commands Version S-2021.06-SP2

remove_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303
..........
remove_auto_path_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305 ..........
remove_boundary_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307 ...........
remove_boundary_cell_io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1309 ..........
remove_bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1311 ..........
remove_bsd_compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1313 ..........
remove_bsd_instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1315 ..........
remove_bsd_linkage_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1316 ..........
remove_bsd_power_up_reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1318 ..........
remove_buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1319
..........
remove_buffer_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1322 ..........
remove_bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1324
..........
remove_case_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326 ...........
remove_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1328
..........
remove_cell_degradation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330 ...........
remove_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332
...........
remove_clock_gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1334 ..........
remove_clock_gating_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1337 ..........
remove_clock_gating_style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1339 ..........
remove_clock_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1341 ..........
remove_clock_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1343 ..........
remove_clock_sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1345 ..........
remove_clock_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347 ...........
remove_clock_uncertainty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1349 ..........
remove_congestion_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1352 ..........
remove_constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1354 ..........
remove_core_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1356 ..........
remove_data_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357 ...........
remove_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359
...........
remove_dft_clock_gating_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362 ...........
remove_dft_connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363 ...........
remove_dft_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365 ...........
remove_dft_equivalent_signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1367 ..........
remove_dft_location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368 ...........
remove_dft_partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370...........
remove_dft_power_control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1372 ...........
remove_dft_signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1373 ..........
remove_die_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1375 ..........
remove_disable_clock_gating_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376 ...........
remove_disable_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1378 ..........
remove_dp_int_round . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1380 ..........
remove_driving_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1382 ..........
remove_from_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1384 ..........
remove_from_rp_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1386 ..........
remove_generated_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388 ...........

Contents 15
Synthesis Tool Commands Version S-2021.06-SP2

remove_host_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1390 ...........

remove_ideal_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1391 ..........
remove_ideal_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1393
...........
remove_ideal_network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395 ...........
remove_ideal_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1397 ..........
remove_ignored_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1399 ..........
remove_input_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401 ...........
remove_isolate_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404 ...........
remove_isolation_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406...........
remove_keepout_margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1408 ..........
remove_level_shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410..........
remove_libcell_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1411 ..........
remove_license . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1413
..........
remove_link_library_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1415 ..........
remove_min_pulse_width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417 ...........
remove_multibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1419
..........
remove_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1422
..........
remove_net_routing_layer_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1424 ..........
remove_net_search_pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425 ..........
remove_net_shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1427 ...........
remove_ocvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1428
...........
remove_output_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1430 ...........
remove_path_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433 ...........
remove_pin_guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1435 ..........
remove_pin_map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1436 ..........
remove_pin_name_synonym . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1437 ...........
remove_placement_blockage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1440 ..........
remove_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1442
...........
remove_power_domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1444 ..........
remove_preferred_routing_direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1446 ..........
remove_propagated_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448 ...........
remove_route_guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1450 ...........
remove_routing_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1452 ...........
remove_rp_group_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1454 ..........
remove_rp_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1456 ..........
remove_rtl_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1458
..........
remove_safety_core_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1460 ..........
remove_safety_core_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461 ...........
remove_safety_error_code_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1462 ..........
remove_safety_error_code_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1464 ...........
remove_safety_register_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1466 ...........
remove_safety_register_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1468 ..........
remove_scaling_lib_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1469 ..........
remove_scan_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1471 ...........
remove_scan_link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1473..........

Contents 16
Synthesis Tool Commands Version S-2021.06-SP2

remove_scan_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475 ...........

remove_scan_register_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477 ...........
remove_scan_replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1479 ..........
remove_scan_skew_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481 ..........
remove_scan_suppress_toggling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483 ...........
remove_scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1484 ..........
remove_sdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1486 ..........
remove_sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1488 ..........
remove_target_library_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1490 ..........
remove_terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492 ...........
remove_test_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494 ...........
remove_test_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1495 ..........
remove_test_point_element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496 ...........
remove_test_protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1498 ...........
remove_track . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1500 ..........
remove_unconnected_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502 ...........
remove_upf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1504..........
remove_user_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1505 ..........
remove_user_shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507 ...........
remove_verification_priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1509 ..........
remove_via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511
...........
remove_via_ladder_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1513 ..........
remove_via_ladder_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1515 ...........
remove_via_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516 ...........
remove_voltage_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518 ...........
remove_wire_load_min_block_size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1520 ..........
remove_wire_load_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1522 ..........
remove_wire_load_selection_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524 ...........
rename . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1526
..........
rename_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1528 ...........
rename_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1531 ..........
replace_clock_gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533 ...........
replace_synthetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1535 ..........
report_activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537
...........
report_ahfs_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1540 ..........
report_annotated_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542 ...........
report_annotated_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1544 ..........
report_annotated_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1546 ..........
report_app_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1548 ..........
report_app_var . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1549 ...........
report_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551
...........
report_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555
...........
report_auto_floorplan_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1559 ..........
report_auto_ungroup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1562 ..........
report_autofix_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564 ...........

Contents 17
Synthesis Tool Commands Version S-2021.06-SP2

report_autofix_element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566 ...........

report_background_jobs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568 ...........
report_block_abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1570 ..........
report_boundary_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1573 ..........
report_boundary_cell_io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575 ...........
report_bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1577 ..........
report_bsd_buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1579 ..........
report_bsd_compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1581 ..........
report_bsd_instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1583 ..........
report_bsd_linkage_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1586 ...........
report_bsd_power_up_reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588 ..........
report_buffer_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1590 ...........
report_buffer_tree_qor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1592 ..........
report_bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1594
..........
report_case_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1596 ..........
report_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1598
...........
report_cell_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1602 ..........
report_check_library_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604 ...........
report_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1606
..........
report_clock_gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1610 ..........
report_clock_gating_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621 ...........
report_clock_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1624 ..........
report_clock_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1634 ..........
report_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643...........
report_compile_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1647 ..........
report_compile_spg_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650 ...........
report_congestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651 ...........
report_congestion_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653 ...........
report_constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655..........
report_cross_probing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1662 ..........
report_cross_probing_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665 ...........
report_crpr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1667
..........
report_datapath_gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1671 ..........
report_delay_calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1675 ..........
report_delay_estimation_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1680 ..........
report_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1682...........
report_design_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1685 ..........
report_design_mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1687 ..........
report_device_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689 ...........
report_dft_clock_controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692 ...........
report_dft_clock_gating_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1694 ..........
report_dft_clock_gating_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696 ...........
report_dft_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1698 ..........
report_dft_connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1700 ..........
report_dft_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1701 ..........

Contents 18
Synthesis Tool Commands Version S-2021.06-SP2

report_dft_drc_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703 ...........

report_dft_equivalent_signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1705 ..........
report_dft_hierarchical_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706 ...........
report_dft_insertion_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1708 ..........
report_dft_location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1710 ..........
report_dft_partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1712 ..........
report_dft_power_control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714 ...........
report_dft_signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715 ...........
report_direct_power_rail_tie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718 ...........
report_disable_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719 ...........
report_dont_touch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1721 ..........
report_dp_smartgen_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1723 ..........
report_extraction_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724 ...........
report_failsafe_fsm_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1726 ..........
report_failsafe_fsm_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1727 ...........
report_fsm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1728..........
report_gui_stroke_bindings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1730 ..........
report_gui_stroke_builtins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1732 ..........
report_heterogeneous_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1734 ..........
report_hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1736 ...........
report_host_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1738 ..........
report_icc2_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1739 ..........
report_icc_dp_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1741 ..........
report_ideal_network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1743 ..........
report_ieee_1500_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1747 ...........
report_ignored_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1749 ..........
report_inbound_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1750 ..........
report_interclock_relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1752 ...........
report_internal_loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1755 ..........
report_isolate_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1757 ..........
report_isolation_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1759 ..........
report_keepout_margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1762 ..........
report_latch_loop_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1764 ...........
report_level_shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1766 ...........
report_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1769
...........
report_libcell_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1784 ...........
report_link_library_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1786 ..........
report_logic_levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1788 ..........
report_logic_lock_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1792 ..........
report_logicbist_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1794 ..........
report_min_pulse_width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1796 ..........
report_mis_violation_summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1798 ...........
report_missing_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1800 ..........
report_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1802 ...........
report_multibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804
...........

Contents 19
Synthesis Tool Commands Version S-2021.06-SP2

report_multibit_banking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1808 ..........

report_mv_library_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1811 ..........
report_mv_qor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1814 ..........
report_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1818
...........
report_name_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1820 ..........
report_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1823...........
report_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826
...........
report_net_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1830 ...........
report_net_routing_layer_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1833 ...........
report_net_routing_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1835 ..........
report_net_search_pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1838 ...........
report_net_search_pattern_delay_estimation_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1840 ...........
report_net_search_pattern_priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1842 ..........
report_obfuscation_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1844 ...........
report_ocvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1846
..........
report_opcond_inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850 ...........
report_operating_conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1852 ...........
report_optimize_dft_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854 ...........
report_partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1855
..........
report_path_budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1857 ..........
report_path_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1861 ..........
report_physical_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1863 ..........
report_pin_map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1865 ..........
report_pin_name_synonym . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1867 ..........
report_pipeline_scan_data_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1869 ..........
report_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1871
..........
report_power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1876
..........
report_power_calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883 ...........
report_power_derate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1888 ..........
report_power_domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1890 ..........
report_power_gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894 ...........
report_power_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896 ...........
report_power_pin_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1898 ..........
report_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1901 ..........
report_preferred_routing_direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1903 ...........
report_preserve_user_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1905 ..........
report_pst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1906
...........
report_qor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1910
...........
report_qtm_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1914 ..........
report_reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1917...........
report_resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1920 ..........
report_retention_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1925 ...........
report_retention_clamp_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1928 ...........
report_route_zrt_common_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1931 ..........
report_route_zrt_global_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1932 ...........

Contents 20
Synthesis Tool Commands Version S-2021.06-SP2

report_routing_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1933 ...........

report_rp_group_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1935 ..........
report_safety_core_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1937 ..........
report_safety_core_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1938 ..........
report_safety_error_code_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1939 ..........
report_safety_error_code_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1940 ...........
report_safety_logic_port_map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1941 ..........
report_safety_register_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1942 ..........
report_safety_register_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1943 ...........
report_safety_status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944 ...........
report_saif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1946
..........
report_scaling_lib_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1950 ..........
report_scan_chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1952 ..........
report_scan_compression_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1954 ..........
report_scan_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1956 ..........
report_scan_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1960 ..........
report_scan_link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1962 ...........
report_scan_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1964 ..........
report_scan_register_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1967 ..........
report_scan_replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1969 ...........
report_scan_skew_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1971 ...........
report_scan_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1973 ...........
report_scan_suppress_toggling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1975 ...........
report_scenario_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1976 ...........
report_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1978 ...........
report_script_runtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1981 ..........
report_security_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983 ...........
report_security_lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1985 ...........
report_self_gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1987 ...........
report_separate_process_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1991 ..........
report_serialize_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1992 ..........
report_size_only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1994 ...........
report_streaming_compression_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1996 ...........
report_supply_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1998 ...........
report_supply_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2000 ..........
report_synlib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2002
...........
report_synlib_history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2008 ..........
report_target_library_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2010 ..........
report_test_assume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2012 ..........
report_test_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2014 ..........
report_test_point_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2016 ..........
report_test_point_element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2018 ..........
report_testability_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2020 ...........
report_threshold_voltage_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2021 ...........
report_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2024
..........

Contents 21
Synthesis Tool Commands Version S-2021.06-SP2

report_timing_derate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2035 ..........

report_timing_requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2039 ..........
report_tlu_plus_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2043 ...........
report_top_implementation_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2045 ...........
report_track . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2047
..........
report_transitive_fanin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2049 ..........
report_transitive_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2051 ..........
report_units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2054
..........
report_upf_cell_mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2056 ..........
report_use_test_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2058 ...........
report_via_ladder_candidates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2059 ..........
report_via_ladder_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2060 ..........
report_via_ladder_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2062 ..........
report_via_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2063..........
report_voltage_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2065 ...........
report_watermark_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2067 ...........
report_wire_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2069...........
report_wrapper_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2072 ..........
report_write_lib_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2074 ..........
reset_app_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2075 ..........
reset_autofix_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2076 ..........
reset_autofix_element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2078 ..........
reset_bsd_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2080 ...........
reset_cell_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2081 ...........
reset_clock_gate_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2083 ...........
reset_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2085
...........
reset_dft_clock_controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2087 ...........
reset_dft_clock_gating_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2089 ...........
reset_dft_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2090 ...........
reset_dft_drc_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2091 ...........
reset_dft_insertion_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2093 ...........
reset_ieee_1500_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2094 ..........
reset_logic_lock_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2095 ...........
reset_logicbist_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2097 ..........
reset_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2098
..........
reset_obfuscation_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2100 ...........
reset_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2102
..........
reset_physical_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2105 ...........
reset_pipeline_scan_data_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2106 ..........
reset_power_derate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2107 ..........
reset_scan_compression_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2109 ...........
reset_scan_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2110 ...........
reset_security_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2111 ..........
reset_security_lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2113 ...........
reset_serialize_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2115 ..........

Contents 22
Synthesis Tool Commands Version S-2021.06-SP2

reset_streaming_compression_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2116 ...........

reset_switching_activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2117 ..........
reset_test_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2119 ...........
reset_test_point_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2120 ..........
reset_testability_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2121 ..........
reset_timing_derate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2122 ..........
reset_watermark_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2124 ..........
reset_wrapper_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2126 ..........
resize_polygon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2128 ...........
rewire_clock_gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2132 ..........
rp_group_inclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2135 ...........
rp_group_instantiations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2137 ..........
rp_group_references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2139 ..........
run_test_point_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2141 ..........
saif_map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2143
...........
save_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2149
..........
save_qtm_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2151 ..........
save_ssf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2153
...........
save_upf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2154
...........
scale_floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2156...........
select_block_scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2158 ..........
set_active_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2161 ..........
set_ahfs_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2163 ..........
set_always_on_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2166 ..........
set_always_on_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2167 ...........
set_analyze_rtl_logic_level_threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2169 ..........
set_annotated_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2171 ...........
set_annotated_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2174 ..........
set_annotated_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2177 ..........
set_app_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2179 ...........
set_app_var . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2181..........
set_aspect_ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2183 ...........
set_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2185
..........
set_auto_disable_drc_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2187 ..........
set_auto_floorplan_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2190 ...........
set_auto_ideal_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2193 ...........
set_autofix_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2194 ...........
set_autofix_element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2197 ...........
set_balance_registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2200 ..........
set_boundary_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2202 ..........
set_boundary_cell_io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2208 ..........
set_boundary_optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2210 ..........
set_bsd_ac_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2212 ...........
set_bsd_compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2214 ...........
set_bsd_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2216 ..........

Contents 23
Synthesis Tool Commands Version S-2021.06-SP2

set_bsd_instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2219
...........
set_bsd_linkage_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2224 ...........
set_bsd_power_up_reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2226 ...........
set_case_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2228..........
set_cell_degradation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2230 ..........
set_cell_internal_power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2232 ..........
set_cell_location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2234
...........
set_cell_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2236
..........
set_check_library_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2238 ..........
set_cle_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2250
..........
set_clock_gate_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2252 ..........
set_clock_gating_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2256 ..........
set_clock_gating_enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2259 ..........
set_clock_gating_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2261 ...........
set_clock_gating_registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2263 ...........
set_clock_gating_style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2265 ...........
set_clock_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2274
..........
set_clock_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2277
...........
set_clock_sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2280
...........
set_clock_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2282
..........
set_clock_uncertainty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2284...........
set_combinational_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2288 ..........
set_compile_directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2290 ...........
set_compile_partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2292 ..........
set_compile_power_high_effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2295 ..........
set_compile_spg_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2297 ..........
set_congestion_optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2299 ..........
set_congestion_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2301 ..........
set_connection_class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2303 ...........
set_constant_register_removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2305 ..........
set_context_margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2306 ..........
set_cost_priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2308
...........
set_critical_range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2310
...........
set_current_command_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2312 ...........
set_current_spfm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2314
..........
set_data_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2315
..........
set_datapath_gating_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2318 ...........
set_datapath_optimization_effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2322 ...........
set_default_drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2324
..........
set_default_driving_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2326 ..........
set_default_fanout_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2329 ...........
set_default_input_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2331 ..........
set_default_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2333
...........
set_default_output_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2335 ...........
set_delay_estimation_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2337 ..........

Contents 24
Synthesis Tool Commands Version S-2021.06-SP2

set_design_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2340 ...........

set_design_license . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2346 ...........
set_design_top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2348 ...........
set_device_constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2349 ...........
set_device_group_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2351 ..........
set_dft_clock_controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2353 ..........
set_dft_clock_gating_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2356 ..........
set_dft_clock_gating_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2359 ..........
set_dft_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2361 ..........
set_dft_connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2365 ..........
set_dft_drc_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2369 ...........
set_dft_drc_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2371 ..........
set_dft_equivalent_signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2373 ...........
set_dft_insertion_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2375 ...........
set_dft_location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2378 ..........
set_dft_power_control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2381 ..........
set_dft_signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2383
...........
set_direct_power_rail_tie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2394 ..........
set_disable_clock_gating_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2396 ..........
set_disable_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2398 ..........
set_domain_supply_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2400 ..........
set_dont_retime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2402 ..........
set_dont_touch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2404 ...........
set_dont_touch_network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2407 ..........
set_dont_use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2410 ..........
set_dp_int_round . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2412 ..........
set_dp_smartgen_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2415 ..........
set_drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2421
...........
set_driving_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2423
...........
set_dynamic_optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2427 ..........
set_equal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2429
..........
set_equivalent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2431 ..........
set_extraction_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2433 ..........
set_failsafe_fsm_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2435 ..........
set_false_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2437 ..........
set_fanout_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2441 ..........
set_fix_hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2443
..........
set_fix_multiple_port_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2445 ..........
set_flatten . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2447
...........
set_fp_base_gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2449 ...........
set_fsm_encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2451 ..........
set_fsm_encoding_style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2453 ...........
set_fsm_minimize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2455 ...........
set_fsm_order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2456...........
set_fsm_preserve_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2458 ...........

Contents 25
Synthesis Tool Commands Version S-2021.06-SP2

set_fsm_state_vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2459 ...........

set_gui_stroke_binding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2460 ..........
set_gui_stroke_preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2464 ...........
set_host_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2466 ..........
set_hpc_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2468 ...........
set_icc2_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2470 ...........
set_icc_dp_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2474 ...........
set_ideal_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2476 ..........
set_ideal_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2478..........
set_ideal_network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2480 ..........
set_ideal_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2483 ...........
set_ieee_1500_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2485 ...........
set_ignored_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2487 ...........
set_impl_priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2489...........
set_implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2491 ..........
set_input_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2493 ..........
set_input_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2497 ..........
set_isolate_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2499 ..........
set_isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2501
..........
set_isolation_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2508 ..........
set_isolation_control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2510 ...........
set_keepout_margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2512 ...........
set_latch_loop_breakers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2515 ..........
set_leakage_optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2517 ...........
set_leakage_power_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2519 ..........
set_level_shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2521..........
set_level_shifter_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2527 ..........
set_lib_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2529..........
set_libcell_dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2531 ..........
set_libcell_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2533 ...........
set_libpin_location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2535 ..........
set_link_library_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2537 ...........
set_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2540
..........
set_local_link_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2543 ..........
set_logic_dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2545
..........
set_logic_lock_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2547 ..........
set_logic_one . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2549...........
set_logic_zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2551 ..........
set_logicbist_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2553 ...........
set_map_only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2556 ...........
set_max_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2558 ...........
set_max_capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2560 ...........
set_max_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2562 ...........
set_max_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2567 ..........
set_max_time_borrow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2569 ..........

Contents 26
Synthesis Tool Commands Version S-2021.06-SP2

set_max_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2571 ..........

set_message_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2573 ..........
set_message_severity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2575 ..........
set_min_capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2576 ..........
set_min_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2578..........
set_min_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2582
...........
set_min_pulse_width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2584 ..........
set_minimize_tree_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2586 ..........
set_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2588
..........
set_model_drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2590...........
set_model_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2592 ..........
set_model_map_effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2594 ..........
set_multi_vth_constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2595 ...........
set_multibit_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2598 ..........
set_multicycle_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2602 ..........
set_mw_lib_reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2607 ..........
set_mw_technology_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2609 ...........
set_net_routing_layer_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2611 ..........
set_net_routing_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2613 ...........
set_net_search_pattern_delay_estimation_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2616 ...........
set_net_search_pattern_priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2618 ...........
set_obfuscation_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2620 ..........
set_opcond_inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2622 ..........
set_operating_conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2624 ...........
set_opposite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2628
...........
set_optimize_dft_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2630 ..........
set_optimize_registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2632 ..........
set_output_clock_port_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2636 ..........
set_output_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2638 ..........
set_partial_on_translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2642 ..........
set_path_margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2644...........
set_pg_pin_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2648 ..........
set_physical_hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2650 ...........
set_pin_access_optimization_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2651 ..........
set_pin_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2653..........
set_pin_name_synonym . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2655 ..........
set_pin_physical_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2657 ..........
set_pipeline_scan_data_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2660 ...........
set_placement_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2662 ...........
set_port_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2664..........
set_port_fanout_number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2670 ..........
set_port_location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2672..........
set_port_side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2674
..........
set_power_clock_scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2676 ..........
set_power_derate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2678 ...........

Contents 27
Synthesis Tool Commands Version S-2021.06-SP2

set_power_guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2681 ..........

set_power_prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2683 ...........
set_power_switch_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2685 ..........
set_prefer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2687
...........
set_preferred_routing_direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2689 ..........
set_preferred_scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2691 ..........
set_preserve_clock_gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2693 ..........
set_propagated_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2696 ..........
set_qor_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2698...........
set_qtm_global_parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2700 ...........
set_qtm_port_drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2702 ...........
set_qtm_port_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2704 ..........
set_qtm_technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2706 ...........
set_query_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2709 ..........
set_ref_libs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2715
...........
set_register_merging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2717 ..........
set_register_replication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2719 ..........
set_register_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2722 ..........
set_related_supply_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2725 ..........
set_repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2727
...........
set_replace_clock_gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2730 ..........
set_resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2732..........
set_resource_allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2734 ..........
set_retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2736
...........
set_retention_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2741...........
set_retention_control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2743 ..........
set_retention_control_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2746 ...........
set_retention_elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2748 ..........
set_route_zrt_common_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2750 ...........
set_route_zrt_global_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2766 ...........
set_rp_group_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2770 ...........
set_rtl_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2776
...........
set_safety_core_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2781 ..........
set_safety_error_code_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2783 ..........
set_safety_logic_port_map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2785 ..........
set_safety_register_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2787 ...........
set_scaling_lib_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2789 ...........
set_scan_compression_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2791 ..........
set_scan_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2797 ..........
set_scan_element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2803 ..........
set_scan_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2806 ..........
set_scan_link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2810
..........
set_scan_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2812 ..........
set_scan_register_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2820 ..........
set_scan_replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2822 ...........

Contents 28
Synthesis Tool Commands Version S-2021.06-SP2

set_scan_skew_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2824 ..........

set_scan_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2826 ...........
set_scan_suppress_toggling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2827 ..........
set_scenario_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2830 ..........
set_scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2833
...........
set_script_runtime_report_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2835 ..........
set_security_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2837 ..........
set_security_lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2839 ..........
set_self_gating_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2841 ..........
set_self_gating_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2844 ..........
set_sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2846
...........
set_separate_process_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2848 ...........
set_serialize_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2849 ...........
set_size_only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2852 ..........
set_spfm_loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2854 ...........
set_spfm_target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2855 ..........
set_streaming_compression_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2856 ..........
set_structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2860
...........
set_svf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2862
..........
set_switching_activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2864 ...........
set_switching_activity_profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2868 ...........
set_synlib_dont_get_license . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2872 ..........
set_tap_elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2874 ...........
set_target_library_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2875 ...........
set_technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2878 ...........
set_test_assume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2880 ..........
set_test_point_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2882 ..........
set_test_point_element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2885 ..........
set_testability_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2888 ...........
set_timing_derate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2894 ...........
set_timing_ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2897 ..........
set_tlu_plus_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2900 ..........
set_top_implementation_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2903 ..........
set_transform_for_retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2906 ..........
set_unconnected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2908 ..........
set_ungroup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2910 ..........
set_uninitialized_register_value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2912 ...........
set_units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2914
...........
set_unloaded_register_removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2916 ...........
set_upf_cell_mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2917 ...........
set_upf_query_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2919 ...........
set_user_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2921 ...........
set_user_budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2923 ...........
set_utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2925
..........
set_variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2927
...........

Contents 29
Synthesis Tool Commands Version S-2021.06-SP2

set_verification_priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2929 ...........

set_verification_top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2931 ...........
set_via_ladder_candidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2933 ...........
set_via_ladder_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2935 ...........
set_via_ladder_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2937 ..........
set_voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2939 ...........
set_voltage_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2942 ..........
set_vsdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2944 ...........
set_watermark_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2946 ...........
set_wire_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2948 ...........
set_wire_load_min_block_size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2953 ...........
set_wire_load_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2955 ..........
set_wire_load_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2957 ..........
set_wire_load_selection_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2961 ..........
set_wrapper_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2963 ...........
set_zero_interconnect_delay_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2972 ..........
setenv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2973
...........
sh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2975
..........
sh_list_key_bindings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2977 ..........
shell_is_dcnxt_shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2979 ..........
shell_is_in_exploration_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2980 ..........
shell_is_in_ndm_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2981 ...........
shell_is_in_topographical_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2982 ..........
shell_is_in_xg_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2983 ..........
sim_assertion_control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2984 ..........
sim_corruption_control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2986 ...........
sim_replay_control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2988 ..........
simplify_constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2990 ..........
size_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2992..........
sizeof_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2994 ...........
sort_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2996 ...........
source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2998
...........
split_register_bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3000 ..........
ssf_version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3002 ...........
start_icc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3004 ..........
start_icc2_dp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3006 ..........
start_icc_dp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3008 ..........
streaming_dft_planner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3010 ..........
sub_designs_of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3014 ..........
sub_instances_of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3016 ..........
suppress_icc2_message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3018 ..........
suppress_message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3019 ..........
translate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3021..........
unalias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3023..........
ungroup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3024 ..........

Contents 30
Synthesis Tool Commands Version S-2021.06-SP2

uniquify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3028
...........
unset_power_guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3031 ..........
unsetenv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3033...........
unsuppress_message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3035 ..........
update_bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3037 ...........
update_cross_probing_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3039 ..........
update_floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3042 ...........
update_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3043...........
update_lib_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3045 ...........
update_lib_pg_pin_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3047 ..........
update_lib_pin_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3049 ..........
update_lib_voltage_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3051 ..........
update_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3053 ...........
upf_version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3055 ...........
use_interface_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3057 ..........
use_test_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3059 ..........
which . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3061
..........
while . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3063
...........
win_select_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3065 ..........
win_set_filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3067 ..........
win_set_select_class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3069 ..........
write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3070
..........
write_app_var . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3071 ...........
write_bsd_rtl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3073 ...........
write_bsdl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3075...........
write_cell_expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3077 ..........
write_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3078 ...........
write_def . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3081
...........
write_design_lib_paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3085 ...........
write_environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3087 ..........
write_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3089
...........
write_floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3093 ..........
write_icc2_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3097 ...........
write_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3100
..........
write_lib_specification_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3102 ...........
write_link_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3104 ...........
write_milkyway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3106 ...........
write_multibit_components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3108 ...........
write_multibit_guidance_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3109 ..........
write_mw_lib_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3111 ..........
write_parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3113 ...........
write_physical_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3116 ..........
write_qtm_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3118 ..........
write_rp_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3120 ..........
write_rtl_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3123 ..........

Contents 31
Synthesis Tool Commands Version S-2021.06-SP2

write_safety_register_data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3125 ...........

write_saif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3126
..........
write_scan_def . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3129 ...........
write_script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3131
...........
write_sdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3135
..........
write_sdf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3139
...........
write_tech_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3141
...........
write_test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3143
..........
write_test_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3146 ..........
write_test_protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3148 ..........
write_timing_context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3151 ...........

Contents 32
Synthesis Tool Commands Version S-2021.06-SP2

acs_get_parent_partition
Creates a collection of designs that are compiled partitions containing the specified subdesign.

SYNTAX
string acs_get_parent_partition
design_name
[-hierarchy]
[-list]

Data Types
design_name string

ARGUMENTS
design_name

Specifies the name of a subdesign.

-hierarchy

Causes the command to collect all parent partitions of the specified design. By default only the immediate parent partition is
returned.

-list

Causes the command to return a list of names. Without this option a collection of design objects is returned.

DESCRIPTION
The acs_get_parent_partition command returns the lowest-level compile partition that contains the specified subdesign. If the
specified subdesign is a compile partition, the command returns the subdesign. If the -hierarchy option is specified, all partitions that
contain the subdesign are included in the collection. If the subdesign is in the subtree of a multiply instantiated design, all parent
partitions of all instances of this multiply instantiated design are included in the result. The command creates a collection containing
the design objects, unless the -list option is specified. In this case, the command returns a Tcl list with the names of the designs.

SEE ALSO
set_compile_partitions(2)

acs_get_parent_partition 33
Synthesis Tool Commands Version S-2021.06-SP2

acs_read_hdl
Reads in the HDL source code of a design and generates the GTECH representation.

SYNTAX
status acs_read_hdl
[design_name]
[-hdl_source file_or_dir_list]
[-exclude_list file_or_dir_list]
[-format {verilog | vhdl}]
[-recurse]
[-no_dependency_check]
[-no_elaborate]
[-library design_lib_name]
[-verbose]
[-auto_update | -update file_list]
[-destination destination_dir]
[-sv_package_files file_list]

Data Types
design_name string
file_or_dir_list list
design_lib_name string
file_list list
destination_dir string

ARGUMENTS
design_name

Specifies the name of the top-level design. Elaboration starts at the specified module and elaborates the entire design subtree
under that module. This argument is required unless the -no_elaborate option is specified.

-hdl_source file_or_dir_list

Specifies a list of files or directories containing the source code of the design. The acs_read_hdl command analyzes the contents
of all files in the list (and in the subdirectories if the -recurse option is set) according to the acs_verilog_extensions,
acs_vhdl_extensions, acs_exclude_list, and acs_exclude_extensions variables.

If this option is not specified, the command uses the acs_hdl_source Tcl variable by default. If the acs_hdl_source variable is not
defined, the search_path variable is used. The command-line argument overrides the variables. The names in the -hdl_source
lists can contain wildcards. The command performs a Tcl glob-style expansion on each list item.

-exclude_list file_or_dir_list

Specifies a list of files and directories that are not to be analyzed. If the command expands an item from the -hdl_source list, it
checks the file or directory against all entries of this list and ignores the file or directory if it is covered by at least one of the entries.

If this option is omitted, the command uses the acs_exclude_list Tcl variable. The command-line argument overrides the variable.

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Synthesis Tool Commands Version S-2021.06-SP2

It is possible to apply Tcl's UNIX-like filename globbing features by using the *, ?, and [] in file and directory names in this list. Add a
file name (wildcards are allowed) without a path to exclude all files with that name regardless of their location.

-format {verilog | vhdl}

Specifies that acs_read_hdl is to only look for files of the specified language with extensions from the corresponding extensions list
for the acs_verilog_extensions or acs_vhdl_extensions variables. The default is that the command reads in all files it finds with
Verilog extensions and VHDL extensions.

Use this option when you want to specify file names in the -hdl_source list that do not have one of the language-specific
extensions.

-recurse

Specifies that the command is to look into subdirectories of directories specified in the -hdl_source list, and recursively collect
source files from that location.

The default is that the command looks into the specified directories, but does not look in their subdirectories.

-no_dependency_check

Causes the command not to detect Verilog include files, not to determine VHDL libraries, and not to reorder the source file list.
Instead, the command processes the HDL source file list from left to right and analyzes VHDL files into the current working library
or the library specified with the -library option.

-no_elaborate

Prevents acs_read_hdl from performing the elaboration. The command stops after all source files are analyzed. Specify this option
when you want to manually elaborate the design after the command finishes.

-library design_lib_name

Specifies the library that is used as the working library for all VHDL files.

-verbose

Prints out more messages.

-auto_update

Automatically determines the HDL files to update, puts them in order according to the dependency (unless the -
no_dependency_check option is specified) and analyzes and elaborates the files. The designs defined in the specified HDL file(s)
replace the corresponding designs in the unmapped design in the destination directory. The option also creates the tables of
timestamps used by the subsequent acs_read_hdl -auto_update, acs_read_hdl -update, and acs_merge_design -auto_update
commands.

This option is mutually exclusive with the -update option.

-update file_list

Analyzes and elaborates the specified HDL source files in the given order. The designs defined in the specified HDL file(s) replace
the corresponding designs in the unmapped design in the destination directory. The option also creates the tables of timestamps
used by the subsequent acs_read_hdl -auto_update, acs_read_hdl -update, and acs_merge_design -auto_update commands.

This option is mutually exclusive with the -auto_update option.

-destination destination_dir

Specifies the directory to which the unmapped design is written when either the -update or the -auto_update option is specified.
The default is that the command writes the unmapped design and the timestamp tables to the elab/db directory.

DESCRIPTION

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Synthesis Tool Commands Version S-2021.06-SP2

The acs_read_hdl command reads in the HDL source files of a design, analyzes them, and elaborates the design starting at the
specified top-level module. It retains the resulting GTECH representation in memory.

To locate the source files, the command expands each item from the -hdl_source list. The list is either specified as an option with -
hdl_source at the command line, or set as the value of the acs_hdl_source Tcl variable. If neither of these methods are used, then
the search_path variable is used. The acs_read_hdl command performs a Tcl glob-style expansion on an item and checks if the
result is excluded by the acs_exclude_list or the acs_exclude_extensions variable. If it is not excluded and a file ends with one of
the extensions from the acs_vhdl_extensions variable extensions list, it is considered a VHDL source file. If the file ends with one of
the acs_verilog_extensions, it is considered a Verilog source file.

If an expansion is a directory, the command collects the files from the directory, and recursively from its subdirectories if the -
recursive option is set. The command then performs all extension checks on these files. If the -format option is set, only files with
Verilog or VHDL extensions are collected (based on the value of the option).

After acs_read_hdl collects all of the source files, it performs the following dependency checks (unless the -no_dependency_check
option is specified).

Detects Verilog include files to verify that they are not analyzed as source code files.

If a Verilog include file that appears only in the list of HDL source files is detected, but its directory does not appear in the global
search_path variable, and it is included in the Verilog source code without giving the path, then acs_read_hdl appends the
include file's directory to the search_path. This enables the analyze or read_verilog commands to locate the file. You are
notified about the changes made.

Detects Verilog macro usage and definition and reorders files accordingly to ensure that they are analyzed in the correct order.
This might not always be possible, such as when a macro is defined several times in different files or when macros are defined
in files included by other include files.

Determines the target library for each VHDL file. However, if the -library option is specified, this step is skipped and all VHDL
files are analyzed into the specified design library.

Orders the VHDL source files to ensure that they are analyzed in the correct order.

After analyzing all source files, the design is elaborated from the top-level module, unless the -no_elaborate option is specified. The
resulting GTECH representation is retained in memory.

If either the -update or the -auto_update option is specified, then the GTECH representation (unmapped design) is written to the
specified destination directory. The default destination directory is elab/db.

When the acs_read_hdl -auto_update or acs_read_hdl -update command is called the first time, all of the source HDL files are
analyzed and elaborated to create the unmapped design and the timestamp tables. Subsequent acs_read_hdl -auto_update
commands only analyze and elaborate the updated HDL source files and subsequent acs_read_hdl -update commands only analyze
and elaborate the specified HDL source files. The updated designs are replaced in the unmapped design. The first issuance of the
acs_read_hdl command is determined by the presence of the unmapped design file and timestamp tables in the destination directory.

EXAMPLES
The following example assumes that the current directory is the source directory. It specifies the source file list at the command line
and calls the command with the name of the top-level entity.

prompt> acs_read_hdl -hdl_source {.} -recurse E1

The next example specifies extensions for Verilog files that are different than the default ({.v}), sets the -hdl_source list and the
exclude_list list, and calls the command with the name of the top-level module name, forcing it to only collect files with Verilog
extensions.

prompt> set acs_verilog_extensions { .ve .VE }

prompt> set acs_hdl_source {mod1/src mod2/*/src}
prompt> set acs_exclude_list {mod1/src/incl mod2/*/src/incl}
prompt> acs_read_hdl -f verilog -no_dep TOP

Note that excluding include directories explicitly is only necessary if include files have the same extensions as source files and not all

acs_read_hdl 36
Synthesis Tool Commands Version S-2021.06-SP2

include files are included in the source.

prompt> acs_read_hdl -hdl_source src/mixed -auto_update

The first time the above command is issued, all of the mixed (Verilog and VHDL) HDL files from the specified directory are analyzed
and elaborated, and the resulting unmapped design is written to the default destination directory along with the timestamp tables. The
timestamp tables are used by the acs_merge_design -auto_update command to determine which designs are new, so that the
partitions which depend on the updated designs are recompiled by the acs_compile_design -update command. The subsequent
calls to the above command only analyze and elaborate the updated HDL files, and the corresponding designs are replaced in the
unmapped design in the destination directory.

SEE ALSO
acs_merge_design(2)
acs_compile_design(2)
analyze(2)
elaborate(2)
search_path(3)

acs_read_hdl 37
Synthesis Tool Commands Version S-2021.06-SP2

acs_report_user_messages
Reports the number of error, warning, and information messages.

SYNTAX
status acs_report_user_messages
[-total]
[-errors]
[-warnings]
[-infos]
[-reset]

ARGUMENTS
-total

Prints the total number of error messages that have occurred since the the current session began. The default is to print the number
of error messages since the last call to the acs_report_user_messages command.

-errors

Prints the number of error messages that have occurred since the last call to acs_report_user_messages.

-warnings

Prints the number of warning messages that have occurred since the last call to acs_report_user_messages.

-infos

Prints the number of informational messages that have occurred since the last call to acs_report_user_messages.

-reset

Resets the counters for the errors, warnings, and informational messages. However, subsequent calls to
acs_report_user_messages with the -total option prints the number of error, warning, and information messages since the start of
the session.

DESCRIPTION
The acs_report_user_messages command reports the number of error, warning, and information messages.

You can use any combination of the -errors, -warnings, and -infos options with the command. If no options are specified, then the
effect is the same as if all three of the options are specified; all three types of messages are printed. Note that the -total option is
independent of these three options.

The ACS chip-level compile commands acs_compile_design, acs_recompile_design, and acs_refine_design issue the
acs_report_user_messages -reset command when the commands begin.

acs_report_user_messages 38
Synthesis Tool Commands Version S-2021.06-SP2

EXAMPLES
The following example prints the number of error, warning, and information messages since the last call to
acs_report_user_messages:

prompt> acs_report_user_messages

The following example prints the number of warning and error messages that have occurred since the last call to
acs_report_user_messages:

prompt> acs_report_user_message -errors -warnings

The following example prints the number of errors since the start of the session:

prompt> acs_report_user_message -errors -total

SEE ALSO
acs_compile_design(2)
acs_recompile_design(2)
acs_refine_design(2)

acs_report_user_messages 39
Synthesis Tool Commands Version S-2021.06-SP2

add_module
Reads in a specified library file containing module functional information and uses it to update an existing technology library.

SYNTAX
status add_module
[-overwrite]
[-force]
[-permanent]
file_name
library_name
[-no_warnings]

Data Types

file_name string
library_name string

ARGUMENTS
-overwrite

Indicates that a group declared in file_name is to overwrite any group in library_name having the same name. Only groups added
by add_module or model can be overwritten. Groups included in the original library and groups added with the -permanent option
cannot be modified. If -force is specified, some library-level groups (wire_load, power_supply, and operating_conditions) included
in the original library can be modified. The other groups included in the original library and groups added with -permanent cannot
be modified.

-force

Indicates that some library-level groups and attributes declared in file_name can overwrite the same groups and attributes included
in the original library. The library-level groups are as follows:

wire_load
power_supply
operating_conditions.

The library-level attributes are as follows:

<k_factors>
in_place_swap_mode
default_wire_load_mode
default_wire_load_selection
default_wire_load_capacitance
default_wire_load_resistance
default_wire_load_area
default_operating_conditions

-permanent

add_module 40
Synthesis Tool Commands Version S-2021.06-SP2

Indicates to store groups declared in file_name in the library in such a way that they cannot be overwritten.

file_name

Specifies the name of the file in which one or more new groups containing module functional information are listed. The syntax of
this file is the same as that expected by read_lib, except that the file contains only library-level groups without the library() {} group
definition.

library_name

Specifies the name of the library to update. The library must reside in memory. This option can be a simple filename with no
directory specification and, therefore, no slash ("/") (for example, test_db or library.db). Simple filenames must be found in a
directory listed in the search_path. Alternatively, this option can be a complex filename, which has a directory specification (for
example, ~synopsys/dc/test.lib). Complex filenames are not included in the search_path.

-no_warnings

Indicates that all warning messages are suppressed. The default is to issue all warning messages. Warning messages can identify
serious library problems; use this option sparingly.

DESCRIPTION
This command reads in a library file and adds to the specified library only those groups with module functional information declared in
the library file. Groups are added to the library as if they were entered at the end of the original text of the library. If the tool finds any
errors while processing a group, it does not add that group to the library. You do not need a Library Compiler License to add groups
with module functionality to a technology library.

For details on library file syntax, see the Library Compiler manuals.

EXAMPLES
The following example adds the library file add_ram.lib, which contains module information, (that is, a RAM group) to the library
memory.

prompt> add_module add_ram.lib memory

The following example adds the library file romgen.lib, which contains a cell description of a ROM cell, to the cmos library. The -
permanent option indicates that the new cell cannot be overwritten.

prompt> add_module -permanent romgen.lib cmos

SEE ALSO
read_lib(2)
update_lib(2)
write_lib(2)

add_module 41
Synthesis Tool Commands Version S-2021.06-SP2

add_parameter
Define parameters that can be overridden by apply_power_model.

SYNTAX
status add_parameter
parameter_name
[-default default_value]
[-type type_name]
[-description description text]

Data Types
parameter_name string
default_value string
type_name buildtime, runtime, or rate
description text string
text description

ARGUMENTS
parameter_name

Specifies the name of the parameter to be defined inside a power model.

-default default_value

Specifies the default value of the parameter if there is no parameter mapping specified in the apply_power_model command.

-type type_name

When -type option is specified, the parameter defined is used for system-level IP power model. The parameter scope is within the
power model only and power models and power functions cannot access parameters that are defined outside of the power model in
which they are used.

Three types of parameters can be defined as follows:

1. Build time - for parameters that remain unchanged during run time

2. Run time - for parameters that can change during run time

3. Rate - for parameters that represent rate-based quantities that can change during run time

-description description text

Text description of the parameter.

add_parameter 42
Synthesis Tool Commands Version S-2021.06-SP2

DESCRIPTION
The add_parameter command is used to define parameters for use within a power model. A parameter can be used just like a regular
Tcl variable by prepending the parameter name with the $ keyword.

This command can only be defined within the define_power_model command and applied to a macro instance through the
apply_power_model command. It is an error if this command is executed through the load_upf command.

The -parameters option of the apply_power_model command can change the value of a parameter during application of the power
model on a macro instance. If the parameter is not found in the -parameter option, default value specifed in add_parameter will be
used.

A power model provides a self-contained environment for variables. Parameters defined outside a power model are not visible inside
the power model. Parameters defined within a power model are only visible inside the power model.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
define_power_model MODEL -for {lib_cell} {
add_parameter PD_NAME -default "PD" -description "power domain in model"
add_parameter process -type buildtime -default 1.0
add_parameter cache_miss -type rate -default 0.02
create_supply_net VDD
create_supply_net VSS
create_supply_set SS -function {power VDD} -function {ground VSS}
create_power_domain $PD_NAME -supply {primary SS} -include_scope
}

apply_power_model MODEL -parameters {{PD_NAME pd_macro}}

SEE ALSO
define_power_model(2)
apply_power_model(2)
report_power_model(2)

add_parameter 43
Synthesis Tool Commands Version S-2021.06-SP2

add_pg_pin_to_db
Converts a non-PG-pin-based logic library in compiled format (.db file) into a PG-pin-based logic library in .db format.

SYNTAX
status add_pg_pin_to_db
input_db_filename
-output pg_db_filename
[-mw_library_name mw_lib_name]
[-pg_map_file map_file]
[-pg_map_template template_filename]
[-expanded]
[-fast]
[-force_update]
[-verbose]

Data Types
input_db_filename string
pg_db_filename string
mw_lib_name list
map_file string
template_filename string

ARGUMENTS
input_db_filename

Specifies the name of the existing logic library in compiled format (.db file) that lacks PG pin data.

-output pg_db_filename

Specifies the name of the new PG-pin-based .db file generated by the conversion. This name must be different from the name of
the input .db file unless the -force_update option is used.

-mw_library_name mw_lib_name

Specifies the names of one or more Milkyway libraries containing the FRAM views of the input .db library file. The FRAM views
provide PG pin information used to update the library.

-pg_map_file map_file

Specifies the name of a text file that defines the mapping between non-PG-pin-based data and PG-pin-based data.

-pg_map_template template_filename

Specifies the file name a map template. If you use this option, the command generates only a map template file; it does not perform
a library update. You can edit the generated template file and use it to specify the PG mapping for a subsequent
add_pg_pin_to_db command.

-expanded

add_pg_pin_to_db 44
Synthesis Tool Commands Version S-2021.06-SP2

Generates an expanded rather than compressed PG map template. By default, when you use the -pg_map_template option, the
command generates a compressed PG map template, using wildcards to specify multiple mappings where possible, to reduce the
file size. Use this option to generate a PG map template with the wildcards expanded to individual names.

-fast

Generates a PG pin library from a non-PG pin library without using a PG map file. This option uses the information available in the
Milkyway FRAM view, the input non-PG pin library, or a combination of both. It is recommended that you use the FRAM view, which
helps identify the names of the cell's PG pins. If you omit the -mw_library_name option, the FRAM view is not used and the -fast
option can only infer the PG pin names if they are specified in the logic library's Liberty (.lib file) attributes: rail_connection,
input_signal_level, and output_signal_level.

-force_update

Forces the command to update the library data based on the input data and overwrite the existing data in the library. By default, the
command writes out a new .db library and retains the existing library.

-verbose

Writes out all sections of the PG map data, whether generated automatically or expanded from a compressed PG map file.

DESCRIPTION
The add_pg_pin_to_db command converts a non-PG-pin-based logic library in compiled format (.db file) into a PG-pin-based logic
library and writes out the new, updated library in .db format.

The command converts and updates a logic library automatically from the old rail_connection Liberty syntax or from a format that is
not based on PG pin syntax to a library with PG pin syntax. You specify an existing logic library in .db format and the related physical
libraries with Milkyway FRAM views, if available, and a PG map file.

The command gets information it needs to perform the conversion from the FRAM views in the Milkyway library or from the PG map
file, or both. The PG map file is a text file that specifies the mapping between signal pins and their related power and ground pins,
between PG pins and their corresponding voltage names, and between voltage names and voltage values.

You can use the add_pg_pin_to_db command with the -pg_map_template option to automatically generate a PG map template file,
which you can then edit to provide the specific mapping information. When you use this option, the command only writes out the PG
map template file and does not actually perform the library conversion. You first need to edit the template file, then use the command
again with the -pg_map_file option to perform the library conversion.

The options you can use depend on whether a Milkyway library with FRAM views is available:

With a complete Milkyway library

If all cells have single PG rail (one power rail and one ground rail), the -pg_map_file option is not required; use the -
mw_library_name option to allow the command to derive the mapping from the Milkyway FRAM view. If some cells have
multiple PG rails, the -pg_map_file option is required.

Without a Milkyway library (.db library only)

If you specify only a logic library (.db file), without using the -mw_library_name option, you need to use the -pg_map_file
option, whether the library uses single or multiple PG rails.

With a partial Milkyway library

If some cells exist in both the logic library and the Milkyway library while others exist only in the logic library, you need to use the
-pg_map_file option for the cells that are missing from the Milkyway library.

For more information, see "Adding PG Pin Syntax to Logic Libraries" in the "UPF Library Preparation Application Notes," available on
SolvNet.

add_pg_pin_to_db 45
Synthesis Tool Commands Version S-2021.06-SP2

EXAMPLES
The following example writes out a PG map template file named "pg.map" using information from the compiled logic library "old.db"
and the corresponding FRAM views in the Milkyway library named "mw_lib." This command does not convert the library; it only writes
out the PG map template file, which you can edit and use later for library conversion.

prompt> add_pg_pin_to_db old.db -mw_library_name {mw_lib} \

-pg_map_template pg.map

The following example converts a non-PG-pin-based logic library named "old.db" into a PG-pin-based library named "pg.db."

prompt> add_pg_pin_to_db old.db -mw_library_name {mw_lib} \

-pg_map_file pg.map -output pg.db

SEE ALSO
add_pg_pin_to_lib(2)

add_pg_pin_to_db 46
Synthesis Tool Commands Version S-2021.06-SP2

add_pg_pin_to_lib
Converts a non-PG-pin based logic library in Liberty format (.lib file) into a PG-pin-based logic library in .lib format.

SYNTAX
status add_pg_pin_to_lib
input_lib_filename
-output pg_lib_filename
[-mw_library_name mw_lib_name]
[-pg_map_file map_file]
[-pg_map_template template_filename]
[-common_shell_path common_shell_path]
[-expanded]
[-fast]
[-force_update]
[-verbose]

Data Types
input_lib_filename string
pg_lib_filename string
mw_lib_name list
map_file string
template_filename string
common_shell_path string

ARGUMENTS
input_lib_filename

Specifies the name of the existing logic library in Liberty format (.lib file) that lacks PG pin data.

-output pg_lib_filename

Specifies the name of the new PG-pin-based .lib file generated by the conversion. This name must be different from the name of the
input .lib file unless the -force_update option is used.

-mw_library_name mw_lib_name

Specifies the names of one or more Milkyway libraries containing the FRAM views of the input .lib library file. The FRAM views
provide PG pin information used to update the library.

-pg_map_file map_file

Specifies the name of a text file that defines the mapping between non-PG-pin-based data and PG-pin-based data, including the
power management attributes.

-pg_map_template template_filename

Specifies the file name a map template. If you use this option, the command generates only a map template file; it does not perform
a library update. You can edit the generated template file and use it to specify the PG mapping for a subsequent

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add_pg_pin_to_lib command.

-common_shell_path common_shell_path

Specifies a common shell path where lc_shell or dc_shell resides, to compile the input .lib using an older tool version. By default,
the current Library Compiler or Design Compiler tool version is used. Use this option for older .lib files, when the latest utility version
cannot compile the input .lib file due to new checking applied in the current version.

-expanded

Generates an expanded rather than compressed PG map template. By default, when you use the -pg_map_template option, the
command generates a compressed PG map template, using wildcards to specify multiple mappings where possible, to reduce the
file size. Use this option to generate a PG map template with the wildcards expanded to individual names.

-fast

Generates a PG pin library from a non-PG pin library without using a PG map file. This option uses the information available in the
Milkyway FRAM view, the input non-PG pin library, or a combination of both. It is recommended that you use the FRAM view, which
helps identify the names of the cell's PG pins. If you omit the -mw_library_name option, the FRAM view is not used and the -fast
option can only infer the PG pin names if they are specified in the logic library's Liberty (.lib file) attributes: rail_connection,
input_signal_level, and output_signal_level.

-force_update

Forces the command to update the library data based on the input data and overwrite the existing data in the library. By default, the
command writes out a new .lib library and retains the existing library.

-verbose

Writes out all sections of the PG map data, whether generated automatically or expanded from a compressed PG map file.

DESCRIPTION
The add_pg_pin_to_lib command converts a non-PG-pin based logic library in Liberty format (.lib file) into a PG-pin-based logic
library and writes out the new, updated library in .lib format.

The command converts and updates a logic library automatically from the old rail_connection Liberty syntax or from a format that is
not based on PG pin syntax to a library with PG pin syntax. You specify an existing logic library in .lib format and the related physical
libraries with Milkyway FRAM views, if available, and a PG map file.

The command gets information it needs to perform the conversion from the FRAM views in the Milkyway library or from the PG map
file, or both. The PG map file is a text file that specifies the mapping between signal pins and their related power and ground pins,
between PG pins and their corresponding voltage names, and between voltage names and voltage values.

You can use the add_pg_pin_to_lib command with the -pg_map_template option to automatically generate a PG map template file,
which you can then edit to provide the specific mapping information. When you use this option, the command only writes out the PG
map template file and does not actually perform the library conversion. You first need to edit the template file, then use the command
again with the -pg_map_file option to perform the library conversion.

The options you can use depend on whether a Milkway library with FRAM views is available:

With a complete Milkyway library

If all cells have single PG rail (one power rail and one ground rail), the -pg_map_file option is not required; use the -
mw_library_name option to allow the command to derive the mapping from the Milkyway FRAM view. If some cells have
multiple PG rails, the -pg_map_file option is required.

Without a Milkyway library (.lib library only)

If you specify only a logic library (.lib file), without using the -mw_library_name option, you need to use the -pg_map_file
option, whether the library uses single or multiple PG rails.

With a partial Milkyway library

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If some cells exist in both the logic library and the Milkyway library while others exist only in the logic library, you need to use the
-pg_map_file option for the cells that are missing from the Milkyway library.

For more information, see "Adding PG Pin Syntax to Logic Libraries" in the "UPF Library Preparation Application Notes," available on
SolvNet.

EXAMPLES
The following example writes out a PG map template file named "pg.map" using information from the Liberty logic library "old.lib" and
the corresponding FRAM views in the Milkyway library named "mw_lib." This command does not convert the library; it only writes out
the PG map template file, which you can edit and use later for library conversion.

prompt> add_pg_pin_to_lib old.lib -mw_library_name {mw_lib} \

-pg_map_template pg.map

The following example converts a non-PG-pin-based logic library named "old.lib" into a PG-pin-based library named "pg.lib."

prompt> add_pg_pin_to_lib old.lib -mw_library_name {mw_lib} \

-pg_map_file pg.map -output pg.lib

SEE ALSO
add_pg_pin_to_db(2)

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add_port_state
Adds state information to a supply port.

SYNTAX
string add_port_state
supply_port_name
-state {state_name state_value}

Data Types
supply_port_name string
state_name string
state_value string

ARGUMENTS
supply_port_name

Specifies the name of the supply port. Hierarchical names are allowed.

-state {state_name state_value}

Specifies the name and value of a state of the supply port. You can repeat this option. The state value can be one of the following:

A single floating point number that represents the nominal voltage for the specified state. For example, to define a state called
s88 with a nominal voltage of 0.88, use the following syntax:

-state {s88 0.88}

Three floating point numbers that represent the minimum, nominal, and maximum voltages of the specified state, respectively.
For example, to define a state called active_state with a minimum voltage of 0.88, a nominal voltage of 0.90, and a maximum
voltage of 0.92, use the following syntax:

-state {active_state 0.88 0.90 0.92}

NOTE: It is an error if minimum voltage is greater than (>) the nominal voltage or the nominal voltage is greater than (>) the
maximum voltage.

The keyword off, which indicates an inactive state. For example, to define an inactive state called off_state, use the following
syntax:

-state {off_state off}

DESCRIPTION

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This command adds state information to a supply port. The first occurrence of the supply_port_name option is the default state of the
supply port. You can use this to represent off-chip supply sources that are not driven by the testbench. This option defines the voltage
level supplied to the chip. It provides a convenient shortcut to facilitate verification and analysis without requiring the creation of a
power domain and a supply network within the verification environment. An error occurs if supply_port_name does not already exist
before executing this command.

This command returns the fully-qualified name from the current scope of the created port or a null string if the port is not created.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example shows the states and voltages of a supply port named VN1:

prompt> add_port_state VN1 \

-state {active_state 0.88 0.90 0.92} \
-state {off_state off}

SEE ALSO
add_pst_state(2)
create_pst(2)
report_pst(2)

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add_power_state
Adds state information to a supply set or a group or a domain.

SYNTAX
status add_power_state
[-supply | -group | -domain] object_name
[-simstate {simstate}]
[-update]
[-state state_name {[-supply_expr {supply_expression}]
[-logic_expr {logic_expression}]
[-simstate {simstate}]
[-illegal]}]*

Data Types
object_name string
simstate string
state_name string
supply_expression string
logic_expression string

ARGUMENTS
-supply | -group | -domain object_name

Specifies the name of a supply set, or the name of a group created with the create_power_state_group command, or the name of
a domain. The name should be a simple (nonhierarchical) name.

-state state_name

Specifies the name of the state of the supply set or the group or the domain. The name should be a simple (nonhierarchical) name.
This option can be specified multiple times in the same command.

-supply_expr {supply_expression}

Specifies a Boolean expression in terms of nets and their netstates. This option can only be specified when the object_name is a
supply set. The only operator allowed in the Boolean expression is && (AND operator). Each subexpression in the Boolean
expression specifies the net and netstate definitions. Each subexpression must have the following syntax:

net == netstate

The net can be power or ground and the netstate syntax must be one of the following:

status
`{status}
`{status, nom}
`{status, min, max}
`{status, min, nom, max}

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{status}
{status nom}
{status min max}
{status min nom max}

status can be OFF or FULL_ON

min, nom, and max are floating-point numbers representing the minimum, nominal, and maximum voltages of the specified
state, respectively.

NOTE: It is an error if min is greater than (>) nom or if nom is greater than (>) max.

If the status is FULL_ON, at least one voltage must be defined.

-logic_expr {logic_expression}

If the object_name is a supply set, then this option specifies a SystemVerilog Boolean expression in terms of logic nets and supply
nets. The -logic_expr option does not affect implementation and is intended to be used by simulation tools, to read and write
transparently.

If the object_name is a group or a domain, then this option specifies a Boolean expression in terms of supply
sets/groups/domains/PSTs and their states. The only operator allowed in the Boolean expression is &&.

-simstate {simstate}

Specifies a simstate for the power states associated with a supply set. Valid values are NORMAL, CORRUPT_ON_ACTIVITY,
CORRUPT, NOT_NORMAL, CORRUPT_STATE_ON_CHANGE, CORRUPT_STATE_ON_ACTIVITY and
CORRUPT_ON_CHANGE. This option can only be specified when the object_name is a supply set. The -simstate option does not
affect implementation and is intended to be used by simulation, so the tool reads and writes the information specified with this
option transparently.

This option can be specified for every state that is defined with the add_power_state command:

add_power_state -state state_name {-simstate simstate_value}.

This option can also be specified globally for the entire add_power_state command:

add_power_state -simstate simstate_value -state state_name {...}

However, the UPF standard does not use the -simstate globally. It is retained only for backward compatibility purposes and will be
obsolete in a future release.

-update

Specifies additional power states (supply set states or group states or domain statess) to add to an object. Also specifies additional
power state intent to add to an existing state.

For supply sets, this option can be used to add incremental information (-logic_expr, -supply_expr, -simstate) to an existing
supply set state.

For groups and domains, this option can be used to add incremental information (-logic_expr) to an existing group or domain state.

-illegal

Indicates that the state defined (for a supply set or a group) is an illegal state.

DESCRIPTION
This command adds state information to a supply set or a group.

If the object specified is a supply set, then use this command to set power states on the nets of a supply set and then use them as
supplies for the power state table. If the supply set does not already exist, this command issues an error.

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If the object specified is a group, then use this command to create the power state table by using supply sets, other groups or PSTs in
the -logic_expr option. The group should have been previously created using the create_power_state_group command. If the group
does not already exist, this command issues an error. To add additional group states to a group, the -update option must be used.

EXAMPLES
The following example shows the states and voltages of a supply set, SS1:

prompt> add_power_state SS1 \

-state HVp {-supply_expr {power == `{FULL_ON, 0.88, 0.90, 0.92}}}

prompt> add_power_state SS1 \

-state HPg {-supply_expr {ground == `{OFF}}}

The following example defines LV state, but omitting the details on voltages for SS2 supply set:

prompt> add_power_state SS2 \

-state LV {}

The following example defines a state ON for supply set SS1 where the supply_expression is a Boolean expression of power and
ground.

prompt> add_power_state -supply SS1\

-state ON {-supply_expr {power == {FULL_ON 0.8} && ground == {FULL_ON 0}}}

The following example shows how power states can be added to a group. Here 'GROUP1' is a power state group that has previously
been created with the create_power_state_group command. GS1 and GS2 are the names of the group states created. The system is
in state GS1 when supply set SS1 is in state ON1, and group GROUP2 defined in scope MID1 is in state ON1, and the PST PST1
defined in scope MID2 is in state ON1.

prompt> add_power_state -group GROUP1 \

-state GS1 {-logic_expr {SS1 == ON1 && MID1/GROUP2 == ON1 && MID2/PST1 == ON1}}
-state GS2 {-logic_expr {SS1 == ON2 && MID1/GROUP2 == ON2 && MID2/PST1 == ON2}}

SEE ALSO
create_power_state_group(2)
add_pst_state(2)
create_pst(2)
create_supply_set(2)
report_pst(2)

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add_pst_state
Defines the states of each of the supply nets for one possible state of the design.

SYNTAX
status add_pst_state
state_name
-pst table_name
-state supply_states

Data Types
state_name string
table_name string
supply_states list

ARGUMENTS
state_name

Specifies the name of the power state.

-pst table_name

Specifies the power state table (PST) to which this state applies.

-state supply_states

Lists the supply net state names in the corresponding order of the -supplies option listing in the create_pst command.

DESCRIPTION
The add_pst_state command defines the states of each of the supply nets for one possible state of the design. It is an error if the
number of supply state names is different from the number of supply nets within the power state table.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES

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The following example defines the supply net state names for the s1, s2 and s3 power states:

create_pst pt -supplies { PN1 PN2 SOC/OTC/PN3 }

add_pst_state s1 -pst pt -state { s08 s08 s08 }
add_pst_state s2 -pst pt -state { s08 s08 off }
add_pst_state s3 -pst pt -state { s08 s09 off }

SEE ALSO
add_port_state(2)
create_pst(2)
report_pst(2)

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add_row
Creates a list of rows in the design.

SYNTAX
status add_row
-within {coordinates}
[-direction horizontal | vertical]
[-flip_first_row]
[-no_double_back]
[-minimal_channel_height channel_height]
[-no_start_from_first_row]
[-tile_name tile_name]
[-snap_to_row_direction {wire_track | tile_width | none}]
[-snap_to_orthogonal_row_direction {existing_row | wire_track | none}]
[-left_offset left_offset]
[-right_offset right_offset]
[-top_offset top_offset]
[-bottom_offset bottom_offset]
[-allow_overlap]

Data Types
coordinates list
channel_height float
tile_name string
left_offset float
right_offset float
top_offset float
bottom_offset float

ARGUMENTS
-within {coordinates}

Specifies the boundary within which to create rows. For a rectangular region, specify the coordinates for the lower-left and upper-
right corners as {ll_x ll_y} {ur_x ur_y}}. For a rectilinear region, specify a list of rectilinear coordinates in either clockwise or
counterclockwise order.

-direction horizontal | vertical

Specifies the direction of rows to be created. By default, the direction of rows is the same as the direction of the base array where
the rows are added.

-flip_first_row

Flips the bottom row in a horizontal core area or the leftmost row in a vertical core area. The -flip_first_row and -no_double_back
options are mutually exclusive. By default, the first row is not flipped.

-no_double_back

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Creates rows without flipping one row in each pair. The -no_double_back and -flip_first_row options are mutually exclusive. By
default, the area can contain pairs of rows that are doubled back.

-minimal_channel_height channel_height

Specifies the amount of channel height to allocate for routing between rows. By default, the minimum channel height is 0.0.

-no_start_from_first_row

Specifies that the bottom row in a horizontal core area or the leftmost row in a vertical core area is not paired with the second row.
By default, the first row can form a row pair with the second row.

-tile_name tile_name

Specifies the name of the unit tile to use in rows. By default, the tile name is unit.

-snap_to_row_direction {wire_track | tile_width | none}

Specifies the snapping type in the row direction.

If you specify a snapping type of wire_track for a design with horizontal rows, the tool aligns the vertical-layer wire tracks of the tile
and the design. For a design with vertical rows, the tool aligns the horizontal-layer wire tracks of the tile and the design.

If you specify a snapping type of tile_width for a design with horizontal rows, the tool separates the left edge of the base array
boundary and the starting left edge of the row by using a multiple of the tile width. For a design with vertical rows, the tool separates
the bottom edge of the base array boundary and the bottom edge of the first row by using a multiple of the tile width.

If you specify a snapping type of none for a design with horizontal rows, the tool creates each new row from the left edge as
specified by the -within option. For a design with vertical rows, the tool creates each new row from the bottom edge as specified by
the -within option.

By default, the snapping type is wire_track.

-snap_to_orthogonal_row_direction {existing_row | wire_track | none}

Specifies the snapping type in the orthogonal row direction.

If you specify an orthogonal snapping type of existing_row, the tool attempts to align the new row with an existing row that is within
one tile height of the specified location. The existing row must have the same tile pattern and orientation as the first new row. If the
tool cannot find an existing row that meets the criteria, the tool snaps the new row to a wire track.

If you specify a snapping type of wire_track for a design with horizontal rows, the tool aligns the horizontal-layer wire track of the
tile and the design. For a design with vertical rows, the tool aligns the vertical-layer wire tracks of the tile and the design.

If you specify a snapping type of none for a design with horizontal rows, the tool creates the first row at the bottom edge as
specified by the -within option. For a design with vertical rows, the tool creates the first row at the left edge as specified by the -
within option.

By default, the orthogonal row snap type is existing_row.

-left_offset left_offset

Specifies the minimum space between the new rows and the left boundary specified by the -within option. By default, the left offset
is 0.

-right_offset right_offset

Specifies the minimum space between the new rows and the right boundary specified by the -within option. By default, the right
offset is 0.

-top_offset top_offset

Specifies the minimum space between the new rows and the top boundary specified by the -within option. By default, the top offset
is 0.

-bottom_offset bottom_offset

Specifies the minimum space between the new rows and the bottom boundary specified by the -within option. By default, the

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bottom offset is 0.

-allow_overlap

Specifies that overlapped rows are allowed. By default, overlapped rows are not allowed, whether they are same height or not.

DESCRIPTION
This command adds rows to the specified area.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example creates rows in a rectangular region.

prompt> add_row -within {{100 100} {300 300}} -tile_name unit1

info: created 6 rows.
1

The following example creates rows in the specified rectilinear region.

prompt> add_row -within {{30.0 30.0} {30.0 50.0} \

{40.0 50.0} {40.0 60.0} {50.0 60.0} {50.0 40.0} \
{60.0 40.0} {60.0 30.0} {30.0 30.0}} -tile_name unit2

Info: 18 rows are added.

1

The following example creates rows and sets left/right offset of 5 units and top/bottom offset of 10 units.

prompt> add_row -within {{100 100} {300 300}} \

-left_offset 5 -right_offset 5 \
-top_offset 10 -bottom_offset 10 \

Info: 6 rows are added.

1

The following example creates rows with a channel height of 3.69 units between the rows.

prompt> add_row -within {{30 148} {30 159} \

{645 159} {645 166} {817 166} \
{817 159} {1432 159} {1432 148}} \
-minimal_channel_height 3.69
Info: created 4 rows.
1

The following example creates rows that overlap with the existing rows in the region.

prompt> add_row -within {{30 148} {30 159} \

{645 159} {645 166} {817 166} \
{817 159} {1432 159} {1432 148}} \
-allow_overlap
Warning: Existing row (id = 11279) found in the specified new row creation region. (MWUI-183)
Warning: Existing row (id = 11280) found in the specified new row creation region. (MWUI-183)

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Warning: Existing row (id = 11281) found in the specified new row creation region. (MWUI-183)
Warning: Existing row (id = 11282) found in the specified new row creation region. (MWUI-183)
Warning: Existing row (id = 11283) found in the specified new row creation region. (MWUI-183)
Info: created 5 rows.
1

SEE ALSO
cut_row(2)
write_floorplan(2)

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add_state_transition
Adds state transitions to an existing UPF object.

SYNTAX
status add_state_transition
[-supply | -domain | -group]object_name
[-update]
[-transition transition_name {through_list}]}]*
[-complete]

Data Types
transition_name string

ARGUMENTS
-supply | -domain | -group object_name

Specifies the name of a supply set, power domain or power state group to which the transitions will be added.

-update

Used when updating an already existing transition.

-transition transition_name

Specifies the name of a transition to be added to the object. This option can be specified multiple times in the same command.

-complete

Indicates that the transitlion list is complete. Any new transitions defined after the command with -complete is given will result in an
error.

DESCRIPTION
This command defines named state transitions between power states of an object. This is a UPF 3.0 command and it replaces the
describe_state_transition command.

The allwed object types, in case no type is specified through options, are the following:

- Power Domain
- Supply Set
- Power State Group
- Power State Table
- Supply Port

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- Supply Net
- Power Switch

If the specified doesn not exist or is not one of these types, the command issues an error.

Multiple transitions can be defined in the same command, and the initial and final states of each transition can be specified either
using two separate -from and -to lists or a -paired list. If none of these are specified the command issues an error. Furthermore, the
same state cannot be an initial and final state of the same transition, and specifying this will cause the command to return an error.

Synopsys has a specific extension consisted of the -through option, which is a list of intermediate states to the -from and -to lists. If
this option is specified without the -from or -to option, the command issues an error.

Design Compiler doesn not preserve this command through hierarchical flow, a warning will be issued from characterize when this
command is seen.

Design Compiler only parses and preserves this command.

EXAMPLES
Following examples show different usages of add_state_transition command and the outcome.

prompt> add_state_transition -supply MID_SS \

-transition {turn_on -from [list OFF PWR_OFF] -to [list ON PWR_ON] -legal} \
-transition {turn_off -from [list ON PWR_ON] -to [list OFF PWR_OFF] -legal} \
-complete
1

prompt> add_state_transition -domain supply_set_1 \

-transition {failed_transition -from OFF -to ON -legal}
Error: Object supply_set_1 isn't a defined power domain. (UPF-901)

prompt> add_state_transition MID_PD \

-transition {failed_transition -from ON -through TRAN}
Error: State list -through can't be defined if -from or -to lists are empty. (UPF-897)

prompt> add_state_transition MID_SS -transition {failed_transition}

Error: State lists -from and -to can't be empty if -paired state list is not defined. (UPF-896)

prompt> add_state_transition MID3_SS -transition {failed_transition -from OFF -to ON}

Error: Object MID3_SS wasn't found (UPF-899)

SEE ALSO
describe_state_transition(2)

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add_supply_state
Adds state information to a supply object.

SYNTAX
string add_supply_state
supply_name
-state {state_name state_value}

Data Types
supply_name string
state_name string
state_value string

ARGUMENTS
supply_name

Specifies the name of the supply port, supply net or supply set function. Hierarchical names are allowed.

-state {state_name state_value}

Specifies the name and value of a state of the supply. You can repeat this option in the command to define multiple supply states.

The supply state value can be specified as one of the following:

A single floating-point number that represents the nominal voltage for the named state:

-state {s88 0.88}

The keyword off, which represents the inactive state:

-state {off_state off}

DESCRIPTION
The add_supply_state command adds state information to a supply object for a UPF power state table. The command specifies the
name of the supply object and the possible states of the object. Each state is specified as a state name and the voltage level for that
state.

You can specify the voltage level as a single nominal value, or the keyword off to indicate the off state.

Use the create_pst command first, then the add_supply_state command to specify the names and voltages of the possible states for
each supply, and finally the add_pst_state command to specify the allowed combinations of supply states. Here is an example:

# Create power state table, specify supply ports or nets for table

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create_pst MyPST -supplies { PN1 PN2 SOC/PN3 }

# Specify supply states and corresponding voltages

add_supply_state PN1 -state {sLO 0.88}
add_supply_state PN2 -state {sLO 0.88} -state {sHI 0.99}
add_supply_state SOC/PN3 -state {sLO 0.88} -state {PDOWN off}

# Specify power states (allowed combinations of supply states)

add_pst_state S1 -pst MyPST -state {sLO sLO sLO}
add_pst_state S2 -pst MyPST -state {sLO sLO PDOWN}
add_pst_state S3 -pst MyPST -state {sLO sHI PDOWN}

The power state table defines the legal combinations of states that can exist at any given time during the operation of the design. The
supply states sLO, sHI, and PDOWN represent the low voltage, high voltage, and power-down states of the supplies. The power states
S1, S2, and S3 each refer to a specific combination of supply states for the supplies listed in the create_pst command.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example shows the states and voltages of a supply set function named ss1.power:

prompt> add_supply_state ss1.power \

-state {active_state 0.88} \
-state {off_state off}

SEE ALSO
add_port_state(2)
add_pst_state(2)
create_pst(2)
report_pst(2)

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add_to_collection
Adds objects to a collection, resulting in a new collection. The base collection remains unchanged.

SYNTAX
collection add_to_collection
[-unique]
collection1
object_spec

Data Types
collection1 collection
object_spec list

ARGUMENTS
-unique

Indicates that duplicate objects are to be removed from the resulting collection. By default, duplicate objects are not removed.

collection1

Specifies the base collection to which objects are to be added. This collection is copied to the result collection, and objects matching
object_spec are added to the result collection. The collection1 option can be the empty collection (empty string), subject to some
constraints, as explained in the DESCRIPTION section.

object_spec

Specifies a list of named objects or collections to add.

If the base collection is heterogeneous, only collections can be added to it.

If the base collection is homogeneous, the object class of each element in this list must be the same as in the base collection. If it is
not the same class, it is ignored. From heterogeneous collections in the object_spec, only objects of the same class of the base
collection are added. If the name matches an existing collection, the collection is used. Otherwise, the objects are searched for in
the database using the object class of the base collection.

The object_spec has some special rules when the base collection is empty, as explained in the DESCRIPTION section.

DESCRIPTION
The add_to_collection command allows you to add elements to a collection. The result is a new collection representing the objects in
the object_spec added to the objects in the base collection.

Elements that exist in both the base collection and the object_spec, are duplicated in the resulting collection. Duplicates are not

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removed unless you use the -unique option. If the object_spec is empty, the result is a copy of the base collection.

If the base collection is homogeneous, the command searches in the database for any elements of the object_spec that are not
collections, using the object class of the base collection. If the base collection is heterogeneous, all implicit elements of the
object_spec are ignored.

When the collection1 argument is the empty collection, some special rules apply to the object_spec. If the object_spec is non-empty,
there must be at least one homogeneous collection somewhere in the object_spec list (its position in the list does not matter). The first
homogeneous collection in the object_spec list becomes the base collection and sets the object class for the function. The examples
show the different errors and warnings that can be generated.

The append_to_collection command has similar semantics as the add_to_collection command; however, the
append_to_collection command can be much more efficient in some cases. For more information about the command, see the man
page.

For background on collections and querying of objects, see the collections man page.

EXAMPLES
The following example uses the get_ports command to get all of the ports beginning with 'mode' and then adds the "CLOCK" port.

prompt> set xports [get_ports mode*]

{mode[0] mode[1] mode[2]}
prompt> add_to_collection $xports [get_ports CLOCK]
{mode[0] mode[1] mode[2] CLOCK}

The following example adds the cell u1 to a collection containing the SCANOUT port.

prompt> set so [get_ports SCANOUT]

{SCANOUT}
prompt> set u1 [get_cells u1]
{u1}
prompt> set het [add_to_collection $so $u1]
{u1}
prompt> query_objects -verbose $het
{{port SCANOUT} {cell u1}}

The following examples show how the add_to_collection command behaves when the base collection is empty. Adding two empty
collections yields the empty collection. Adding an implicit list of only strings or heterogeneous collections to the empty collection
generates an error message, because no homogeneous collections are present in the object_spec list. Finally, if one homogeneous
collection is present in the object_spec list, the command succeeds, even though a warning message is generated. The example uses
the variable settings from the previous example.

prompt> sizeof_collection [add_to_collection "" ""]

0

prompt> set A [add_to_collection "" [list a $het c]]

Error: At least one homogeneous collection required for argument 'object_spec'
to add_to_collection when the 'collection' argument is empty (SEL-014)

prompt> add_to_collection "" [list a $het $sp]]

Warning: Ignored all implicit elements in argument 'object_spec'
to add_to_collection because the class of the base collection
could not be determined (SEL-015)
{SCANOUT u1 SCANOUT}

SEE ALSO

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append_to_collection(2)
collections(2)
query_objects(2)
remove_from_collection(2)
sizeof_collection(2)

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add_to_rp_group
Adds a cell, hierarchical group, or keepout to an existing relative placement group.

SYNTAX for Leaf Cells

status add_to_rp_group
rp_groups
-leaf cell_names
[-column integer]
[-row integer]
[-pin_align_name pin_name]
[-orientation direction]
[-alignment bottom-left | bottom-right]
[-num_rows integer]
[-num_columns integer]
[-free_placement]

Data Types
rp_groups list or collection
cell_names cells
pin_name string
direction list of strings

SYNTAX for Hierarchical Groups

status add_to_rp_group
rp_groups
-hierarchy group_name
[-instance instance_name]
[-column integer]
[-row integer]
[-orientation direction]
[-alignment bottom-left | bottom-right]

Data Types
group_name list or collection
instance_name cell

SYNTAX for Keepouts

status add_to_rp_group
rp_groups
-keepout keepout_name

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[-column integer]
[-row integer]
[-width integer]
[-height integer]
[-type hard | soft | space]

Data Types
keepout_name string

ARGUMENTS
rp_groups

Specifies the relative placement groups in which to add an item. The groups must all be in the same design.

-leaf cell_names

Specifies the name of a cell to add to the relative placement groups in rp_groups. The specified cell must be in the design that
contains the relative placement groups in rp_groups. Multiple cells are accepted when the -free_placement option is specified.

-column integer

Specifies the column position in which to add the item. If you do not specify the column position, the default is zero.

-row integer

Specifies the row position in which to add the item. If you do not specify the row position, the default is zero.

-pin_align_name pin_name

Specifies the name of the pin to use for pin alignment of this cell with other cells in a group. This overrides the default pin name
specified for the relative placement group into which it is being added. This option can only be used when adding a leaf cell with the
-leaf option.

-orientation direction

Specifies the placement orientation of the cell or relative placement group being added. The option functions differently for cells
from for relative placement groups. For cells, specify the orientation with respect to the group to which the cell is being added. You
can specify a list of possible orientations, and the tool chooses the first legal orientation for the cell. For relative placement groups,
the orientation you specify overrides any group orientation that was specified.

You can specify the direction using DEF syntax:

DEF syntax:
N, W, S, E, FN, FW, FS, FE

This option can only be used to add a leaf cell with the -leaf option or hierarchical instance with the -hierarchy and -instance
options.

-alignment bottom-left | bottom-right

Specifies the alignment to use when placing the cell or group with respect to its parent group.

If a relative placement group has the -compress option set, and you add an element in that group with the -alignment bottom-
right option, then the alignment type of that element is ignored.

-num_rows integer

Specifies the number of rows to which you add the leaf cell. You can specify multiple rows, ranging from 1 to 255. The default is 1 if
you do not specify this option.

-num_columns integer

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Specifies the number of columns to which you add the leaf cell. You can specify multiple columns, ranging from 1 to 255. The
default is 1 if you do not specify this option. You cannot use the bottom-right and bottom-pin alignment settings for a leaf cell that
occupies multiple columns.

-free_placement

Specifies that the cells being provided using -leaf option must be placed randomly, that is, similar to the cells of a bound. These
cells can be added in multiple locations using the -num_rows and -num_columns options. The width and height of the placement
area is automatically calculated for free placement cells placed inside relative placement group. You might need to specify the -
width option when free placement cells are being added to boundary columns and the -height option when cells are being added to
boundary rows. The cell being added should not belong to any other bound.

-hierarchy group_name

Specifies the relative placement group to be added hierarchically to the relative placement groups in rp_groups.

-instance instance_name

Specifies the hierarchical cell in which to instantiate the relative placement group specified with the -hierarchy option. The cell must
be an instance of the reference design that contains the relative placement group specified with -hierarchy and must be in the
design containing the relative placement groups specified in rp_groups. This option can be used only when adding a relative
placement group with the -hierarchy option.

-keepout keepout_name

Specifies the name of the keepout to be added to the relative placement groups in rp_groups. Although the keepout is not a design
object, you name the keepout to refer to it after it is created.

-width integer

Specifies the width of the keepout being added when used with -keepout. Unit for keepout width is the width of the site row for a
particular library. If you do not specify the width, the keepout defaults to the width of the column into which the keepout is being
added.

It also specifies the width of the placement area for multiple cells being added with the -free_placement option. The unit is the
width of one site of site row.

-height integer

Specifies the height of the keepout being added when used with the -keepout option. Unit for keepout height is the height of the
site row for a particular library. If you do not specify the height, the default value is height of the row of relative placement group to
which the keepout is added.

It also specifies the height of the placement area for multiple cells being added with the -free_placement option. The unit is the
height of the site row.

-type hard | soft | space

Specifies whether a keepout is hard, soft, or space.

A hard keepout keeps everything out of a location during legalization. This is the default.

A soft keepout allows non-relative-placement cells to come into its location during the legalization stage.

A space keepout allows non-relative-placement cells to come into its location during placement.

DESCRIPTION
This command adds an item to the specified relative placement groups. The relative placement groups must have been previously
defined by using the create_rp_group command. The item can be either a leaf cell, a relative placement group, or a keepout. The
item is placed in a particular lattice position of the group as specified by a row and column.

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Multicorner-Multimode Support

This command has no dependency on scenario-specific information.

EXAMPLES
The following example uses add_to_rp_group to add a cell to an existing relative placement group and then adds that group
hierarchically to another existing group:

prompt> get_rp_groups ripple::grp_ripple

{ripple::grp_ripple}

prompt> add_to_rp_group ripple::grp_ripple -leaf carry_in_1

{ripple::grp_ripple}

prompt> add_to_rp_group example3::top_group -hier grp_ripple -instance U2

{example3::top_group}

prompt> add_to_rp_group example3::top_group -leaf { U1 U2 U3 U4 U5 } \

-row 0 -column 1 -num_rows 2 -num_columns 3 -free_placement
{example3::top_group}

SEE ALSO
create_rp_group(2)
remove_rp_groups(2)
write_rp_groups(2)

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alias
Creates a pseudo-command that expands to one or more words, or lists current alias definitions.

SYNTAX
string alias
[name]
[def]

Data Types
name string
def string

ARGUMENTS
name

Specifies a name of the alias to define or display. The name must begin with a letter, and can contain letters, underscores, and
numbers.

def

Expands the alias. That is, the replacement text for the alias name.

DESCRIPTION
The alias command defines or displays command aliases. With no arguments, the alias command displays all currently defined
aliases and their expansions. With a single argument, the alias command displays the expansion for the given alias name. With more
than one argument, an alias is created that is named by the first argument and expanding to the remaining arguments.

You cannot create an alias using the name of any existing command or procedure. Thus, you cannot use alias to redefine existing
commands.

Aliases can refer to other aliases.

Aliases are only expanded when they are the first word in a command.

EXAMPLES
Although commands can be abbreviated, sometimes there is a conflict with another command. The following example shows how to
use alias to get around the conflict:

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prompt> alias q quit

The following example shows how to use alias to create a shortcut for commonly-used command invocations:

prompt> alias include {source -echo -verbose}

prompt> alias rt100 {report_timing -max_paths 100}

After the previous commands, the command include script.tcl is replaced with source -echo -verbose script.tcl before the
command is interpreted.

The following examples show how to display aliases using alias. Note that when displaying all aliases, they are in alphabetical order.

prompt> alias rt100

rt100 report_timing -max_paths 100

prompt> alias
include source -echo -verbose
q quit
rt100 report_timing -max_paths 100

SEE ALSO
unalias(2)

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alib_analyze_libs
Reads in the target library files, analyzes each of them separately, and creates the corresponding alib files.

SYNTAX
integer alib_analyze_libs

DESCRIPTION
This command parses the target_library string. For each of the specified target libraries, the command attempts to find a valid alib. If
no valid alib is found for target library X, library analysis occurs for X and the result is stored as X.alib in the
alib_library_analysis_path variable directory. Note that the analysis is not affected by dont_use settings in the script where the
command is issued.

EXAMPLES
Use the following command to analyze the x.db and y.db libraries:

set target_library "x.db y.db"

set alib_library_analysis_path "./out"
alib_analyze_libs

Two files, x.db.alib and y.db.alib are generated in a versioned directory under "./out". The directory is named "./out/alib-N", where N is
the alib version number. To load these alibs, set the alib_library_analysis_path variable to ./out in your compile script. You do not need
to specify the directory name, since this detail is managed entirely by the tool.

SEE ALSO
alib_library_analysis_path(3)
OPT-1310(n)
OPT-1311(n)

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all_active_scenarios
Lists the active scenarios available in memory.

SYNTAX
string all_active_scenarios

ARGUMENTS
This command has no arguments.

DESCRIPTION
This command displays all active scenarios currently in memory. This list excludes scenarios that are inactive.

Creation and usage of scenarios is available with Design Compiler Graphical.

Multicorner-Multimode Support
This command uses information from all active scenarios.

EXAMPLES
The following example uses the all_active_scenarios command to list the active scenarios.

prompt> create_scenario MODE1

prompt> create_scenario MODE2
prompt> create_scenario MODE3
prompt> set_active_scenarios {MODE1 MODE3}
prompt> all_active_scenarios
MODE1 MODE3

SEE ALSO
all_scenarios(2)
create_scenario(2)

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current_scenario(2)
remove_scenario(2)
set_active_scenarios(2)

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all_clock_gates
Returns a collection of clock-gating cells or pins in the current design.

SYNTAX
collection all_clock_gates
[-no_hierarchy]
[-clock clock_name]
[-cells]
[-enable_pins]
[-clock_pins]
[-output_pins]
[-test_pins]
[-observation_pins]

Data Types
clock_name string

ARGUMENTS
-no_hierarchy

Limits the search to only the current level of hierarchy. Subdesigns are not searched. By default, the search spans the full hierarchy
down from the current level.

-clock clock_name

In the search, considers only clock-gating cells for registers originally clocked by clock_name. By default, the search considers
registers clocked by all clocks.

-cells

Returns cells. This is the default behavior.

-enable_pins

Returns enable pins instead of cells.

-clock_pins

Returns clock input pins instead of cells.

-output_pins

Returns the output pins of the clock-gating cells that generate the gated clocks instead of the cells.

-test_pins

Returns test_mode or scan_enable input pins instead of cells.

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-observation_pins

Returns the output pins of the observation logic, instead of cells.

DESCRIPTION
This command returns a collection of clock-gating cells or pins in the current instance, filtered by the specified options. By default, the
command lists all clock-gating cells in the design. If you specify clock_name, the command lists only the clock-gating cells in the
transitive fanout of the specified clock. The -cells option, which is the default, can be combined with one or more of the pins options.

Self-gating cells inserted by Power Compiler are excluded from the search. Use the all_self_gates command to get information about
self-gating cells.

EXAMPLES
The following example tags all clock gates for registers originally clocked by CLK for removal:

prompt> remove_clock_gating -gating_cells [all_clock_gates -clock CLK]

The following example returns a list of test pins for all clock gates for registers originally clocked by CLK:

prompt> all_clock_gates -test_pins -clock CLK

SEE ALSO
current_design(2)
current_instance(2)
report_clock_gating(2)

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all_clocks
Returns a collection of all clocks in the current design.

SYNTAX
collection all_clocks

ARGUMENTS
This command has no arguments.

DESCRIPTION
Returns a collection containing all clocks in the current design. The clocks must be defined in the design before running this command.

To create clocks, use the create_clock command. To remove clocks, use the remove_clock command. To list detailed information
about all clocks in the design, use the report_clock command.

Multicorner-Multimode Support
This command uses information from the current scenario only.

EXAMPLES
The following example applies the set_dont_touch_network command to all clocks in the current design:

prompt> set_dont_touch_network [all_clocks]

SEE ALSO
create_clock(2)
remove_clock(2)
report_clock(2)
set_dont_touch_network(2)

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all_connected
Returns the objects connected to a net, port, pin, net instance, or pin instance.

SYNTAX
collection all_connected
[-leaf]
object

Data Types
object string

ARGUMENTS
-leaf

Specifies that only leaf pins are returned for a hierarchical net. For nonhierarchical nets, there is no difference in output.

object

Specifies the object whose connections are returned. The object must be a net, port, pin, net instance, or pin instance.

DESCRIPTION
The all_connected command returns a collection of objects connected to the specified net, port, pin, net instance, or pin instance. A
net instance is a net in the hierarchy of the design. A pin instance is a pin on a cell in the hierarchy of a design.

If the -leaf option is used, a list of leaf pins of the net is returned.

To connect nets to ports or pins, use the connect_net command. To break connections, use the disconnect_net command.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example uses all_connected to return the objects connected to MY_NET:

prompt> all_connected MY_NET

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prompt> connect_net MY_NET OUT3

Connecting net 'MY_NET' to port 'OUT3'.

prompt> connect_net MY_NET U65/Z

Connecting net 'MY_NET' to pin 'U65/Z'.

prompt> all_connected MY_NET

{OUT3 U65/Z}

prompt> all_connected OUT3

{MY_NET}

prompt> all_connected U65/Z

{MY_NET}

This example uses all_connected to associate net load capacitance with the net n47, which is connected to the pin instance C/Z:

prompt> set_load 0.147 [all_connected [get_pins U0/U1/C/Z]]

Set "load" attribute to 0.147 for net "U0/U1/n47"

SEE ALSO
all_inputs(2)
all_outputs(2)
connect_net(2)
create_net(2)
current_design(2)
disconnect_net(2)
remove_net(2)

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all_critical_cells
Returns a collection of critical leaf cells in the top hierarchy of the current design.

SYNTAX
collection all_critical_cells
[-slack_range range_value]

Data Types
range_value float

ARGUMENTS
-slack_range range_value

Specifies a margin of slack for searching top-hierarchy leaf cells in paths whose slacks are in the specified range_value relative to
the worst slack of the current design. A top-hierarchy leaf cell is a cell in the top hierarchy and with no hierarchy underneath.

The range_value must be expressed in the same units as the technology library used during optimization. In addition, the
range_value must be positive or 0.0. If no range_value is specified, the default is 0.0. A range_value of 0.0 means that top-hierarchy
leaf cells in the most critical paths (those with the worst violations) are returned. If a positive range_value is specified, all top-
hierarchy leaf cells are returned if they are in near-critical paths with slacks in the range_value relative to the worst slack of the
current design.

DESCRIPTION
The all_critical_cells command returns a collection of leaf cells that are in the top hierarchy and in some path with a slack in the
range_value relative to the worst slack of the current design. This command returns only those cells with no hierarchy underneath.

If all timing paths passing through a cell are unconstrained, the cell is assumed to be non-critical, and is not returned. You can use this
command, along with the group command, to group together into a new subhierarchy those cells in the most critical paths. Then you
can try various optimization techniques on the new subhierarchy.

Multicorner-Multimode Support
This command uses information from the current scenario only.

EXAMPLES
The following example lists all top-hierarchy leaf cells in the worst critical paths of the current design:

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prompt> all_critical_cells

The following example lists all top-hierarchy leaf cells in those paths within range 5.0 relative to the worst slack of the current design:

prompt> all_critical_cells -slack_range 5.0

The following example groups all top-hierarchy leaf cells in the worst critical paths into a new hierarchy, called CRIT, under the top
hierarchy of the current design:

prompt> group [all_critical_cells] -design_name CRIT

The following example reports cell connections of all top-hierarchy leaf cells in the worst critical paths of the current design.

prompt> report_cell -connections [all_critical_cells]

SEE ALSO
all_critical_pins(2)
current_design(2)
group(2)
report_cell(2)

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all_critical_pins
Returns a collection of critical endpoints or startpoints in the current design.

SYNTAX
collection all_critical_pins
[-type endpoint | startpoint]
[-slack_range range_value]

Data Types
range_value float

ARGUMENTS
-type endpoint | startpoint

Specifies that the pins or ports to be searched are either timing endpoints or timing startpoints. The default is endpoint.

-slack_range range_value

Specifies a margin of slack for searching timing endpoints (or startpoints) in paths whose slacks are in the specified range_value
relative to the worst slack of the current design. The range_value must be expressed in the same units as the technology library
used during optimization. In addition, the range_value must be positive or 0.0. If no range_value is specified, the default is 0.0. A
range_value of 0.0 means that endpoints (or startpoints) in the most critical paths (those with the worst violations) will be returned. If
a positive range_value is specified, endpoints (or startpoints) in near-critical paths with slacks in the range_value relative to the
worst slack of the current design will be returned.

DESCRIPTION
The all_critical_pins command returns a collection of endpoints (or startpoints) that are in some timing path with a slack in the
range_value relative to the worst slack of the current design. For a pin, if all timing paths passing through it are unconstrained, it is
assumed to be non-critical, and it will not be returned.

This command may be used together with the all_fanin or all_fanout command to report useful information; for example, cells in the
transitive timing fanin cone of the most critical endpoints.

Multicorner-Multimode Support
This command uses information from the current scenario only.

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EXAMPLES
The following example lists all endpoints in the worst critical paths of the current design:

prompt> all_critical_pins

The following example lists all startpoints in those paths within range 5.0 relative to the worst slack of the current design:

prompt> all_critical_pins -type startpoint -slack_range 5.0

The following example reports cells in the 3-level transitive fanin timing cone of endpoints in the worst critical paths:

prompt> report_cell [all_fanin -to [all_critical_pins] \

-only_cells -levels 3 -flat]

The following example reports the logic in the transitive fanin of endpoints in the worst critical paths of the current design:

prompt> report_transitive_fanin -to [all_critical_pins]

SEE ALSO
all_critical_cells(2)
all_fanin(2)
current_design(2)
group(2)
report_cell(2)
report_transitive_fanin(2)
report_transitive_fanout(2)

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all_designs
Returns a collection containing all designs in the current design.

SYNTAX
collection all_designs

ARGUMENTS
There are no arguments to this command.

DESCRIPTION
The all_designs command returns a collection containing the designs in the current design hierarchy in bottom-up order. You must
set the current design using the current_design command before using all_designs.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

SEE ALSO
current_design(2)

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all_dont_touch
Returns a collection of dont_touch cells or nets from the current design or from the specified input collection.

SYNTAX
collection all_dont_touch
-cells | -nets
[input_coll]

Data Types
input_coll string

ARGUMENTS
-cells

Specifies that all cells with the dont_touch attribute are to be returned. The -cells and -nets options are mutually exclusive.

-nets

Specifies that all nets with the dont_touch attribute are to be returned. The -cells and -nets options are mutually exclusive.

input_coll

Searches the specified input collection and returns the collection of cells or nets having the dont_touch attribute. Objects are to be
searched only from the content of input_coll rather than from the entire design. By default, this option is off.

DESCRIPTION
This command returns the collection of cells or nets that have the dont_touch attribute from the design or from a list that you specify.
You can use wildcard characters, such as an asterisk (*) or question mark (?), when specifying the input cell list.

The command returns a standard Tcl collection. You can perform all of the generic collection-manipulating commands, such as
foreach_in_collection, sizeof_collection, and so on, on this collection handle.

Multicorner-Multimode Support
This command uses information from the current scenario only.

EXAMPLES

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The following example shows the collection of all cells with the dont_touch attribute in the design:

prompt> all_dont_touch -cells

{U20 U21 U23 SBLK/U1 SBLK/U2}

The following example shows the collection of all nets with the dont_touch attribute from an existing collection where COLL is its
handle:

prompt> all_dont_touch -nets $COLL

{n2 n5 SBLK/n2}

SEE ALSO
foreach_in_collection(2)
get_attribute(2)
get_cells(2)
get_nets(2)
report_attribute(2)
set_attribute(2)
set_dont_touch(2)
set_dont_touch_network(2)
sizeof_collection(2)

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all_drc_violated_nets
Returns a collection of DRC-violated nets from the current design or from the specified input collection.

SYNTAX
collection all_drc_violated_nets
-max_capacitance | -max_transition | -max_fanout
[input_coll]
[-bound upper]
[-threshold threshold]

Data Types
input_coll collection
upper float
threshold float

ARGUMENTS
-max_capacitance

Returns the collection of maximum capacity nets that violate design rule checking (DRC), as designated by drc_violated_nets.

-max_transition

Returns the collection of maximum transition nets that violate DRC, as designated by drc_violated_nets.

-max_fanout

Returns the collection of maximum fanout nets that violate DRC, as designated by drc_violated_nets.

input_coll

Searches the specified input collection and returns the requested collection of nets that violate DRC constraints. Objects are
searched only from the contents of the specified input collection, rather than from the design.

-bound upper

Captures all DRC-violated nets that have values less than or equal to the bound specified by upper. By default, this option is off.

-threshold threshold

Captures all DRC-violated nets that have values greater than or equal to the threshold specified by threshold. By default, this option
is off.

DESCRIPTION

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The all_drc_violated_nets command returns a collection of DRC-violated nets from the current design or from the specified input
collection. The tool can search the entire design hierarchy. It returns DRC-violated nets from the entire design, not just from the top
level.

This command returns the 3 most common types of DRC violations: max_capacitance, max_transition, and max_fanout. You can
specify each of the violations separately in this command. If you do not specify an option, a collection of all three types of DRC-violated
nets is returned.

The command returns a standard Tcl collection. You can perform all of the generic collection manipulating commands, such as
foreach_in_collection, sizeof_collection, and so on, on this collection handle.

Multicorner-Multimode Support
This command uses information from the current scenario only.

EXAMPLES
The following example shows the collection of all maximum capacity DRC-violated nets from the design:

prompt> all_drc_violated_nets -max_cap

{n1 n2 n3 abc/n14}

The following example shows the collection of all -max_fanout DRC-violated nets from an existing collection stored in $COLL:

prompt> all_drc_violated_nets -max_fanout $COLL

{n1 n3 abc/n14}

SEE ALSO
foreach_in_collection(2)
sizeof_collection(2)

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all_fanin
Reports pins, ports, or cells in the fanin of specified sinks.

SYNTAX
collection all_fanin
-to sink_list
[-startpoints_only]
[-exclude_bboxes]
[-break_on_bboxes]
[-only_cells]
[-flat]
[-levels count]
[-trace_arcs arc_type]

Data Types
sink_list list
count int

ARGUMENTS
-to sink_list

Reports a list of sink pins, ports, or nets in the design and a timing fanin of each sink in the sink_list. If you specify a net, the effect
is the same as listing all driver pins on the net.

-startpoints_only

Returns only the timing startpoints.

-exclude_bboxes

Excludes black boxes from the final result.

-break_on_bboxes

Stops timing fanin traversal on black boxes.

-only_cells

Results in a set of all cells in the timing fanin of the sink_list.

-flat

Specifies to function in the flat mode of operation. The two major modes in which all_fanin functions are hierarchical (the default)
and flat. When in hierarchical mode, only objects from the same hierarchy level as the current sink are returned. Thus, pins within a
level of hierarchy lower than that of the sink are used for traversal but are not reported.

-levels count

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Stops traversal when reaching the perimeter of the search of count hops, where counting is performed over the layers of cells that
are equidistant from the sink.

-trace_arcs arc_type

Specifies the type of combinational arcs to trace during the traversal. Allowed values are timing, which permits the tracing only of
valid timing arcs (arcs that are neither disabled nor invalid due to case analysis), and all, which permits tracing of all combinational
arcs regardless of either case analysis or arc disabling. The default in Design Compiler (both in topographical mode and non-
topographical mode) is timing. The default in DC Explorer is all. You can change the default by setting the
fanin_fanout_trace_arcs variable to the desired value.

DESCRIPTION
The all_fanin command reports the timing fanin of specified sink pins, ports, or nets in the design. A pin is considered to be in the
timing fanin of a sink if there is a timing path through combinational logic from the pin to that sink. The fanin report stops at the clock
pins of registers (sequential cells).

Multicorner-Multimode Support
Depending on the options used, this command either uses the current scenario or has no dependency on scenario-specific
information.

EXAMPLES
The following examples show the timing fanin of a port in the design. The design comprises three inverters in a chain named iv1, iv2,
and iv3. The iv1 and iv2 inverters are hierarchically combined in a larger cell named ii2.

prompt> all_fanin -to tout

{ii2/hin iv3/in iv3/out tin ii2/hout tout}

prompt> all_fanin -to tout -flat

{ii2/iv1/U1/a ii2/iv2/U1/z tin iv3/U1/a ii2/iv1/U1/z
ii2/iv2/U1/a iv3/U1/z tout}

SEE ALSO
all_fanout(2)
report_transitive_fanin(2)

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all_fanout
Returns a set of pins, ports, or cells in the fanout of the specified sources.

SYNTAX
collection all_fanout
-clock_tree
-from source_list
[-endpoints_only]
[-exclude_bboxes]
[-break_on_bboxes]
[-only_cells]
[-flat]
[-levels count]
[-trace_arcs arc_type]

Data Types
source_list list
count int

ARGUMENTS
-clock_tree

Uses all clock source pins and/or ports in the design as the list of sources. Clock sources are specified by using the create_clock
command. If there are no clocks, or if the clocks have no sources, the report is empty. Use the report_clock command to list the
sources for all clocks in the design. The -clock_tree option generates a report that displays the clock trees or networks in the
design. The -clock_tree and -from options are mutually exclusive.

-from source_list

Specifies a list of source pins, ports, or nets in the design. The timing fanout of each source in the source_list is reported. If a net is
specified, the effect is the same as listing all load pins on the net. The -clock_tree and -from options are mutually exclusive.

-endpoints_only

Returns only timing endpoints as a result.

-exclude_bboxes

Excludes black boxes from the final result.

-break_on_bboxes

Stops timing fanout traversal on black boxes.

-only_cells

Results in a set of all cells in the timing fanout of the source_list, rather than a set of pins or ports.

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-flat

Specifies to function in the flat mode of operation. The two major modes in which all_fanout functions are hierarchical (the default)
and flat. When in hierarchical mode, only objects from the same hierarchy level as the current source are returned. Thus, pins
within a level of hierarchy lower than that of the source are used for traversal but are not reported.

-levels count

Stops traversal when reaching the perimeter of the search of count hops, where counting is performed over the layers of cells that
are equidistant from the source.

-trace_arcs arc_type

Specifies the type of combinational arcs to trace during the traversal. Allowed values are timing, which permits the tracing only of
valid timing arcs (arcs that are neither disabled nor invalid due to case analysis), and all, which permits tracing of all combinational
arcs regardless of either case analysis or arc disabling. The default in IC Compiler and Design Compiler (both in topographical
mode and non-topographical mode) is timing. The default in DC Explorer is all. The default can be changed by setting the
fanin_fanout_trace_arcs variable to the desired value.

DESCRIPTION
The all_fanout command reports the timing fanout of specified source pins, ports, or nets in the design. A pin is considered to be in
the timing fanout of a sink if there is a timing path through combinational logic from that source to the pin. The fanout report stops at
the inputs to registers (sequential cells). The source pins or ports are specified by using the -clock_tree or -from source_list option.

Multicorner-Multimode Support
Depending on the options used, this command either uses the current scenario or has no dependency on scenario-specific
information.

EXAMPLES
The following example shows the timing fanout of a port in the design. The design comprises the following three inverters in a chain
named iv1, iv2, and iv3. The iv1 and iv2 inverters are hierarchically combined in a larger cell named ii2.

prompt> all_fanout -from tin

{iv3/out tout iv3/in ii2/hin ii2/hout tin}

prompt> all_fanout -from tin -flat

{tout ii2/iv2/U1/z ii2/iv1/U1/a iv3/U1/z iv3/U1/a
ii2/iv2/U1/a ii2/iv1/U1/z tin}

prompt> all_fanout -from tin -levels 1 -only_cells

{iv3 ii2}

SEE ALSO
all_fanin(2)
create_clock(2)
report_clock(2)
report_transitive_fanout(2)

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all_high_fanout
Returns a collection of high-fanout nets from the current design or from the specified input collection.

SYNTAX
collection all_high_fanout
-nets
[-threshold value]
[input_coll]
[-through_buf_inv]

Data Types
value float
input_coll collection

ARGUMENTS
-nets

Returns the collection of high-fanout nets.

-threshold value

Specifies a threshold value used to determine if a net is a high-fanout net. The value is a user-specified value. By default, the
high_fanout_net_threshold variable value is used to determine if a net is a high-fanout net.

input_coll

Searches the specified input collection for high-fanout nets. Objects are to be searched only from the contents of the specified input
collection, rather than from the design.

-through_buf_inv

Indicates to treat a buffer tree as transparent. The leaf loads of the buffer tree are treated as the fanouts of the net.

DESCRIPTION
The all_high_fanout command returns a collection of all high-fanout nets in the design. The tool searches the entire design hierarchy.
It returns nets from the entire design, not just from the top level.

To determine if a net is a high-fanout net, use the high_fanout_net_threshold variable value as the threshold value. The command
returns all nets with a fanout count higher than this threshold as high-fanout nets. You can also specify the threshold by using the -
threshold option.

If you specify a value for input_coll, the command searches for high-fanout objects only from the specified collection, rather than from

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the entire design.

A standard Tcl collection is returned. All of the generic collection manipulating commands, such as foreach_in_collection,
sizeof_collection, and so on, can be performed on this collection handle.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example shows the collection of all high-fanout nets from the design:

prompt> all_high_fanout -nets

{ii2/hin iv3/in iv3/out tin ii2/hout tout}

The following example shows the collection of all high-fanout nets from an existing collection stored in $COLL:

prompt> all_high_fanout -nets $COLL

{ii2/hin iv3/in iv3/out tin ii2/hout tout}

The following example shows the collection of all high-fanout nets from the design having a fanout count of more than 100:

prompt> all_high_fanout -nets -threshold 100

{ii2/hin iv3/in iv3/out tin ii2/hout tout}

SEE ALSO
all_fanin(2)
all_fanout(2)
foreach_in_collection(2)
report_net_fanout(2)
sizeof_collection(2)

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all_ideal_nets
Returns a collection of ideal nets from the current design or from the specified input collection.

SYNTAX
collection all_ideal_nets
[input_coll]

Data Types
input_coll collection

ARGUMENTS
input_coll

Specifies the input collection to search for ideal nets.

If you do not specify this argument, the command searches for ideal nets in the current design.

DESCRIPTION
The all_ideal_nets command returns a collection of ideal nets.

If you specify a value for input_coll, the command searches for ideal nets only in the specified collection.

If you do not specify a collection, the command searches for ideal nets in the current design. The tool searches the entire design
hierarchy. The command returns ideal nets from the entire design, not just from the top level.

A standard Tcl collection is returned. All of the generic collection manipulating commands, such as foreach_in_collection,
sizeof_collection, and so on, can be performed on this collection handle.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example returns a collection of all ideal nets from the design:

prompt> all_ideal_nets

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{ii2/hin iv3/in iv3/out tin ii2/hout tout}

The following example returns a collection of all ideal nets from an existing collection stored in $COLL:

prompt> all_ideal_nets $COLL

{ii2/hin iv3/in iv3/out tin ii2/hout tout}

SEE ALSO
all_fanout(2)
foreach_in_collection(2)
sizeof_collection(2)

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all_inputs
Returns a collection of input or inout ports in the current design.

SYNTAX
collection all_inputs
[-clock clock_name]
[-edge_triggered | -level_sensitive]

Data Types
clock_name string

ARGUMENTS
-clock clock_name

Limits the search to ports that have input delay relative to clock_name.

-edge_triggered

Limits the search to ports that have edge-triggered input delay as specified by the set_input_delay command with the -clock
option.

-level_sensitive

Limits the search to ports that have level-sensitive input delay as specified by the set_input_delay command with the -
level_sensitive option.

DESCRIPTION
The all_inputs command returns a collection of all input or inout ports in the current design, unless one of the options limits the
search. The all_inputs command is usually used with a command that places attributes on input ports. To get detailed information on
ports in the current design, use the report_port command.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES

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The following example lists all input ports in the current design:

prompt> all_inputs
{A1 A2 BIDIR1}

The following example sets the drive value of all the input ports on the current design to 10:

prompt> set_drive 10.0 [all_inputs]

The following example marks with a multicycle value of 0 all paths from inputs having level-sensitive input delay relative to PHI1 to
level-sensitive registers clocked by PHI1:

prompt> set_multicycle_path 0 \
-from [all_inputs -clock PHI1 -level_sensitive] \
-to [all_registers -data_pins -clock PHI1]

SEE ALSO
all_outputs(2)
current_design(2)
report_port(2)
set_drive(2)
set_input_delay(2)
set_multicycle_path(2)

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all_isolation_cells
Returns a collection of isolation cells available in the design.

SYNTAX
collection all_isolation_cells

ARGUMENTS
The all_isolation_cells command has no arguments.

DESCRIPTION
The all_isolation_cells command returns a collection of the existing isolation cells in the design. The enabled level shifters also work
as isolation cells, but that type of cell is not returned by this command.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

SEE ALSO
all_level_shifters(2)
check_mv_design(2)

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all_level_shifters
Returns a collection of level-shifter cells available in the design.

SYNTAX
collection all_level_shifters
[-type els | simple]

ARGUMENTS
-type els | simple

Specifies the type of level-shifter cells to include in the collection. If you specify -type els, the command returns only the enabled
level-shifter cells. If you specify -type simple, the command returns only regular level-shifter cells. If you do not specify this option,
the command returns all level-shifter cells.

DESCRIPTION
The all_level_shifters command returns a collection of existing level-shifter cells in the design. You can restrict the types oflevel-
shifter cells returned in the collection by using the -type option.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

SEE ALSO

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all_macro_cells
Returns a collection of all macro cells in the design or from a list of objects in the input collection.

SYNTAX
collection all_macro_cells
[input_coll]

Data Types
input_coll collection

ARGUMENTS
input_coll

Specifies the input collection to search and return the collection of macro cells. Objects are to be searched only from the content of
the specified input collection rather than from the design.

DESCRIPTION
This command can return the collection of all macro cells from the design. The tool searches the entire design hierarchy. It returns
cells from the entire design, not just from the top level. This command uses the same definition as used in the legalizing process to
determine if a cell is a macro cell.

If you specify a value for input_coll, the command searches for macro cells only from the specified collection, rather than from the
entire design.

A standard Tcl collection is returned. All of the generic collection manipulating commands, such as foreach_in_collection,
sizeof_collection, and so on, can be performed on this collection.

A library cell can be set as macro cell by using set_cell_type command. If user requires any cell to be set as macro cell, cell_type
needs to be made BLOCK, COVER or RING. These cell_type attributes are the lef attributes and coming from LEF on all the existing
macro cells. To remove these macro cell attributes from any macro library cell, cell_type can be set as PAD or CORE type.

In case of non-topographical mode, the all macro cells count will be same as the "Macro Count" results of the report_qor.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

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EXAMPLES
The following example shows the collection of all macro cells from the design.

prompt> all_macro_cells
{macro1 top/macro2 top/macro4 macro10}

The following example shows the collection of all macro_cells from an existing collection stored in $COLL.

prompt> all_macro_cells $COLL

{macro1 macro2}

SEE ALSO
foreach_in_collection(2)
sizeof_collection(2)

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all_outputs
Returns a collection of output or inout ports in the current design.

SYNTAX
collection all_outputs
[-clock clock_name]
[-edge_triggered | -level_sensitive]

Data Types
clock_name string

ARGUMENTS
-clock clock_name

Limits the search to ports that have output delay relative to clock_name.

-edge_triggered

Limits the search to ports that have edge-triggered output delay as specified by the set_output_delay command with the -clock
option.

-level_sensitive

Limits the search to ports that have level-sensitive output delay as specified by the set_output_delay command with the -
level_sensitive option.

DESCRIPTION
The all_outputs command returns a collection of all output or inout ports in the current design, unless one of the options limits the
search. This command is usually used with a command that places attributes on output ports. To get detailed information on ports in
the current design, use the report_port command.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES

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The following example lists all output ports:

prompt> all_outputs
{OUT1 OUT2 BIDIR1}

The following example sets a capacitive load of 3.5 on each output port:

prompt> set_load 3.5 [all_outputs]

The following example sets paths leading to output ports clocked by TSTCLK to be false.

prompt> set_false_path -to [all_outputs -clock TSTCLK]

SEE ALSO
all_inputs(2)
current_design(2)
report_port(2)
set_false_path(2)
set_load(2)
set_output_delay(2)

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all_physical_only_cells
Returns a collection of all the physical-only cells from a design or from a list of objects in an input collection.

SYNTAX
collection all_physical_only_cells
[-lib_cells lib_list | -cell_name list]
[-coordinates {llx lly urx ury}]
[input_coll_handle]

Data Types
lib_list list
list list
llx float
lly float
urx float
ury float
input_coll_handle collection

ARGUMENTS
-lib_cells lib_list

Specifies a list of library cells. The tool searches for physical-only cells in the specified library cell list. The default behavior returns
all physical-only cells from the entire design.

-cell_name list

Specifies the base instance name of the filler cells to be searched for in the design. The default behavior returns all physical-only
cells from the entire design.

-coordinates {llx lly urx ury}

Specifies the coordinates of the area to search for physical-only cells. Returns a collection of the physical-only cells contained within
the specified area. The default behavior returns all physical-only cells from the entire design.

input_coll_handle

Specifies the name of a collection from which to search for physical-only cells. Returns a collection of physical-only cells that are
contained within the specified input collection. The default behavior returns all physical-only cells from the entire design.

DESCRIPTION
This command returns a collection of all the physical-only cells in the design. The tool searches the entire design hierarchy. It returns
physical-only cells from the entire design, not just from the top level.

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You can use wild cards, such as an asterisk (*) or question mark (?), when specifying cell instance names.

A standard Tcl collection is returned. All of the collection-manipulating commands, such as the foreach_in_collection and
sizeof_collection commands, can be performed on the collection of physical-only cells.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example collects all the physical-only cells from the design.

prompt> all_physical_only_cells
{fill1 fill2 fill3 abc/fill4}

The following example collects all the physical-only cells from the design that have a library cell of type OKOAFILLER.

prompt> all_physical_only_cells -lib_cell OKOAFILLER

{hin in out tin hout tout}

The following example collects all the physical-only cells from an existing collection stored in $COLL.

prompt> all_physical_only_cells $COLL

{ii2/hin iv3/in iv3/out tin ii2/hout tout}

The following example collects all the physical-only cells from the design that have an instance name starting with fill.

prompt> all_physical_only_cells -cell_name fill*

{fill1 fill2 fill3}

SEE ALSO
foreach_in_collection(2)
sizeof_collection(2)

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all_registers
Returns a collection of sequential cells or pins in the current design.

SYNTAX
collection all_registers
[-no_hierarchy]
[-clock clock_name]
[-rise_clock rise_clock_name]
[-fall_clock fall_clock_name]
[-cells]
[-data_pins]
[-clock_pins]
[-slave_clock_pins]
[-output_pins]
[-level_sensitive | -edge_triggered]
[-master_slave]
[-include_icg]
[-include_operator_register]

Data Types
clock_name string
rise_clock_name string
fall_clock_name string

ARGUMENTS
-no_hierarchy

Limits the search to only the current level of hierarchy. Subdesigns are not searched.

By default, the entire hierarchy is searched.

-clock clock_name

Considers only sequential cells clocked by the specified clock.

By default, all sequential cells in the current design are considered.

-rise_clock rise_clock_name

Considers only sequential cells triggered by the rising edge of the specified clock.

By default, all sequential cells in the current design are considered.

-fall_clock fall_clock_name

Considers only sequential cells triggered by the falling edge of the specified clock.

By default, all sequential cells in the current design are considered.

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-cells

Returns a collection of sequential cells that meet the search criteria.

If you do not specify any of the object type options, the command returns a collection of sequential cells.

-data_pins

Returns a collection of data pins of the sequential cells that meet the search criteria.

-clock_pins

Returns a collection of clock pins of the sequential cells that meet the search criteria.

-slave_clock_pins

Returns a collection of slave clock pins of master-slave registers that meet the search criteria. Slave clock pins are specified as
clocked_on_also in the library.

-output_pins

Returns a collection of output pins of the sequential cells that meet the search criteria.

-level_sensitive

Limits the search to level-sensitive cells.

-edge_triggered

Limits the search to edge-triggered cells.

-master_slave

Limits search to master_slave cells.

-include_icg

Returns a collection containing integrated clock-gating cells.

-include_operator_register

Performs synthetic netlisting even if no valid clock is specified.

DESCRIPTION
The all_registers command returns a collection of sequential cells or pins in the current design, filtered as specified by the options. By
default, the command returns a collection of all sequential cells in the design. If you specify clock_name, it considers only the
sequential cells in the transitive fanout of the sources of the clock.

You can use one or more of the -cells, -data_pins, -clock_pins, -slave_clock_pins, and -output_pins options to return a collection
containing the respective types of objects. For example, if you use -data_pins, the command returns a collection containing the only
the data pins of the sequential cells that meet the search criteria. If you use both -cells and -data_pins, the command returns a
collection containing both the sequential cells and their data pins.

When the variable all_registers_include_icg is set to TRUE, the command returns a collection containing integrated clock-gating
cells.

Multicorner-Multimode Support
This command uses information from the current scenario only.

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EXAMPLES
The following example sets max_delay targets for timing paths leading to data pins of all registers clocked by PHI2:

prompt> set_max_delay 10.0 -to [all_registers -clock PHI2 -data_pins]

The following example returns a list of data pins for all master-slave registers clocked by clockB:

prompt> all_registers -master_slave -data_pins -clock clockB

The following example returns a list of all level-sensitive cells and their clock (enable) pins:

prompt> all_registers -level_sensitive -cells -clock_pins

The following example shows how to push into an instance named U1 and find level-sensitive cells without searching subdesigns of
that instance:

prompt> current_instance U1

prompt> all_registers -no_hierarchy

SEE ALSO
create_clock(2)
current_design(2)
current_instance(2)
remove_clock(2)
set_max_delay(2)
all_registers_include_icg(3)

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all_rp_groups
Returns a collection of specified relative placement groups and all groups in their hierarchy.

SYNTAX
collection all_rp_groups
[rp_groups]

Data Types
rp_groups list or collection

ARGUMENTS
rp_groups

Specifies the relative placement groups for which to search.

If you do not specify this argument, the command returns a collection that contains all relative placement groups currently loaded in
memory.

DESCRIPTION
The all_rp_groups command returns a collection of the specified groups and all subgroups in their hierarchy.

If you do not specify the rp_groups argument, the command returns all relative placement groups currently loaded in memory.

If no relative placement groups are found, the command returns an empty string.

This command is supported only for designs that do not contain multiply-instantiated designs.

Relative placement usage is available with Design Compiler Ultra.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example uses the all_rp_groups command:

prompt> get_rp_groups

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{mul::grp_mul ripple::grp_ripple example3::top_group}

prompt> all_rp_groups
{mul::grp_mul ripple::grp_ripple example3::top_group}

prompt> all_rp_groups ripple::grp_ripple

{ripple::grp_ripple mul::grp_mul}

prompt> remove_rp_groups -all -quiet

1

prompt> all_rp_groups

SEE ALSO
add_to_rp_group(2)
all_rp_hierarchicals(2)
all_rp_inclusions(2)
all_rp_instantiations(2)
all_rp_references(2)
create_rp_group(2)
remove_rp_groups(2)

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all_rp_hierarchicals
Returns a collection of hierarchical relative placement groups that contain the specified groups in their hierarchy. The specified groups
can be either included or instantiated in their parent group.

SYNTAX
collection all_rp_hierarchicals
[rp_groups]

Data Types
rp_groups list or collection

ARGUMENTS
rp_groups

Specifies the relative placement groups whose ancestor groups are to be in the collection returned by this command. The specified
groups can be either included or instantiated in their parent group.

If you do not specify this argument, this command returns a collection that contains all hierarchical relative placement groups
currently loaded in memory.

DESCRIPTION
The all_rp_hierarchicals command returns a collection of hierarchical groups that are ancestors of the relative placement groups
specified in the rp_groups argument.

If you do not specify the rp_groups argument, the command returns a collection that contains all hierarchical relative placement groups
currently loaded in memory.

If no relative placement groups are found, the command returns an empty string.

This command is supported only for designs that do not contain multiply-instantiated designs.

Relative placement usage is available with Design Compiler Ultra.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

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EXAMPLES
The following example uses the all_rp_hierarchicals command:

prompt> get_rp_groups
{b::top a0::a0_group b::u_top/a1_group
b::u_top/a1_group_include b::u_nxt/a1_group
b::a1_group_include a1::a1_group}

prompt> all_rp_hierarchicals
{b::a1_group_include b::u_nxt/a1_group
b::u_top/a1_group_include b::u_top/a1_group b::top}

prompt> all_rp_hierarchicals b::u_top/a1_group_include

{b::u_top/a1_group}

prompt> remove_rp_groups -all -quiet

1

prompt> all_rp_hierarchicals

SEE ALSO
add_to_rp_group(2)
all_rp_groups(2)
all_rp_inclusions(2)
all_rp_instantiations(2)
all_rp_references(2)
create_rp_group(2)
remove_rp_groups(2)

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all_rp_inclusions
Returns a collection that contains the hierarchical relative placement groups that include the specified groups.

SYNTAX
collection all_rp_inclusions
[rp_groups]

Data Types
rp_groups list or collection

ARGUMENTS
rp_groups

Specifies the included relative placement groups whose parent groups are to be included in the collection returned by this
command.

If you do not specify this argument, this command returns a collection that contains all hierarchical relative placement groups in the
design that contain included groups.

DESCRIPTION
The all_rp_inclusions command returns a collection that contains the hierarchical groups that include the relative placement groups
specified in the rp_groups argument.

If you do not specify the rp_groups argument, the command returns a collection that contains all hierarchical relative placement
groups currently in memory that include other relative placement groups.

If no relative placement groups are found, the command returns an empty string.

This command is supported only for designs that do not contain multiply-instantiated designs.

Relative placement usage is available with Design Compiler Ultra.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES

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The following example uses the all_rp_inclusions command:

prompt> get_rp_groups
{mul::grp_mul mul::big_grp ripple::grp_ripple
example3::g2 example3::top_group}

prompt> all_rp_inclusions
{mul::big_grp example3::g2}

prompt> all_rp_inclusions mul::grp_mul

{mul::big_grp}

prompt> remove_rp_groups -all -quiet

1

prompt> all_rp_inclusions

SEE ALSO
add_to_rp_group(2)
all_rp_groups(2)
all_rp_hierarchicals(2)
all_rp_instantiations(2)
all_rp_references(2)
create_rp_group(2)
remove_rp_groups(2)

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all_rp_instantiations
Returns a collection of hierarchical relative placement groups that instantiate the specified groups.

SYNTAX
collection all_rp_instantiations
[rp_groups]

Data Types
rp_groups list or collection

ARGUMENTS
rp_groups

Specifies the instantiated relative placement groups whose parent groups are to be included in the collection returned by this
command.

If you do not specify this argument, this command returns a collection that contains all hierarchical relative placement groups in the
design that contain instantiated groups.

DESCRIPTION
The all_rp_instantiations command returns a collection of hierarchical relative placement groups that instantiate the groups specified
in the rp_groups argument.

If you do not specify the rp_groups argument, the command returns a collection that contains all hierarchical relative placement groups
currently in memory that instantiate other relative placement groups.

If no relative placement groups are found, the command returns an empty string.

This command is supported only for designs that do not contain multiply-instantiated designs.

Relative placement usage is available with Design Compiler Ultra.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES

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The following example uses the all_rp_instantiations command:

prompt> get_rp_groups
{mul::grp_mul ripple::grp_ripple example3::top_group}

prompt> all_rp_instantiations
{ripple::grp_ripple example3::top_group}

prompt> all_rp_instantiations ripple::grp_ripple

{example3::top_group}

prompt> remove_rp_groups -all -quiet

1

prompt> all_rp_instantiations

SEE ALSO
add_to_rp_group(2)
all_rp_groups(2)
all_rp_hierarchicals(2)
all_rp_instantiations(2)
all_rp_references(2)
create_rp_group(2)
remove_rp_groups(2)

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all_rp_references
Returns a collection of relative placement groups that directly contain the specified cells, which are either leaf cells or hierarchical cells
that contain instantiated relative placement groups.

SYNTAX
collection all_rp_references
[cell_list]
[-design design_name]

Data Types
cell_list list
design_name string

ARGUMENTS
cell_list

Specifies the cells (either leaf cells or hierarchical cells that contain instantiated relative placement groups) whose parent groups
are to be included in the collection returned by this command.

If you do not specify this argument, the command returns a collection that contains all relative placement groups that directly
contain any leaf cells in the specified design.

-design design_name

Specifies the design in which to locate the specified cells.

If you do not specify this option, the tool looks for the cells in the current design.

DESCRIPTION
The all_rp_references command returns a collection of relative placement groups that directly contain the cells (either leaf cells or
hierarchical cells that contain instantiated relative placement groups) specified in the cell_list argument.

If you do not specify the cell_list argument, the command returns a collection that contains all relative placement groups that directly
contain any leaf cells in the specified design.

A group directly contains a leaf cell if the cell was added to the group by using the -leaf option of the add_to_rp_group command.

A group directly contains a hierarchical cell if the cell was used to hierarchically instantiate another group by using the -instance option
of the add_to_rp_group command.

This command is supported only for designs that do not contain multiply-instantiated designs.

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Relative placement usage is available with Design Compiler Ultra.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example uses the all_rp_references command:

prompt> get_rp_groups
{mul::grp_mul ripple::grp_ripple example3::ripple
example3::top_group}

prompt> all_rp_references
{mul::grp_mul ripple::grp_ripple example3::ripple}

prompt> all_rp_references U1 -design mul

{mul::grp_mul}

prompt> remove_rp_groups -all -quiet

1

prompt> all_rp_references

SEE ALSO
add_to_rp_group(2)
all_rp_groups(2)
all_rp_inclusions(2)
all_rp_instantiations(2)
create_rp_group(2)
remove_rp_groups(2)

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all_scenarios
Lists all defined scenarios available in memory.

SYNTAX
string all_scenarios

ARGUMENTS
The all_scenarios command has no arguments.

DESCRIPTION
The all_scenarios command displays the scenarios currently defined in memory. This list includes both active and inactive scenarios.

Creation and usage of scenarios is available with Design Compiler Graphical.

Multicorner-Multimode Support
This command uses information from both active and inactive scenarios.

EXAMPLES
The following example uses all_scenarios to list the available scenarios:

prompt> create_scenario MODE1

prompt> create_scenario MODE2

prompt> all_scenarios
MODE1 MODE2

SEE ALSO
all_active_scenarios(2)
create_scenario(2)

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current_scenario(2)
remove_scenario(2)
set_active_scenarios(2)

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all_self_gates
Returns a collection of self-gating cells or pins in the current design. This command is supported only in topographical mode.

SYNTAX
collection all_self_gates
[-no_hierarchy]
[-clock clock_name]
[-cells]
[-enable_pins]
[-clock_pins]
[-output_pins]
[-test_pins]

Data Types
clock_name string

ARGUMENTS
-no_hierarchy

Limits the search to only the current level of hierarchy. Subdesigns are not searched. By default, this option is off.

-clock clock_name

Considers only self-gating cells for registers originally clocked by clock_name in the search. The clock_name can be either a string
or collection of one object. By default, this option is off.

-cells

Returns cells. This is the default.

-enable_pins

Returns enable pins instead of cells. By default, this option is off.

-clock_pins

Returns clock-input pins instead of cells. By default, this option is off.

-output_pins

Returns gated-clock output pins instead of cells. By default, this option is off.

-test_pins

Returns test_mode or scan_enable input pins instead of cells. By default, this option is off.

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DESCRIPTION
This command returns a collection of self-gating cells or pins in the current design, filtered as specified by the options. By default, the
command lists self-gating cells in the design. If you specify clock_name, it considers self-gating cells in the transitive fanout of the
specified clock in the search. Normally, it considers all self-gating cells in the search. The -cells option, which is the default, can be
combined with one or more of the pins options.

Traditional clock-gating cells inserted by the Power Compiler are excluded from the search. Use the all_clock_gates command to get
information about them.

EXAMPLES
The following example returns all self-gating cells for registers originally clocked by CLK:

prompt> all_self_gates -clock CLK

The following example returns a list of test pins for all self-gating cells for registers originally clocked by CLK:

prompt> all_self_gates -test_pins -clock CLK

SEE ALSO
compile_ultra(2)
report_self_gating(2)
all_clock_gates(2)

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all_test_modes
Displays all of the test modes that are defined for the current design.

SYNTAX
list all_test_modes

ARGUMENTS
The all_test_modes command has no arguments.

DESCRIPTION
The all_test_modes returns a list of all the modes defined for the current design. The define_test_mode command is used to define
a test mode of operation for a design.

EXAMPLES
The following is an example of the test modes report:

set mode_list [all_test_modes]

foreach m $mode_list {
current_test_mode $m
dft_drc
}

SEE ALSO
list_test_modes(2)
current_design(2)
current_test_mode(2)
define_test_mode(2)
insert_dft(2)

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all_threestate
Returns a collection of three-state cells or nets.

SYNTAX
collection all_threestate
-nets
[input_coll]

Data Types
input_coll collection

ARGUMENTS
-nets

Specifies that the collection of three-state nets is to be returned.

input_coll

Searches the specified input collection and returns a collection of three-state nets. Objects are to be searched only from the content
of the specified input collection, rather than from the design.

DESCRIPTION
The all_threestate command returns a collection of all three-state nets from the design. The tool searches the entire design hierarchy.
It returns three-state nets from the entire design, not just from the top level.

If you specify a value for input_coll, the command searches for three-state nets only from the specified collection, rather than from the
entire design.

Only the nets that are driven by a pin that is tristate or bidirectional are returned as three-state nets.

If you do not specify the -nets option, the all_threestate command returns an error.

A standard Tcl collection is returned. All of the generic collection manipulating commands, such as foreach_in_collection,
sizeof_collection, and so on, can be performed on this collection handle.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

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EXAMPLES
The following example returns a collection of all three-state nets from the design:

prompt> all_threestate -nets

{ii2/hin iv3/in iv3/out tin ii2/hout tout}

SEE ALSO
all_fanout(2)
foreach_in_collection(2)
sizeof_collection(2)

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all_tieoff_cells
Returns a collection of all tie-off cells in the current design or in the input collection.

SYNTAX
collection all_tieoff_cells
[input_coll]

Data Types
input_coll collection

ARGUMENTS
input_coll

Searches the specified input collection and returns a collection of tie-off cells. Objects are to be searched only from the content of
the specified input collection, rather than from the design.

DESCRIPTION
The all_tieoff_cells command returns a collection of all tie-off cells from the current design. The tool searches the entire design
hierarchy. It returns tie-off cells from the entire design, not just from the top level.

Tie-off cells are the constant cells that the tool introduced in the design. To find the value of a tie-off cell, the tool examines the
corresponding lib_cell of each cell to determine if it is logic-0 or logic-1.

If you specify a value for input_coll, the command searches for tie-off cells or nets only from the specified collection, rather than from
the entire design.

This command returns a standard Tcl collection. All of the generic collection manipulating commands, such as foreach_in_collection,
sizeof_collection, and so on, can be performed on this collection.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example returns a collection of all tie-off cells from the design:

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prompt> all_tieoff_cells
{logic1 logic0}

The following example returns a collection of all tie-off cells from an existing collection stored in $COLL:

prompt> all_tieoff_cells $COLL

{logic1}

SEE ALSO
foreach_in_collection(2)
sizeof_collection(2)

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all_upf_repeater_cells
Returns a collection of repeater cells available in the design by virtue of the UPF repeater-supply port attribute.

SYNTAX
collection all_upf_repeater_cells

ARGUMENTS
None

DESCRIPTION
The all_upf_repeater_cells command returns a collection of the repeater cells in the design, that were inserted or matched at the
domain boundary pin to honor the specification of the repeater-supply UPF attribute on the port. Repeater cells are buffers and
inverters using supplies specified by the set_port_attributes command.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

SEE ALSO
set_port_attributes(2)

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analyze
Analyzes the specified HDL source files and stores the resulting templates into the specified library in a format ready to specialize and
elaborate to form linkable cells of a full design.

SYNTAX
status analyze
[-format verilog | sverilog | vhdl]
[-define define_list]
[-library library_name | -work library_name]
[-uses design_libs_list]
[-vcs vcs_opts]
[-create_update]
[-update]
[-recursive]
[-autoread]
[-rebuild]
[-output_script output_string]
[-exclude exclude_list]
[-verbose]
[-top top_design_name]
file_list

Data Types
define_list string
library_name string
design_libs_list string
vcs_opts string
output_string string
exclude_list list
top_design_name string
file_list list

ARGUMENTS
-format verilog | sverilog | vhdl

Specifies the format of the files to be analyzed. The supported formats are Verilog, SystemVerilog, and VHDL.

Specifies that the -autoread option should look for files in the specified language whose extensions match the extensions in the list
identified by the hdlin_autoread_verilog_extensions, hdlin_autoread_sverilog_extensions, or
hdlin_autoread_vhdl_extensions variable. The -autoread option supports Verilog, SystemVerilog, and VHDL formats. By default,
-autoread reads in all the files it finds that have Verilog, SystemVerilog, and VHDL extensions. You can use the -autoread option to
specify file names in the file_list that do not have one of the language-specific extensions.

-define define_list

Specifies a list of constant macros to be defined for the session of the analyze command. This is useful for the inclusion of Verilog
or SystemVerilog code enclosed by `ifdef/`endif constructs. For details, see the HDL Compiler for Verilog User Guide.

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-library library_name

Specifies library_name as the current work library (whose -path receives all analyzed output files). The library_name should be
previously established by the define_design_lib command. Design libraries (directories containing template intermediate files)
should not be confused with .db or .ddc linkage libraries (files containing design cells).

By default, the analyze command stores all output in the work design library. To store design elements in libraries other than work
library, use the -library option. A writable directory must exist at the path defined for the current work library.

-work library_name

An alias for -library. This option is not available with the -autoread option.

-uses design_libs_list

This option is not available with the -format vhdl or -autoread option.

SystemVerilog and Verilog designs might contain unresolved references to unelaborated design templates without indication of
where those template definitions are located.

The compiler and linker always search for these templates first in the home directory of the parent design. By default, they then
continue each template search by visiting every design library defined by the define_design_lib command. The -uses option
overrides this last step. It stores a design library search order (as a cell attribute named link_design_libraries) within each design
being analyzed. Later, elaboration or linking will follow this prescribed order rather than visiting every known library. An empty list
argument limits the search to just the home library of the parent design. You do not need to repeat the -library_name setting, and
you cannot override a search of the work directory.

-vcs vcs_opts

Specifies all VCS-specific command-line options. The options must be specified as a single string, such as enclosed within braces
({}) or double quotation marks (""). Options specified by the -vcs option follow the VCS command-line syntax:

[-sverilog | -verilog] Specifies the format of the files to be analyzed.

[-y directory_path] Specifies the directories that contain the library files to be searched for unresolved module instantiations in the
design.

[+libext+.extension1+...] Specifies the extension to consider during a file search in the -y library directories. The default is no
extension.

[-v library_file] Holds several module definitions to be used during the search for unresolved modules.

[-f command_file] Specifies a command file.

[+define+macro_name+...] Defines a macro.

[+incdir+dir1+...] Includes directories in the search list.

src_file1 Specifies the files that are to be analyzed.

This option is not available with the -autoread option.

-create_update

Facilitates the packaging of HDL files for distribution performed by developers of DesignWare parts. For details, see the
DesignWare Developer's Guide. This option is not available with the -autoread option.

-update

Facilitates the installation of DesignWare parts in DesignWare installation scripts. For details, see the DesignWare Developer's
Guide. This option is not available with the -autoread option.

-recursive

Specifies that the analyze -autoread command must recursively scan the directory trees below those specified in the file_list list.
By default, the -autoread option looks only in the specified directories.

This option can be used only with the -autoread option.

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-autoread

Specifies to use the -autoread mode for script-free analysis of whole HDL source directories or directory trees. All HDL source files
located in those directories are prescanned, grouped, and then ordered into distinct source code streams based on their mutual
inclusion and package-reference dependences. Some or all source streams are finally analyzed using the basic command.

By default, the -autoread option creates or replaces only a subset of analyzed result files; it works in an incremental-update mode
that resembles the Unix make command. If an HDL source file does not exist or is newer than the intermediate files it should
produce, only that file and the source streams that require it are reanalyzed.

For more information, see the description for the -rebuild option.

-rebuild

Replaces any result files regardless of their timestamp. It analyzes all the indicated HDL source streams as if the result library was
empty.

This option can be used only with the -autoread option.

-output_script output_string

Creates a Tcl script that is compatible with Design Compiler and Formality.

The file reading order for third-party tools and a DOT language file dependency graph are embedded in the script as comments.

This option is available only with the -autoread option.

-exclude exclude_list

Specifies a list of files and directories that are not to be analyzed. An analyze -autoread [...] file_list command checks each HDL
source path against all elements of the exclude_list; it ignores a file if it or any of its directory paths matches any excluded path.

This option can be used only with the -autoread option.

-verbose

Prints out more messages for the -autoread option.

This option can be used only with the -autoread option.

-top top_design_name

Identifies the top-level component of a hierarchical design specified within the -autoread HDL source directories.

The analyze -autoread -top design name command selects a subset of the indicated HDL source streams to analyze. Its goal is to
analyze into intermediate form precisely those source files required for a later elaboration and linking of design_name. Files in the
indicated directories that are not required to elaborate the design hierarchy descending from design_name are prescanned but the
design templates they would produce are not created or replaced.

If the -top option is not provided, all HDL source streams indicated by the file_list argument are analyzed.

This option can be used only with the -autoread option.

file_list

Specifies the files to be analyzed.

To analyze multiple files, list them by using curly braces, {}. Note: Source files in a list are effectively concatenated into a single
source stream in the listed order.

In -autoread mode only, the file_list argument can also specify directory names. All HDL source files located in those directories
are prescanned. For more information about prescanning, see the descriptions for the -autoread and -recursive options.

DESCRIPTION

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This command translates the specified HDL files and stores the intermediate format in the specified library.

The following paragraphs describe the support for the -autoread option:

The -autoread option reads in the files from file_list, determines the dependencies between them, and analyzes them in the right
order to prevent errors due to missed or misplaced files.

The dependencies are calculated only from the files or directories present in file_list. If file_list changes between consecutive calls with
the -autoread option, the dependency inference is performed over the latest set of files provided. Based on this, all required sources
must be present in file_list option or be available if the -recursive option is used on each call with the -autoread option.

If the top design name is provided by the -top option, only the source files required for elaborating that top design are analyzed. This
filtering is based on file dependencies previously inferred. If the -top option is not provided, all sources are ordered, grouped, and
analyzed per the dependency inferred between them.

To locate the source files, the command expands each item in the file_list list with the search_path variable. Then, it determines
whether the result is excluded by the -exclude option or the hdlin_autoread_exclude_extensions variable. If it is not excluded and a
file ends with one of the extensions in the hdlin_autoread_vhdl_extensions variable list, it is considered a VHDL source file. If the file
ends with one of the extensions in the hdlin_autoread_verilog_extensions variable list, it is considered a Verilog source file. If the
file ends with one of the extensions in the hdlin_autoread_sverilog_extensions variable list, it is considered a SystemVerilog source
file.

When expanding a directory, the command collects the files from the directory, and from its subdirectories and theirs recursively if the -
recursive option is set. The command then performs all extension checks on these files. If the -format option is set, only files with
Verilog, SystemVerilog, or VHDL extensions are collected based on the value of the option.

After the -autoread option collects all of the source files, it performs the following dependency checks:

Detects analyze dependencies: List RTL files in the right order for analyzing. For example, analyze the file that contains a VHDL
entity before analyzing files that defines architectures of that entity, or analyze the file that contains a SystemVerilog package
declaration before the files that import that package.

Detects Verilog and SystemVerilog compilation unit dependencies: Determine if a file needs to be analyzed in the same
compilation unit with other files. For example, if a file defines macros, SystemVerilog local parameter, and SystemVerilog
enumerated values, and the file is not explicitly included by the file that requires that definitions, the -autoread option groups
them in the same compilation unit in the correct order. This might not always be possible, such as when a macro is defined
several times in different files and the -autoread option cannot determine which of those alternatives is the right choice.

Detects link dependencies: Schedule the analyze stage for files required for elaboration of the design hierarchy. For example, if a
Verilog or SystemVerilog design that is instantiated in one source file is declared on a different source file provided in the file_list,
the second file also requires to be analyzed for a complete top-down design elaboration.

Detects include dependencies: If a Verilog or SystemVerilog file is included in another source and the file changes between two
consecutive calls of the -autoread option (in the same synthesis session), the analyze command includes this file and all files
that include them to update the design.

Infers the target library for VHDL files. However, if the -library option is specified, this step is skipped and VHDL files provided in
the file_list are analyzed into the specified design library.

After the dependency check, all the required HDL files specified by the file_list option (regarding its dependencies and the -top design
option if defined) are analyzed.

When the -autoread option is used again (with the same file_list setting) after a file is changed, only the updated source files are
analyzed.

The -autoread option executes the dependency analysis based only on the current file_list information. All HDL source files that might
have relevant dependency relationships should be passed together in one analyze -autoread command.

EXAMPLES
The following example analyzes the packages.vhd file and stores the results in the MY_LIB design library:

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prompt> analyze -work MY_LIB -format vhdl packages.vhd

The following example analyzes two SystemVerilog clients of two libraries:

prompt> define_design_lib BUSDEFN -path /remote/IP/metra/big_bus

prompt> define_design_lib NClib -path ../../NCD/libNC
prompt> analyze -format sverilog -uses { BUSDEFN NClib } { senderAlice.sv receiverBob.sv }

The following example assumes that the current directory is the source directory. It specifies the source file list early in the command
line and gives options, including the name of the top-level entity later.

prompt> analyze {.} -autoread -recursive -top E1

The next example specifies extensions for Verilog files that are different from the default ({.v}), sets the source list and the exclude list,
and calls the command with the name of the top-level module name, forcing it to only collect files with Verilog extensions:

prompt> set hdlin_autoread_verilog_extensions {.ve .VE}

prompt> set my_sources {mod1/src mod2/src}
prompt> set my_excludes {mod1/src/incl mod2/src/incl}
prompt> analyze $my_sources -exclude $my_excludes -autoread \
-format verilog

Note that excluding include directories explicitly is only necessary if include files have the same extensions as source files and not all
include files are included in the source.

SEE ALSO
define_design_lib(2)
elaborate(2)
link(2)
read_file(2)
report_design_lib(2)
hdlin_autoread_exclude_extensions(3)
hdlin_autoread_verilog_extensions(3)
hdlin_autoread_sverilog_extensions(3)
hdlin_autoread_vhdl_extensions(3)

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analyze_datapath
Provides a datapath analysis report that lists the resources and datapath blocks used in the current design.

SYNTAX
analyze_datapath
[-file file_name]

Data Types
file_name string

ARGUMENTS
-file file_name

Specifies the file name of a log file that contains the report_resources -hierarchy and report_area -designware reports from a
previously compiled design. This option enables you start the tool and use the analyze_datapath command to generate a datapath
analysis report for a design without having to read in and compile the design a second time.

DESCRIPTION
The analyze_datapath command provides a datapath analysis report that lists a summary of the resources and datapath blocks used
in the current design. The report includes information reported by the report_resources -hierarchy command and the report_area -
designware command.

The report displays the area of singleton DesignWare designs and extracted datapath designs. The report summarizes the number of
singleton DesignWare components, summarizes the number of datapath designs, and lists the designs output width ranges.

EXAMPLES
The following example displays resource information for the current design:

prompt> analyze_datapath

***************************************************
Estimate of Datapath Content

Extracted Datapath: area = 45.9%, parts = 125

Singleton Datapath: area = 22.4%, parts = 168

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Total Datapath: area = 68.3%, parts = 293

***************************************************

***************************************************
Estimate of Datapath Types

Singletons:
out width
component count min max ave
----------------------------------------
DW01_add 69 7 32 23.5
DW01_sub 38 9 16 11.5
DW01_inc 19 9 20 16.4
DW_cmp 6 12 16 14.8
DW_mult_uns 35 8 32 19.1
DW_mult_tc 1 21 21 21.0
----------------------------------------

Datapaths:
out width
operation count min max ave
----------------------------------------
+- 340 6 32 16.8
* 50 15 31 22.6
? 69 9 32 15.4
== != 5 12 12 12.0

***************************************************

In the following example, the resource_area_rpt.txt file contains the report_resources -hierarchy and report_area -designware
reports from a previously compiled design. The -file option is used to read the resource_area_rpt.txt file and generate a datapath
analysis report based on the data in the file. You do not need to read in and compile the design a second time.

prompt> analyze_datapath -file resource_area_rpt.txt

***************************************************
Estimate of Datapath Content

Extracted Datapath: area = 45.9%, parts = 125

Singleton Datapath: area = 22.4%, parts = 168

Total Datapath: area = 68.3%, parts = 293

***************************************************

***************************************************
Estimate of Datapath Types

Singletons:
out width
component count min max ave
----------------------------------------
DW01_add 69 7 32 23.5
DW01_sub 38 9 16 11.5
DW01_inc 19 9 20 16.4
DW_cmp 6 12 16 14.8
DW_mult_uns 35 8 32 19.1
DW_mult_tc 1 21 21 21.0
----------------------------------------

Datapaths:
out width
operation count min max ave
----------------------------------------

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+- 340 6 32 16.8
* 50 15 31 22.6
? 69 9 32 15.4
== != 5 12 12 12.0

***************************************************

SEE ALSO
report_resources(2)
report_area(2)

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analyze_datapath_extraction
Analyzes DesignWare datapath extraction.

SYNTAX
status analyze_datapath_extraction
[-no_autoungroup]
[-no_report]
[-filter_msg none | low | medium]
[-sort_msg]
[-max_msgs max_num_msgs]
[-html_file_name html_file]
[design_list]

ARGUMENTS
-no_autoungroup

Specifies that automatic ungrouping is disabled. All hierarchies are preserved unless otherwise specified. The -no_autoungroup
option in analyze_datapath_extraction behaves the same way as the -no_autoungroup option in compile_ultra. If you plan to
specify the -no_autoungroup option in compile_ultra, you should also specify the -no_autoungroup option in
analyze_datapath_extraction.

-no_report

Specifies not to report contained resources at the end of the analysis.

-filter_msg none | low | medium

Turns on message filtering. Messages with severity levels less than or equal to the specified level are filtered out.

-sort_msg

Sorts the leakage detection messages (HDL-120, HDL-132) in each design based on their potential impact from high to low.

-max_msgs max_num_msgs

Specifies the maximum number of leakage detection messages (HDL-120, HDL-132) to display in each design. The message
sorting -sort_msg option is turned on automatically.

-html_file_name html_file

Writes all outputs to the specified HTML file.

design_list

Specifies list of designs to run datapath extraction analysis.

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DESCRIPTION
This command analyzes the datapath extraction of the current design.

When a DesignWare operator is not extracted, it analyzes the reason why it is not extracted. If it is due to the RTL coding, the tool
issues a message about the RTL coding style that interferes with datapath extraction.

After the analysis, a report shows the contained resources in the design. This report helps to find the resources in the design source
code. Note that the datapath names in this report can differ from the datapath names in the report generated using the
report_resources command after compilation. However, the names of the contained resources will be the same.

For more information about RTL coding styles that help improve datapath extraction, see to the coding guidelines documented in
"Coding Guidelines for Datapath Synthesis" on SolvNet (https://solvnet.synopsys.com/retrieve/015771.html).

Here are examples of possible warning messages issued by the analyze_datapath_extraction command:

"HDL-120": Issued when a DesignWare operator is breaking the datapath due to leakage on its fanout or the fanout of its driver. This
DesignWare operator can be the boundary node of an extracted datapath block.

Datapath leakage occurs when an internal operand is not wide enough to store the result of an operation but the full result is required
later. Operands with leakage must be binary and must be at the boundary of a datapath block. Therefore, operands with leakage will
break a potentially larger datapath block into smaller datapath blocks, resulting in suboptimal QoR.

Example 1: module test( a, b, c, d, e, f, o1, o2, o3 ); input [10:0] a, b; input [5:0] c, d, e, f; output [8:0] o1; output [9:0] o2; output [7:0]
o3; assign o1 = a + b + c; (add_9, add_9_2) assign o2 = f + o1; (add_10) assign o3 = e + o1; (add_11) endmodule

In this design, the input 'o1' of 'add_10' is truncated. Therefore, the following message is issued:

Information: Operator associated with resources 'add_10' in design 'test' breaks the datapath extraction because there is leakage due
to truncation on the fanout of its driver 'add_9 add_9_2'. (HDL-120)

On the other hand, the width of 'o3' is smaller than the width of 'o1.'Therefore, there is no leakage on the input of 'add_11".

Example 2: module leakage_a (a, b, c, z); input signed [7:0] a, b; input [7:0] c; output [9:0] z; wire signed [8:0] t; assign t = a + b;
//add_6 // leakage: signed result used in wider unsigned expression assign z = t + c; endmodule

There is leakage due to sign mismatch at the fanin(signed) and fanout(unsigned) of add_6:

Information: Operator associated with resources 'add_6' in design 'leakage_a' breaks the datapath extraction because there is leakage
due to driver/load sign mismatch. (HDL-120)

Example 3: module leakage_b (a, b, c, z); input [7:0] a, b; input signed [7:0] c; output signed [10:0] z; wire signed [8:0] t;

assign t = a + b; // add_7 // leakage: unsigned result used in wider signed expression assign z = t + c; endmodule

There is leakage due to sign mismatch at the fanin(unsigned) and fanout(signed) of add_7:

Information: Operator associated with resources 'add_7' in design 'leakage_b' breaks the datapath extraction because there is leakage
due to driver/load sign mismatch. (HDL-120)

Subtraction can give negative results that cannot be represented with an unsigned operand of limited width. It is recommended to
declare the operands as signed. Note that constants used in signed operations need to be marked signed as well.

Example 4: It is recommended to change the following RTL code: input [13:0] a ; input [13:0] b ; wire [15:0] o = a - 14'd4 - b ;

to

input signed [13:0] a ; input signed [13:0] b ; wire signed [15:0] o = a - 14'sd4 - b;

The "HDL-120" message is associated with coding guideline 19. (https://solvnet.synopsys.com/retrieve/015771.html#leakage).

"HDL-121": There is a sequential cell that breaks the datapath extraction.

Example: module test (clk, en, a, b, c, z); input clk, en; input [7:0] a, b; input [15:0] c; output [15:0] z; reg [15:0] prod;

always @ (posedge clk) begin if (en) begin prod <= a * b; end end assign z = prod + c; endmodule

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There is a register between the multiplier and the adder. The following message will be issued:

Information: There is sequential cell in between operator associated with 'mult_11' and 'add_15' in design 'test'. (HDL-121)

The extracted datapath block cannot contain sequential cells (for example, registers). The register in between operators will break a
potential larger datapath block into smaller datapath blocks, resulting in suboptimal QoR.

The "HDL-121" message is associated with coding guideline 12. (https://solvnet.synopsys.com/retrieve/015771.html#pipelining).

"HDL-125": Design contains instantiated DW. If the instantiated DW is replaced with an inferred DW OP, it could be extracted.

Example: module test(a,b,c,z); parameter wl = 5; input [wl-1:0] a,b,c; output [2*wl-1:0] z;

wire [wl-1:0] sum; assign sum = (b+a); DW02_mult #(wl, wl)U_mult(sum, c, 1'b0, z); endmodule

The instantiated DW02_mult can be replaced by an inferred multiplier. The following message will be issued:

Information: Cell 'U_mult' in design 'test' can not be extracted because it instantiates 'DW02_mult', which could be inferred with
operator '*' instead. (HDL-125)

The instantiated DesignWare component cannot be extracted into datapath blocks. If the RTL design uses inferred the DesignWare
operation instead of instantiated DesignWare components, the inferred DesignWare operator might be extracted into a datapath block.

The "HDL-125" message is associated with coding guideline 11.

(https://solvnet.synopsys.com/retrieve/015771.html#component_instantiation).

EXAMPLES
The following example shows the analysis report about leakage that breaks the datapath extraction.

prompt > analyze_datapath_extraction

Information: Checking out the license 'DesignWare'. (SEC-104)
Running analyze_dp_extraction ...

Information: Operator associated with resources 'add_8 add_8_2' in design 'test' breaks the
datapath extraction because there is leakage due to truncation on its fanout. (HDL-120)

****************************************
Report : resources
Design : test
Version: G-2012.06-ALPHA4
Date : Fri Mar 2 14:50:01 2012
****************************************

Resource Report for this hierarchy in file

/remote/source/rtl/dpl.v
=============================================================================
| Cell | Module | Parameters | Contained Operations |
=============================================================================
| DP_OP_12J2_124_2007 | | |
| | DP_OP_12J2_124_2007 | | |
| DP_OP_13J2_125_9654 | | |
| | DP_OP_13J2_125_9654 | | |
=============================================================================

Datapath Report for DP_OP_12J2_124_2007

==============================================================================
| Cell | Contained Operations |
==============================================================================
| DP_OP_12J2_124_2007 | add_8 add_8_2 |
==============================================================================

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==============================================================================
| | | Data | | |
| Var | Type | Class | Width | Expression |
==============================================================================
| I1 | PI | Unsigned | 9 | |
| I2 | PI | Unsigned | 9 | |
| I3 | PI | Unsigned | 6 | |
| O1 | PO | Unsigned | 9 | I1 + I2 + I3 |
==============================================================================

Datapath Report for DP_OP_13J2_125_9654

==============================================================================
| Cell | Contained Operations |
==============================================================================
| DP_OP_13J2_125_9654 | add_9 add_9_2 add_9_3 add_9_4 |
==============================================================================

==============================================================================
| | | Data | | |
| Var | Type | Class | Width | Expression |
==============================================================================
| I1 | PI | Unsigned | 11 | |
| I2 | PI | Unsigned | 6 | |
| I3 | PI | Unsigned | 6 | |
| I4 | PI | Unsigned | 6 | |
| I5 | PI | Unsigned | 9 | |
| O1 | PO | Unsigned | 12 | I1 + I2 + I3 + I4 + I5 |
==============================================================================

No implementations to report

No multiplexors to report
1

SEE ALSO
report_resources(2)

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analyze_dw_power
Reports the DesignWare delay and power contribution.

SYNTAX
int analyze_dw_power
[-nosplit]
[-hierarchy]
[-sort slack | dyn_pwr | lkg_pwr]
[-sort_ascending]

ARGUMENTS
-nosplit

Prevents line splitting and facilitates writing tools to extract information from the report output. Most design information is listed in
fixed-width columns. If the information for a given field exceeds the column width, the next field begins on a new line, starting in the
correct column.

-hierarchy

Reports the DesignWare information in the hierarchy of the current design or the current instance. By default, resources used only
in the top level of the current design or the current instance are reported.

-sort slack | dyn_pwr | lkg_pwr

Sort the report by the sorting criteria, from largest to smallest.

-sort_ascending

Sort the report in ascending order. This option only works when the -sort option is also specified.

DESCRIPTION
This command lists the slack and power contribution of synthetic cells in the current design.

For the generated DesignWare netlist, the command reports the best case slack that the generator can achieve during optimization.
For the DesignWare netlist with static implementation, the slack reported is the worst case for the design. If the design is ungrouped,
the slack of the ungrouped design is reported. Otherwise, the slack of the design is reported.

For the static DesignWare netlist, only the negative slacks are reported.

This report also shows the power contribution of all the synthetic modules in the current design.

If a synthetic module is ungrouped before propagating the timing and power context, the command does not report the delay and
power contribution. For these cells, the path group column of the report is empty. The DW slack column is na. For these DesignWare
designs, because they are ungrouped after they are optimized for area or power, setting the power_effort to medium or high might

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not improve power.

The report does not include DesignWare with small bitwidth that are ungrouped. The power of such DesignWare cells are not
accounted for the total DesignWare power contribution. Therefore, the total number of DesignWare reported in this report might be
different from the total number of DesignWare reported by the report_area or the report_resources command.

The power contribution of each DesignWare cell is shown in dyn power % and lkg power % columns. If the power contribution of a
DesignWare cell is very small, this column might show a value of 0.00. The power of these DesignWare cells is included in the total
DesignWare power.

The power consumption of all synthetic cells are summarized in the power summary of this report. The slack information is not
reported for DesignWare netlists with static implementation. So, the number of cells listed in the dw_power_analysis table might not
match the number in the power summary report.

For hierarchical DesignWare netlists, only the slack and power contribution of the top-level design are reported. The subcomponents of
the DesignWare are not reported.

To enable reporting of the ungrouped DesignWare components, set the synlib_enable_analyze_dw_power variable to 1 before
compiling the design.

EXAMPLES
The following example generates the analyze_dw_power report:

prompt> analyze_dw_power

****************************************
Report : dw_power_analysis
Design : test
Version: E-2010.12-SP1
Date : Wed Dec 1 16:54:45 2010
****************************************

DesignWare Power Contribution report

==============================================================================
| | | | dyn | lkg | | |
| | Path | DW | power | power | | |
| Cell | group | slack | % |% | opt mode | Attr |
==============================================================================
| DP_OP_11_124_4242 | | | | | |
| | default | -0.16 | 100.00 | 100.00 | area,speed | u |
==============================================================================

Attribute:
u - ungrouped

Power of detected synthetic parts

---------------------------------
No DW parts to report!

Estimated power of ungrouped synthetic parts

-------------------------------------------
DW cell count: 1
Dynamic Power: 3.3256e-01 100.00%
Leakage Power: 1.8464e-03 100.00%
-------------------------------------------
Total synthetic cell dynamic power: 3.3256e-01 100.00% (estimated)
Total synthetic cell leakage power: 1.8464e-03 100.00% (estimated)

Note:
Power Units = 1mW

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The following example generates the analyze_dw_power report for the hierarchical DesignWare components:

prompt> analyze_dw_power -hier

****************************************
Report : dw_slack_power
Design : test
Version: E-2010.12-SP1
Date : Wed Dec 1 17:19:40 2010
****************************************

DesignWare Power Contribution report

==============================================================================
| | | | dyn | lkg | | |
| | Path | DW | power | power | | |
| Cell | group | slack | % |% | opt mode | Attr |
==============================================================================
| add_x_938_1 (DW01_add) | | | | | |
| | default | na | 0.32 | 1.34 | area |u |
| DP_OP_257J1_124_2676 | | | | | |
| | default | 3.95 | 5.73 | 5.80 | area,speed | u |
==============================================================================

Attribute:
u - ungrouped

Power of detected synthetic parts

---------------------------------
No DW parts to report!

Estimated power of ungrouped synthetic parts

-------------------------------------------
DW cell count: 2
Dynamic Power: 5.5592e+00 98.05%
Leakage Power: 1.0676e-03 97.14%
-------------------------------------------
Total synthetic cell dynamic power: 5.5592e+00 98.05% (estimated)
Total synthetic cell leakage power: 1.0676e-03 97.14% (estimated)

Note:
Power Units = 1mW
1

SEE ALSO
report_area(2)
report_resources(2)
synlib_enable_analyze_dw_power(3)

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analyze_minpwr_library
Displays function, drive strength, area and power characteristics of cells from a target library used in datapath generation.

SYNTAX
status analyze_minpwr_library
[-legend]
[library_list]

Data Types
library_list list

ARGUMENTS
-legend

Provides a more detailed description of cell types

library_list

Specifies a list of one or more target libraries to be analyzed. If a list is not specified, libraries from the target_library variable are
used.

DESCRIPTION
This command displays function, drive strength, area and power characteristics of cells of the library that are used in datapath
generation. It also checks for cells or combinations of cells that can improve power QoR during datapath generation.

EXAMPLES
The following examples use the demo class.db library. The analyze_minpwr_library command prints some general attributes of the
library.

Libraries Used:

class (File: ~/class.db)

Library doesn't specify units for: leakage_power

Library units: time=1ns voltage=1V capacitance=0.100000ff dynamic_power=100nW

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Note: library doesn't contain any cells fully characterized for power.

This description is followed by three tables.

The first table lists significant cells used in datapath generation.

===================================================================================
| For cells selected for datapath generation... |
===================================================================================
| | Largest | Best Small | Best Dynamic | Best Leakage |
| Cell Type | Drive | Area Drive | Power | Power |
===================================================================================
| Not | B4IP | IVI | B4IP | B4IP |
| And2 | AN2I | AN2I | AN2I | AN2P |
| Xor2 | EOI | EOI | EOI | EOP |
| Xor3 | EO3P | EO3P | EO3P | EO3P |
| Nand2 | ND2P | ND2I | ND2P | ND2P |
| Xnor2 | ENI | ENI | ENI | ENP |
| Xnor3 | EN3P | EN3P | EN3P | EN3P |
| AOI21 | AO6P | AO6 | AO6P | AO6P |
| Maj23 | *NA* | *NA* | *NA* | *NA* |
| Maj23N | AO5P | AO5 | AO5P | AO5P |
| AddAB | *NA* | *NA* | *NA* | *NA* |
| AddABC | *NA* | *NA* | *NA* | *NA* |
| AddABCD | *NA* | *NA* | *NA* | *NA* |
| AddNABC | *NA* | *NA* | *NA* | *NA* |
| Benc | *NA* | *NA* | *NA* | *NA* |
| Bmux | *NA* | *NA* | *NA* | *NA* |
| Mux2 | MUX21HP | MUX21H | MUX21HP | MUX21HP |
| Mux4 | *NA* | *NA* | *NA* | *NA* |
===================================================================================

*NA* - the library does not contain a cell that implements this function

The second table shows specific attributes of the cells listed in the first table.

==============================================================================
| | | | Dynamic | Leakage |
| Library Cell | Cell Area | Cell Drive | Power | Power |
==============================================================================
| AN2I | 2.00000 | 0.12539 | 2.50000 | *INV* |
| AO2 | 2.00000 | 0.73931 | 5.00000 | *INV* |
| AO2P | 4.00000 | 0.37418 | 10.00000 | *INV* |
| AO4 | 2.00000 | 0.73931 | 5.00000 | *INV* |
| AO4P | 4.00000 | 0.37418 | 10.00000 | *INV* |
| AO6 | 2.00000 | 0.73931 | 3.75000 | *INV* |
| AO6P | 3.00000 | 0.37418 | 7.50000 | *INV* |
| AO7 | 2.00000 | 0.73931 | 3.75000 | *INV* |
| AO7P | 3.00000 | 0.37418 | 7.50000 | *INV* |
==============================================================================

*INV* This power value isn't characterized in the library.

The third table lists characteristics for the lowest area and power versions of the library cells. The area, power, and drive-strength
characteristics are checked for potential problems. Informational warning messages are generated first, followed by the cell
characterization table.

The cell characterization table contains the following information for each cell type:

Smallest Cell : The smallest cell that is found in the library

Total # Drives : Number of different drive strengths for this cell
Min Area # Drives : Number of different drive strengths for the minimum area version of this cell
Estim Size : Estimated size of the cell based on the estimated grid size
Actual Size : Cell size from the library data

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Dynamic Power : Dynamic power from the library data

Min # Trans : Estimated minimum number of transistors required to implement the cell
Estim # Grids : Estimated number of grids required to implement the cell
Actual # Grids : Calculated number of grids for the cell based on the area of the smallest inverter in the library

When a potential problem in the cell is detected, an asterisk (*) is added to the value in the characterization table.

The following example flags the potential problems in some library cells.

Information: Xnor3 Cell too large (too many grids). (UISN-89)

Information: Maj23 Cell does not exist. (UISN-86)
Information: Maj23N Not enough total drives (should have at least 4). (UISN-87)
Information: Maj23N No low power cell (should have at least 2 drives for minimum footprint). (UISN-88)

===================================================================================================
Cell Characterization for Lowest Area / Power
Estimated grid size = 0.500000
===================================================================================================
| Cell | Smallest | Total | Min Area | Estim | Actual | Dynamic| Min | Estim | Acrual |
| Type | Cell | # Drives | # Drives | Size | Size | Power | # Trans | #Grids | #Grids |
===================================================================================================
| Not | IVI | 9 | 4 | 1.000 | 1.000 | 0.0000 | 2 | 2 | 2 |
| And2 | AN2I | 4 | 3 | 2.000 | 2.000 | 0.0000 | 6 | 4 | 4 |
| Xor2 | EOI | 4 | 2 | 3.000 | 3.000 | 0.0000 | 10 | 6 | 6 |
| Xor3 | EO3 | 4 | 2 | 5.500 | 7.000 | 0.0000 | 20 | 11 | 14* |
| Nand2 | ND2I | 4 | 2 | 1.500 | 1.000 | 0.0000 | 4 | 3 | 2 |
| Xnor2 | ENI | 4 | 2 | 3.000 | 3.000 | 0.0000 | 10 | 6 | 6 |
| Xnor3 | EN3 | 4 | 2 | 5.500 | 7.000 | 0.0000 | 20 | 11 | 14* |
| AOI21 | AO6 | 2* | 1* | 2.000 | 2.000 | 0.0000 | 6 | 4 | 4 |
| Maj23 | *NA* | *NA* | *NA* | *NA* | *NA* | *NA* | 0 | 0 | *NA* |
| Maj23N | AO5 | 2* | 1* | 3.000 | 3.000 | 0.0000 | 10 | 6 | 6 |
| AddAB | *NA* | *NA* | *NA* | *NA* | *NA* | *NA* | 0 | 0 | *NA* |
| AddABC | *NA* | *NA* | *NA* | *NA* | *NA* | *NA* | 0 | 0 | *NA* |
| Benc | *NA* | *NA* | *NA* | *NA* | *NA* | *NA* | 0 | 0 | *NA* |
| Bmux | *NA* | *NA* | *NA* | *NA* | *NA* | *NA* | 0 | 0 | *NA* |
| Mux2 | MUX21H | 2* | 1* | 3.500 | 4.000 | 0.0000 | 12 | 7 | 8* |
| Mux4 | *NA* | *NA* | *NA* | *NA* | *NA* | *NA* | 0 | 0 | *NA* |
===================================================================================================

SEE ALSO
target_library(3)

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analyze_mv_design
Analyzes multivoltage design connections.

SYNTAX
status analyze_mv_design
[-level_shifter | -always_on | -lib_cells]
[-from_pin from_pin_list]
[-to_pin to_pin_list]
[-net target_net]
[-isolation]
[-enable_level_shifter]
[-retention]
[-verbose]
[-voltage_type all | nominal]

Data Types
from_pin_list list
to_pin_list list
target_net list

ARGUMENTS
-level_shifter

Enables level-shifter analysis, which is based on load-to-driver pin arguments.

-always_on

Enables always-on analysis, which is based on the target net argument.

-lib_cells

Reports the unmapped isolation, enable level shifter and retention cells for the current design, which is based on -isolation, -
enable_level_shifter and -retention arguments.

-from_pin from_pin_list

Specifies the driver (leaf cell pin or top-level port) for level-shifter analysis.

-to_pin to_pin_list

Specifies the loads (leaf cell pins or top-level ports) for level-shifter analysis.

-net target_net

Specifies the net for always-on analysis.

-isolation

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Enables unmapped isolation cell reporting with -lib_cells. This option is assumed by default with -lib_cells.

-enable_level_shifter

Enables unmapped enable level shifter cell reporting with -lib_cells. This option is assumed by default with -lib_cells.

-retention

Enables unmapped retention cell reporting with -lib_cells. This option is assumed by default with -lib_cells.

-verbose

Generates detailed information in the report.

DESCRIPTION
The analyze_mv_design command performs multivoltage analysis and reports design details that can help you understand
multivoltage-related issues. You can perform one of level-shifter analysis or always-on analysis or unmapped power management cell
reporting by using the -level_shifter or -always_on or -lib_cells option.

The level-shifter analysis lists variable settings, power state table information, signal connections, and library availability information.
The input for the level-shifter analysis is a pin-to-pin connection, which can be derived easily from the output of the check_mv_design
command.

The following variable settings are reported in the level-shifter analysis output:

Level Shifters on clock nets:

This setting is controlled by the auto_insert_level_shifters_on_clocks variable. It specifies the list of clock nets considered for
automatic level shifter insertion. If the value is "all", every clock net it considered. The default is an empty string.

Level shifter on top nets:

This setting is controlled by the compile_no_new_cells_at_top_level variable. It controls the capability of the tool to insert
level-shifter cells at top level. When the variable value is set to true, no new level-shifter cells are accepted. The default is false.

Level shifters allowed on leaf pin boundary:

This setting is controlled by mv_allow_ls_on_leaf_pin_boundary variable. When the setting is true, the tool is allowed to insert
level shifters at any driver or load pins of a net, even if the pins are not on a power domain boundary. The default is false.

The always-on analysis reports details about always-on constraints, related supply nets, relevant power state table settings, and library
cell availability for the target net.

With -lib_cells option, this command reports unmapped isolation, enable level shifter and retention cells for the current design. The
report will list out every element that is not mapped along with the reason on why it cannot be mapped.

If the user does not specify any other option with -lib_cells, tool will assume -isolation, -enable_level_shifter and -retention options.

User can limit the reporting of isolation or enable level shifter or retention cells by specifying one of -isolation or -enable_level_shifter
or -retention option respectively.

EXAMPLES
The following command analyzes a specified level-shifter connection:

prompt> analyze_mv_design -level_shifter \

-from_pin gprs_nrestore -to_pin GPRs/A_reg_reg[0]/NRESTORE

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...

Level Shifter Analysis (1/1)

from driver pin 'gprs_nrestore', to load pin 'GPRs/A_reg_reg[31]/NRESTORE'

*************************************
Level Shifter Analysis - Settings
*************************************
Level Shifters on clock nets: all
Level Shifters on top nets: TRUE
Level Shifters allowed leaf pin boundary: FALSE

********************************************************
Level Shifter Analysis - Driver and Load Related PST
********************************************************
Current Scope: ChipTop
Supply Names: VDD, VSS, VDDG,
Resulting Power States in this Scope:
VDD| VSS|VDDG|
drv: HV| GND| HV|
drv: HV| GND| LV|

********************************************************
Level Shifter Analysis - Drive to Load Pins and Nets
********************************************************
From Pin: gprs_nrestore
Related Supplies: VDD; VSS;
To Pin: GPRs/A_reg_reg[31]/NRESTORE
Related Supplies: VDDG; VSS;
--------------------------------------------------------

Pin: =domain boundary= gprs_nrestore;

Type: Design Port; Domain Boundary;
Constraint: not defined

Net: gprs_nrestore;
Domain: TOP;
Local Fanout: 1;
Primary Supply Nets: VDD, VSS,
Available Supply Nets: VDD, VSS, VDDI, VDDIS, VDDG, VDDM,
- Driver pin related supply nets (VDD, VSS) and load pin related supply nets
(VDDG, VSS) are available in the domain 'TOP'
- Driver pin related supply nets (VDD, VSS) are the primary supplies in the
domain 'TOP'

Pin: =domain boundary= GPRs/gprs_ret1;

Type: Hierarchical Port; Domain Boundary;
Constraint: not defined

Net: GPRs/gprs_ret1;
Domain: GPRS;
Local Fanout: 608;
Primary Supply Nets: VDDGS, VSS,
Available Supply Nets: VSS, VDDG, VDDGS,
- Neither driver pin related supply nets (VDD, VSS) nor load pin related
supply nets (VDDG, VSS) are primary supplies in the domain 'GPRS'

Pin: GPRs/A_reg_reg[31]/NRESTORE;
Type: Cell Input Pin; Lib Cell: RSDFCSRHD2BWP;

*********************************************
Level Shifter Analysis - Target Libraries
*********************************************
Required pin-to-pin level shifter type: H2L

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All level shifters cells found in the target libraries: 12

Usable level shifter cells: 12
Usable level shifter cells of type H2L: 4
Lib Cell 'mylib_wc09072/LVHL' works in the required voltage range:
Input voltage range [0.700 - 1.300]
Output voltage range [0.700 - 1.300]
Lib Cell 'mylib_wc0909/LVHL' works in the required voltage range:
Input voltage range [0.700 - 1.300]
Output voltage range [0.700 - 1.300]
Lib Cell 'mylib_bc11088/LVHL' works in the required voltage range:
Input voltage range [0.700 - 1.300]
Output voltage range [0.700 - 1.300]
Lib Cell 'mylib_bc1111/LVHL' works in the required voltage range:
Input voltage range [0.700 - 1.300]
Output voltage range [0.700 - 1.300]

The following command reports the unmapped isolation and enable level shifter in current design:

prompt> analyze_mv_design -lib_cells

.....
Isolation mapping failures:

Element(s) Cell name(s) Strategy Domain Clamp Sense Reasons

-------------------------------------------------------------------------------
mid_inst/out snps_PDC__iso0_snps_out1_UPF_ISO
iso0 PDC 0 low TLS mismatch(2);
Cannot infer regular iso
-------------------------------------------------------------------------------

Enable level shifter mapping failures:

Element(s) Cell name(s) Strategy Domain Clamp Sense Reasons

-------------------------------------------------------------------------------
Enable level shifter mapping should succeed.
-------------------------------------------------------------------------------

TLS mismatch: Library cell(s) cannot be used as they violate

target_library_subset constraint
Cannot infer regular iso: Inferring a regular isolation library cell will
lead to more corruption compared to RTL.
NOR-style isolation is needed
Retention mapping failures:

Cell name Strategy Domain Reasons

--------------------------------------------------------------------------------------------------------------
mid/bot/q1_reg PD1_RET1 PD1 Scan register type mismatch(1)
mid/bot/q2_reg PD1_RET1 PD1 Scan register type mismatch(1)
--------------------------------------------------------------------------------------------------------------

Scan register type mismatch: Some retention library cell(s) do not meet either set_register_type -exact or \
set_scan_register_type restriction

SEE ALSO
check_mv_design(2)
report_mv_library_cells(2)

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analyze_mv_feasibility
Analyzes multivoltage feasibility of current design.

SYNTAX
status analyze_mv_feasibility
[-lib_cells]
[-resolved_strategy]
[-isolation]
[-enable_level_shifter]
[-level_shifter]
[-repeater]
[-retention]
[-format output_format]
[-domain domain_name]
[-strategy strategy_name]
[-elements objects]
[-disable_clubbing]

Data Types
output_format string
domain_name string
strategy_name string
objects list

ARGUMENTS
-lib_cells

Analyzes the possibility of the tool to map isolation and enable level shifter cells for the current design with the technology libraries
provided. This option is assumed by default.

-resolved_strategy

Generates text based report of the highest precedence isolation, level-shifter, repeater and retention strategy resolved on domain
boundary pins or sequential cells. This option is assumed if the command is issued standalone.

-isolation

Enables isolation analysis. This option is assumed by default.

-enable_level_shifter

Enables enable level shifter analysis. This option is assumed by default with option -lib_cells.

-level_shifter

Enables reporting of resolved level shifter strategies. This option is assumed by default with option -resolved_strategy.

-repeater

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Enables reporting of resolved repeater strategies. This option is assumed by default with option -resolved_strategy.

-retention

Enables reporting of resolved retention strategies. This option is assumed by default with option -resolved_strategy.

-format output_format

This option takes a string value and the allowed value is html. This option is a means to specify the output format of the report. By
default, only text based report will be generated on the standard ouput.

-domain domain_name

This option takes a string value. Full hierarchical name of power domain should be specified. This option restricts
isolation/repeater/level-shifter resolved strategy report to have boundary (upper or lower) pins of the given domain.Similarly, it
restricts retention resolved strategy report to have sequential cells of the given domain. This option is only allowed with -
resolved_strategy.

-strategy strategy_name

This option takes a string value. This option restricts isolation/repeater/level-shifter resolved strategy report to have domain
boundary(upper or lower)pins with the given strategy. Similarly, it restricts retention resolved strategy report to have sequential cells
with the given strategy. When specifying a power management strategy, a power domain should also be specified with -domain
option. If the specified strategy is not a part of the specified power domain, the command fails. This option is only allowed with -
resolved_strategy.

-elements objects

Behaviour with -resolved_strategy: This option takes list of pin names or cell names. Full hierarchical names should be specified.
This option is used to restrict resolved strategy report to only have boundary(upper or lower) pins and cells which are part of the
specified element list. If a pin name is specified in the element list, resolved level-shifter/isolation/repeater report will be generated
only if it is a domain boundary pin. If a leaf cell is specified, resolved retention strategy report will be only if it is a sequential element
with a resolved retention strategy. If hierarchical cell name is specified in the element list, then resolved level-
shifter/repeater/isolation strategy report will be generated for all the domain boundary pins under the scope of this hierarchical cell,
resolved retention strategy report will be generated for all the sequential elements under the scope of this hierarchical cell.
Behaviour with -lib_cells: This option takes list of pin names, net names or cell names. Full hierarchical names should be specified.
This option is used to restrict lib_cells report to only have those unmapped isolation and enable level shifter cells that are inserted at
the specified pins, nets (pins of nets) or cells (pins of cells).

-disable_clubbing

This option disables clubbing of rows in resolved strategy report. This option does not take any value.

DESCRIPTION
With -lib_cells option, this command analyzes the possibility of the tool to map isolation and enable level shifter cells for the current
design with the technology libraries provided.

In the event any isolation or enable level shifter cells cannot be mapped this command will generate a text based report by default on
the standard output. The report will list out every element that would not be mapped along with reason on why it cannot be mapped.

With -format html option, tool will also generate a detailed HTML report. The HTML report will list all the technology library cells that
will be attempted for mapping but discarded, along with the reason for discarding it.

If the user does not specify any option with this command, tool will assume all of -lib_cells, -isolation and -enable_level_shifter
options and will analyze the possibility of the tool to map both isolation and enable level shifter cells for the current design with the
technology libraries provided.

User can limit the analysis to isolation or enable level shifter cells by specifying one of -isolation or -enable_level_shifter option
respectively.

When mapping analysis is requested, this command will return a status of 1 when isolation and enable level shifter cells can be

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Synthesis Tool Commands Version S-2021.06-SP2

mapped along with an information message. It will return a status of 0 when any of them cannot be mapped along with an error
message.

With -resolved_strategy option, user can generate a text report of all domain boundary pins with a resolved isolation/level-
shifter/repeater strategies and all sequential cells with resolved retention strategy. The reported strategy will be the highest
precedence strategy on the domain boundary or sequential cell. This option assumes -isolation, -level_shifter, -repeater, -retention
by default.

User can restrict report to specific domain, strategy or objects with -domain, -strategy, -elements options respectively.

By default, rows of resolved strategy and mapping analysis text reports are clubbed. If -disable_clubbing is used, resolved strategy
report will not club pins or sequentail cells belonging to the same hierarchcial cells or bus to a single row. Each domain boundary pin or
sequential cell will be reported in a separate row.

When resolved strategy report is requested, this command will return a status of one when there are no errors reported and a status of
0 otherwise.

EXAMPLES
The following command analyzes current design with the technology libraries provided:

prompt> analyze_mv_feasibility -lib_cells

.....
Isolation mapping failures:

Element(s) Strategy Domain Clamp Sense Reasons

-------------------------------------------------------------------------------
mid_inst/out iso0 PDC 0 low TLS mismatch(2);
Cannot infer regular iso
-------------------------------------------------------------------------------

Enable level shifter mapping failures:

Element(s) Strategy Domain Clamp Sense Reasons

-------------------------------------------------------------------------------
Enable level shifter mapping should succeed.
-------------------------------------------------------------------------------

TLS mismatch: Library cell(s) cannot be used as they violate

target_library_subset constraint
Cannot infer regular iso: Inferring a regular isolation library cell will
lead to more corruption compared to RTL.
NOR-style isolation is needed

Error: Not all the isolation and enable level shifter cells can be mapped . (UPF-909)
0

prompt> analyze_mv_feasibility -resolved_strategy

****************************************
Report : resolved_strategy
Design : top
****************************************

Attributes that prevent power management cell insertion

dt - dont_touch
an - analog net
pad - pad-port path
pg - power/ground pin

Resolved Isolation strategies:

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--------------------------------------------------------------------------------
Domain-Boundary HighConn (domain) LowConn (domain) Attributes
--------------------------------------------------------------------------------
mid_inst_1/bot_inst_2 PD1_ISO1(PD1) - -
mid_inst_1/bot_inst_1 PD1_ISO1(PD1) - -
--------------------------------------------------------------------------------

Resolved Level shifter strategies:

--------------------------------------------------------------------------------
Domain-Boundary HighConn (domain) LowConn (domain) Attributes
--------------------------------------------------------------------------------
mid_inst_1/bot_inst_1/out1 lsm(PD1) lsb(PD2) -
--------------------------------------------------------------------------------

Resolved Repeater strategies:

--------------------------------------------------------------------------------
Domain-Boundary HighConn (domain) LowConn (domain) Attributes
--------------------------------------------------------------------------------
in1 - TOP_rptr_1(TOP) -
in2 - TOP_rptr_1(TOP) -
--------------------------------------------------------------------------------

Resolved Retention strategies:

--------------------------------------------------------------------------------
Cell Strategy(domain) Attributes
--------------------------------------------------------------------------------
mid_inst_2/bot_inst_2 RET2(PDM) -
mid_inst_2/bot_inst_1 RET2(PDM) -
--------------------------------------------------------------------------------
Note: Use -lib_cells option to know if the resolved isolation strategies will result in successful mapping
1

SEE ALSO
analyze_mv_design(2)
check_mv_design(2)
report_mv_library_cells(2)

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analyze_rtl_congestion
Reports pre-synthesis congestion analysis.

SYNTAX
status analyze_rtl_congestion
[-nosplit]

ARGUMENTS
-nosplit

Prevents line splitting and facilitates writing application to extract information from the report output. Most of the design information
is listed in fixed-width columns. If the information in a given field exceeds the column width, the next field begins on a new line,
starting in the correct column.

DESCRIPTION
The analyze_rtl_congestion command reports pre-synthesis congestion analysis for the current design. The command evaluates the
RTL for potential congestion issues and reports the issues so you can resolve them early in the design flow.

The report includes the line numbers in the RTL where the issues occur to help you identify where RTL changes are needed.

The following types of structures are known to cause congestion:

Large MUXes

Large data switches

Large selectors

Large ROMS

Parallel high-fanout nets

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example runs the analyze_rtl_congestion command:

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prompt> analyze_rtl_congestion

****************************************
Report : RTL congestion
Design : mem
Version: I-2013.12-SP1-CS1
Date : Thu Dec 12 03:54:00 2013
****************************************

########################################
Large MUX details
########################################

--------------------------------------------------------------------------------
Structure Cell name Size (width) Line No RTL File
--------------------------------------------------------------------------------
MUX_OP C10567 16 x 1 (163) 83 /u/9000560869.v
MUX_OP C10566 16 x 1 (163) 82 /u/9000560869.v

########################################
Large Data Switch details
########################################

--------------------------------------------------------------------------------
Structure Cell name Size (width) Line No RTL File
--------------------------------------------------------------------------------
DATA_SWITCH
dataline_A_0/C76676 2 x 1 (128) 361 /rtl/dataline.v
dataline_A_0/C76672 2 x 1 (128) 365 /rtl/dataline.v
DATA_SWITCH
dataline_A_0/C76614 2 x 1 (8) 159 /rtl/dataline.v
dataline_A_0/C76613 3 x 1 (8) 159 /rtl/dataline.v

########################################
Large ROM details
########################################

--------------------------------------------------------------------------------
Structure Cell name Size (width) Line No RTL File
--------------------------------------------------------------------------------
ROM C81944 4096 x 1 (21) 9 /rtl/large_rom2.v

########################################
Large Selector details
########################################

--------------------------------------------------------------------------------
Structure Cell name Size (width) Line No RTL File
--------------------------------------------------------------------------------
SELECT_OP C117247 151 x 1 (4) 83634 /rtl/pba_csr32.v
SELECT_OP C117242 190 x 1 (1) 83634 /rtl/pba_csr32.v

########################################
Parallel High Fanout Net details
########################################

--------------------------------------------------------------------------------
Structure Net name Cell name Loads Line No RTL File
--------------------------------------------------------------------------------
PARALLEL_HFN
sel[0][0][0] sel_reg[0][0][0] 128 18 /rtl/reg-file-2.sv
sel[0][0][1] sel_reg[0][0][1] 128 18 /rtl/reg-file-2.sv

PARALLEL_HFN

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sel[0][1][0] sel_reg[0][1][0] 128 18 /rtl/reg-file-2.sv

sel[0][1][1] sel_reg[0][1][1] 128 18 /rtl/reg-file-2.sv
1

SEE ALSO
report_congestion(2)

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append_to_collection
Adds objects to a collection and modifies a variable.

SYNTAX
collection append_to_collection
[-dict dict_var]
[-unique]
var_name
object_spec

Data Types
dict_var variable referencing a dict
var_name variable referencing a collection
object_spec list

ARGUMENTS
-dict dict_var

Specifies a variable name referencing a dict object. When this is specified the var_name argument specifies the key in the dict to
update.

-unique

Indicates that duplicate objects are to be removed from the resulting collection. By default, duplicate objects are not removed.

var_name

Specifies a variable name. The objects matching object_spec are added into the collection referenced by this variable.

object_spec

Specifies a list of named objects or collections to add.

DESCRIPTION
The append_to_collection command allows you to add elements to a collection. This command treats the variable name given by the
var_name option as a collection, and it appends all of the elements in object_spec to that collection. If the variable does not exist, it is
created as a collection with elements from the object_spec as its value. If the variable does exist and it does not contain a collection, it
is an error.

Alternatively this command may also update a value in a dict. When -dict is specified the dict_var is treated as a dict and the key
specified by var_name is updated. If the dict variable is unset the dict is created. If the value referenced by the variable is not a dict it is
an error.

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The result of the command is the collection that was initially referenced by the var_name option (or dict key value), or the collection
created if the variable did not exist.

The append_to_collection command provides the same semantics as the common use of the add_to_collection command;
however, this command shows significant improvements in performance.

An example of replacing the add_to_collection command with the append_to_collection command is provided below. For example,

set var_name [add_to_collection $var_name $objs]

Using the append_to_collection command, the command becomes:

append_to_collection var_name $objs

Updating a key in a dictionary:

append_to_collection -dict drivers $pinName $newDrivers

The append_to_collection command can be much more efficient than the add_to_collection command if you are building up a
collection in a loop. The arguments of the command have the same restrictions as the add_to_collection command. For more
information about these restrictions, see the add_to_collection man page.

EXAMPLES
The following example from PrimeTime shows how a collection can be built up using the append_to_collection command:

prompt> set xports

Error: can't read "xports": no such variable
Use error_info for more info. (CMD-013)
prompt> append_to_collection xports [get_ports in*]
{in0 in1 in2}
prompt> append_to_collection xports CLOCK
{in0 in1 in2 CLOCK}

SEE ALSO
add_to_collection(2)
foreach_in_collection(2)
index_collection(2)
remove_from_collection(2)
sizeof_collection(2)
dict(2)

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apply_clock_gate_latency
Annotates the clock latencies on the existing clock-gating cells based on the settings previously specified using the
set_clock_gate_latency command.

SYNTAX
status apply_clock_gate_latency

ARGUMENTS
The apply_clock_gate_latency command has no arguments.

DESCRIPTION
The apply_clock_gate_latency command annotates the clock latencies on the existing clock-gating cells based on the settings
previously specified using the set_clock_gate_latency command.

Use this command to do the following:

Manually annotate clock-latency values specified by the set_clock_gate_latency command to existing clock-gating cells

Modify clock-latency values applied to clock-gating cells after gate-level clock gating is finished.

If an inconsistent clock-latency setting is detected during annotation, the tool tries to resolve it to produce a situation where clock
latencies are monotonically increasing values in the path going from the clock source to the gated registers. The following actions can
be performed to achieve this:

Assume that clock-gating cell A is directly driving one or more registers, and some clock-latency settings have been provided for
the timing of these gated registers by using value 0 for the stage option of set_clock_gate_latency command or by propagation
of latency specified for the clock object. In this situation, the latency annotated on cell A is higher than the latency provided for
gated registers, then the latency on clock-gating cell A is overwritten with the latency provided for gated registers. If this fix is
done, it is informed by warning message PWR-746.

If clock-gating cell A is driving another clock-gating cell B, and the clock latency set on A is higher than the one set on B, the tool
resolves it by overwriting the clock latency on A with the value set on B. If this fix is done, it is also informed by warning message
PWR-746.

To remove the settings specified using set_clock_gate_latency, use the reset_clock_gate_latency command.

If the variable power_cg_physically_aware_cg is enabled, then the annotation of latency values from set_clock_gate_latency is
disabled.

Multicorner-Multimode Support
The actual clock latency annotation performed during the execution of compile_ultra or apply_clock_gate_latency commands is

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done for all the scenarios for which a clock latency value is available.

SEE ALSO
power_cg_physically_aware_cg(3)
remove_clock_latency(2)
report_clock_gating(2)
reset_clock_gate_latency(2)
set_clock_gate_latency(2)
set_clock_latency(2)

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apply_power_model
Apply a power model which describes the power intent of a reference library cell to instances.

SYNTAX
status apply_power_model
power_model_name
[-elements instance_names]
[-supply_map supply_map_list]
[-port_map port_map_list]
[-parameters param_map_list]
[-all_hard_macros]

Data Types

power_model_name string
instance_names list of instances
supply_map_list list of power_model_supply_set current_scope_supply_set
port_map_list list of power_model_supply/logic_port current_scope_supply/logic_net
param_map_list list of power_model_parameter parameter_value

ARGUMENTS
power_model_name

Specifies the name of the power model to be applied. The name should be a simple (non-hierarchical) name.

The applied power model is searched in this descending order of preference:

1. Power models defined in the current scope.

2. Power models defined in any direct ancestor scope: the closest the better.

3. Power models defined in user power model library. Please see variables upf_power_model_search_path and
upf_power_model_library.

4. Power models defined in any scope.

-elements instance_names

Specifies a collection of cells that this power model should be applied to.

If this option is not specified, the power model will be applied to all cells in and under the current scope whose reference library cells
match those specified in the power model (i.e. library cells listed in -for option of the define_power_model command).

-supply_map supply_map_list

Specifies the mapping of supply sets in the power model to supply sets in the current scope. For example: -supply_map
{{model_vdd top_vdd} {model_vss top_vss}}

-port_map port_map_list

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Specifies the mapping of supply/logic ports in the power model to supply/logic nets in the current scope. For example: -port_map
{{model_supply_port top_supply_net} {model_logic_port top_logic_net}}

-parameters param_map_list

Specifies the mapping of parameters in the power model to actual parameter values. For example: -parameters {{model_param1
"value_1"} {model_param2 "value_2"}}

-all_hard_macros

Apply power models to all hard macro cells under the current scope with matching power model, i.e., the macro lib cell is included in
the -for option of the define_power_model command, or the power model name is the lib cell name.

power_model_name must not be provided and no other options can be specified.

DESCRIPTION
The apply_power_model command binds the power_model_name to the cell instances specified by the -elements option. The
associated parameter binding specified via the -parameters option allows objects within the environment to be bound to parameters
defined within the power model. Not all parameters within the power model need to be bound to objects in the environment and
parameters that are not bound shall retain their default values during run time.

The apply_power_model command sets the scope to each of the specified set of instances, referred to as the instance scope, and
then executes the set of UPF commands in the power model power_model_name. Upon return, the current scope is restored to the
scope in which the command was invoked. Similarly, the command also sets the design top instance to specified instance, and
restores it to previous state after executing UPF commands for that instance.

Multicorner-Multimode Support

This command has no dependency on scenario-specific information.

EXAMPLES
The following example applies a power model to two macro cells:

prompt> define_power_model MODEL -for {macro_lib_cell} {

create_supply_set SS_macro
create_supply_set SS_macro_ao
create_supply_port VDD_macro
create_supply_port VSS_macro
}
prompt> create_supply_set SS_top
prompt> create_supply_set SS_top_ao
prompt> create_supply_net VDD_top
prompt> create_supply_net VSS_top
prompt> apply_power_model MODEL -elements {u1/macro u2/macro}
-supply_map {{SS_macro SS_top} {SS_macro_ao SS_top_ao}}
-port_map {{VDD_macro VDD_top} {VSS_macro VSS_top}}

The following example applies a power model to all instanced cells of lib_cell in or under the current scope. Power domain PD_macro
will be created in each of the macro cells:

prompt> define_power_model MODEL -for {lib_cell} {

add_parameter DOMAIN -default domain -description "top power domain in model"
create_supply_net VDD
create_supply_net VSS
create_supply_set SS -function {power VDD} -function {ground VSS}

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create_power_domain PD_$DOMAIN -supply {primary SS} -include_scope

}
prompt> apply_power_model MODEL -parameters {{DOMAIN macro}}

The following example applies power model MODEL_A to all instantiated cells of lib_cell_A and applies power model lib_cell_B to all
instantiated cells of lib_cell_B in or under the current scope:

prompt> sh cat ./power_model.upf

define_power_model MODEL_A -for {lib_cell_A} { create_power_domain PD_A }
prompt> sh cat ./lib_cell_B.upf
define_power_model lib_cell_B { create_power_domain PD_B }
prompt> set upf_power_model_search_path "."
prompt> set upf_power_model_library "power_model.upf lib_cell_B.upf"
prompt> apply_power_model -all_hard_macros

SEE ALSO
define_power_model(2)
add_parameter(2)
report_power_model(2)
upf_power_model_library(3)
upf_power_model_search_path(3)

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apropos
Searches the command database for a pattern.

SYNTAX
string apropos
[-symbols_only]
pattern

Data Types
pattern string

ARGUMENTS
-symbols_only

Searches only command and option names.

pattern

Searches for the specified pattern.

DESCRIPTION
The apropos command searches the command and option database for all commands that contain the specified pattern. The pattern
argument can include the wildcard characters asterisk (*) and question mark (?). The search is case-sensitive. For each command that
matches the search criteria, the command help is printed as though help -verbose was used with the command.

Whereas help looks only at command names, apropos looks at command names, the command one-line description, option names,
and option value-help strings. The search can be restricted to only command and option names with the -symbols_only option.

When searching for dash options, do not include the leading dash. Search only for the name.

EXAMPLES
In the following example, assume that the get_cells and get_designs commands have the -exact option. Note that without the -
symbols_only option, the first search picks up commands which have the string "exact" in the one-line description.

prompt> apropos exact

get_cells # Create a collection of cells
[-exact] (Wildcards are considered as plain characters)

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patterns (Match cell names against patterns)

get_designs # Create a collection of designs

[-exact] (Wildcards are considered as plain characters)
patterns (Match design names against patterns)

real_time # Return the exact time of day

prompt> apropos exact -symbols_only

get_cells # Create a collection of cells
[-exact] (Wildcards are considered as plain characters)
patterns (Match cell names against patterns)

get_designs # Create a collection of designs

[-exact] (Wildcards are considered as plain characters)
patterns (Match design names against patterns)

SEE ALSO
help(2)

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as_collection
Find a collection by name

SYNTAX
string as_collection
[-check]
collection1

Data Types
collection1 string

ARGUMENTS
-check

Return 1 if collection1 is a collection

collection1

The collection to convert

DESCRIPTION
This command looks up a string value and returns it as a collection it the collection is still live. All other values are passed through this
command unmodified.

This command is also provides a simple way to check if the input is a collection.

EXAMPLES
Check if a value is a collection:

prompt> as_collection -check [get_cells]

1
prompt> as_collection -check hello
0

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SEE ALSO
collections(2)
foreach_in_collection(2)

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associate_supply_set
Associates a supply set handle to another supply set handle or supply set reference, or associates a list of supply sets.

SYNTAX
status associate_supply_set
supply_set_names
-handle supply_set_handle

Data Types
supply_set_names list
supply_set_handle string

ARGUMENTS
-handle supply_set_handle

Specifies the supply set handle on which the action is performed.

This is an optional argument.

DESCRIPTION
The associate_supply_set command associates the supply set handle specified with the -handle option to the specified supply set.
Also associate_supply_set command associates a list of supply sets. After the association, the tool treats corresponding functions in
each supply set to be virtually connected. So, the supply sets inherit common switching behavior and must eventually be resolved to
the same physical supply net.

A supply set supports the following functions:

Power
Ground

Multicorner-Multimode Support
This command has no dependency on scenario specific information.

EXAMPLES
The following example associates primary supply handle of domain PD1 to a supply set SS1

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prompt> associate_supply_set SS1 \

-handle PD1.primary
1

prompt> associate_supply_set {SS1 PD1.primary}

1

SEE ALSO
create_power_domain(2)
create_supply_set(2)

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balance_buffer
Builds a balanced buffer tree on user-specified nets and drivers.

SYNTAX
status balance_buffer
[-from start_point_list]
[-to end_point_list]
[-net net_list]
[-force]
[-library library_name]
[-prefer buffer | inverter | lib_cell_name]

Data Types

start_point_list string
end_point_list string
net_list string

ARGUMENTS
-from start_point_list

Specifies a list of driver pins from which buffer trees are to be created.

-to end_point_list

Specifies a list of loads to buffer.

-net net_list

Specifies a list of nets to buffer.

-force

Forces balance_buffer implementation regardless of cost effect.

-library library_name

Specifies the library where the lib_cell_name is contained. You must specify this option when specifying lib_cell_name. If you do not
specify lib_cell_name, this option is ignored.

-prefer buffer | inverter | lib_cell_name

Specifies the preferred cell type for the buffer tree.

When buffer is specified, the tool creates a buffer tree using buffer-type library cells.

When inverter is specified, the tool creates a buffer tree using inverter-type library cells.

When lib_cell_name is specified, that library cell is the only cell used to form the buffer tree. You must specify library_name

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when specifying lib_cell_name. The library cell must be a buffer or an inverter library cell.

DESCRIPTION
The balance_buffer command creates DRC-free balanced buffer trees on user-specified nets and drivers. It removes existing buffer
trees on the specified nets or drivers if any are present and builds a new DRC-free buffer tree. The buffer trees created in one
hierarchy considers loads and drivers across hierarchies and creates buffer trees at the fanout nets into these hierarchies.

The balance_buffer command generates a layered buffer tree, where each stage uses the same buffer or inverter and each gate of a
given stage roughly drives the same load capacitance. The type of cells used are a combination of buffer and inverter cells available
from the target library, unless the -prefer option is specified.

Any input port driving a net that is to be buffered by balance_buffer must have its drive value set. Otherwise, the default value
specifies that the input port has infinite drive, and no buffer tree is created. The balance_buffer command uses the NLDM information
specified in the target library for calculations on a buffer tree.

Note that balance_buffer does not take clock skew into account and, therefore, is not recommended for clock trees.

EXAMPLES
In the following example, a buffer tree is first built from port i0. Then, two additional buffer trees are built to drive load1 and load2.

prompt> read -f edif test.edif

prompt> set_driving_cell -cell IV i0
prompt> balance_buffer -from i0
prompt> balance_buffer -to {load1, load2}

SEE ALSO
compile(2)

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balance_registers
Moves the registers of the current design to achieve a minimum cycle time.

SYNTAX
status balance_registers

DESCRIPTION
The balance_registers command moves the registers of a design to obtain a minimum cycle time. You do not have to set the
balance_registers attribute to invoke balance_registers outside of the compile command. Using balance_registers outside of
compile usually gives better control and better quality of results because the gate-level netlist used as a starting point is defined
exactly by the initial compile.

The balance_registers command has the following requirements:

All registers must be edge-triggered flip-flops clocked by the same phase of the same clock; or, all registers must be master-
slave elements with the same signals for the master and slave pins.

Flip-flops and master-slave elements cannot be present in the same design.

Master and slave clock waveforms cannot overlap.

The clock pins of all flip-flops in the design must be connected to the same clock port. The interconnection from the clock port to
the clock pins can contain buffer and inverter cells having one input and one output pin. All paths from the clock port to the clock
pins of the registers can contain either an even number (including zero) of inverters or an odd number of inverters. These paths
cannot be comprised of both even and odd numbers of inverters in a single design.

The outputs of the clock network can be connected to only sequential cells. The clock network of the retimed design will not
contain any cells.

Flip-flops that have asynchronous set or clear pins are not moved.

Designs cannot contain a combinational loop.

Set the timing constraints for the design in the following way:

The external clock port of the design must have a clock constraint created by the create_clock command. This will be
called the base clock.

All primary inputs of the design must have a non-negative input delay relative to the base clock.

All primary outputs of the design must have a non-negative output delay relative to the base clock.

Negative input and output delays are tolerated, but the quality of the final retiming result may be worse.

Input and output delays relative to virtual clocks or clocks other than the base clock are ignored.

Point-to-point timing exceptions as created by the set_false_path, set_multicycle_path, set_max_delay, and

set_min_delay commands are tolerated but ignored.

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Case analysis constraints are ignored.

Designs cannot contain tristate cells or unmapped synthetic library components.

By default, balance_registers ungroups all instances in a design before moving registers. Avoid ungrouping by setting the
dont_touch attribute on instances that are not to be ungrouped. The balance_registers command does not ungroup an instance that
has the dont_touch attribute, and does not place any registers inside an instance that has the dont_touch attribute.

The balance_registers command includes a delay modeling capability. For predictability, the algorithm selects a flip-flop from the
target library with small setup time, good drive at the outputs, and low input loading as compared with other registers in the library.
This register is designated as the preferred flip-flop. Sequential mapping is invoked in the final step to improve the circuit by remapping
the registers. The preferred flip-flop helps provide tighter bounds on the performance variation after the balance_registers sequence.
To disable delay modeling, set the shell variable balance_reg_delay to 0.

As part of the delay modeling capability, balance_registers provides some statistics on the delays in the circuit. If the preferred flip-
flop appears as a driver for a net, balance_registers analyzes the circuit to compute the clock-pin-to-next-state-pin delay for that net.
The maximum of all these clock-pin-to-next-state pin delays is used as a reference for checking the input delays of the design. They
should be larger than the average clock-pin-to-next-state pin delay.

The clock-pin-to-next-pin-delay, the setup time of the preferred flip-flop and the clock uncertainty sum up to the clock correction. The
sum of the clock correction and the maximum critical path length reported when balance registers has finished the register moving
phase give an estimate for the clock period after retiming. However, the value of the clock correction does not influence the minimum
clock period achieved. An example detailing the output of the delay modeling capability is shown in the EXAMPLES section. More
information on the balance_registers command can be found in the Design Compiler documentation.

EXAMPLES
The following example reads in the design pipe_mult_32.db, and moves the registers to achieve a minimum cycle time:

prompt> read pipe_mult_32.db

prompt> balance_registers

The output provided by the delay modeling capability shows that the sequential cell F611 from the target library is selected as the
preferred flip-flop F611. The relevant delay information of the design is summarized in the two tables titled "Design Analysis" and
"Clock-to-Q delay distribution."

prompt> balance_registers pipe_test

Loading design 'pipe_test'

Beginning retiming
------------------
Retiming pipe_test
Preferred register is F611 with setup = 1.34
Design Analysis
-----------------------------------------------------
| Worst | Best | Average |
-----------------------------------------------------
clock to Q | 1.85 | 1.40 | 1.54 |
-----------------------------------------------------
Clock to Q delay distribution
--------------------------------------------
| delay range | number of nets |
--------------------------------------------
| [1.40 - 1.49] | 23 |
| [1.49 - 1.58] | 33 |
| [1.58 - 1.67] | 14 |
| [1.67 - 1.76] | 4 |
| [1.76 - 1.85] | 4 |
--------------------------------------------
Lower bound estimate = 5.40

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Critical path length = 5.40

Clock correction = 3.19 (clock-to-Q delay = 1.85, setup = 1.34, uncertainty = 0.
00) Structuring 'pipe_test'
Mapping 'pipe_test'

Retiming complete
-----------------
Transferring Design 'pipe_test' to database 'mult4_g.db'
1

SEE ALSO
current_design(2)
set_balance_registers(2)
set_dont_touch(2)
attributes(3)

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break
Immediately exits a loop structure.

SYNTAX
int break

ARGUMENTS
None

DESCRIPTION
The break command immediately exits the innermost loop structure. Use the break command to terminate a while loop, rather than
waiting until the loop evaluates to zero.

The break command returns the integer 1, indicating successful operation. A syntax error is reported if break is used outside a loop
structure.

EXAMPLES
In the following example, a list of file names is scanned until the first file name that is a directory is encountered. The break command
is used to terminate the foreach loop when the first directory name is encountered.

foreach f [which {VDD.ave GND.tech p4mvn2mb.idm}] {

echo -n "File $f is "
if { [file isdirectory $f] == 0 } {
echo "NOT a directory"
} else {
echo "a directory"
break
}
}

SEE ALSO

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continue(2)
while(2)

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capture_detailed_script_runtime
Enable detailed capture of runtime script report to a file.

SYNTAX
status capture_detailed_script_runtime
[-start]
[-stop]
[-output output]

ARGUMENTS
-start

Start detailed capture of report script runtime to a file

-stop

Stop detailed capture of report script runtime to a file

-output output

Specify a file name for the output

DESCRIPTION
The report_script_runtime command reports the wall clock or CPU time used by commands issued on the current session. It also
reports on the number of times the command was executed. The capture_detailed_script_runtime command enables detailed
capture of runtime script report to a file.

SEE ALSO
report_script_runtime(2)

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cd
Changes the current directory.

SYNTAX
status cd
[directory]

Data Types
directory string

ARGUMENTS
directory

Specifies an existing directory name.

DESCRIPTION
The cd command changes the current directory to the specified directory. If you do not specify directory, your login or home directory
becomes the new current directory. By default, the current directory is the directory where the shell is invoked.

A file specification of dot (.) is shorthand for the current directory. Dot is commonly included in the search_path variable. Changing
the current directory changes the interpretation of "." in the search_path variable.

Note that the sh command cannot be used to change directories.

EXAMPLES
The following are examples of using the cd command:

prompt> cd /usr/designer
prompt> pwd
/usr/designer

prompt> cd joe
prompt> pwd
/usr/designer/joe

prompt> cd ../bob

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prompt> pwd
/usr/designer/bob

prompt> cd ~
prompt> pwd
/usr/designer/joe

prompt> cd ~doug
prompt> pwd
/usr/designer/doug

prompt> cd
prompt> pwd
/usr/designer/joe

prompt> cd /usr/designer
prompt> ls
bob designs doug
joe one.ddc two.ddc

prompt> cd designs
prompt> ls
one.ddc other.ddc

prompt> set_app_var search_path ". ~"

prompt> read_ddc {one.ddc two.ddc}

Loading ddc file '/usr/designer/designs/one.ddc'
Loading ddc file '/usr/designer/joe/two.ddc'

prompt> cd /tmp

prompt> read_ddc one.ddc

Loading ddc file '/usr/designer/joe/one.ddc'

SEE ALSO
ls(2)
pwd(2)

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cell_of
Returns the cell objects for the specified pins in the current design.

SYNTAX
list cell_of
[object_list]

Data Types
object_list list

ARGUMENTS
object_list

Specifies a list of pins in the current design whose cells are returned by the cell_of command.

DESCRIPTION
The cell_of command returns a list of cell objects that own the pins specified in the object_list. If no cells are found, the return value is
an empty list ({}). Double quotation marks (" ") are needed for pin names that are ambiguous to the command parser.

EXAMPLES
The following example returns the cell of the specified pin in the current design:

prompt> cell_of U1/P

{U1}

The following example returns the cell of pin "reg(8)/Q" in the current design:

prompt> cell_of "reg(8)/Q"

{reg(8)}

The following example returns the list of cells for the given list of pins. The first cell is the owner cell of the first pin and the second cell
is the owner cell of the second pin.

prompt> cell_of {U3/B U9/A}

{U3 U9}

The following example returns the cell of the given pin. The cell name is a hierarchical name at the current level, which can be found

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after ungrouping.

prompt> cell_of {U3/U1/B}

{U3/U1}

The following example returns a warning message when the pin does not exist in the current design:

prompt> cell_of U999/Z

Warning: Can't find pin `U999/Z' in design `TOP'. (UID-95)
{}

The following example returns the cell of a hierarchical pin:

prompt> cell_of U1/U2/U3/A

{U1/U2/U3}

SEE ALSO
all_connected(2)

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change_link
Changes the design to which a cell is linked.

SYNTAX
status change_link
object_list
design_name
[-all_instances]
[-force]
[-pin_map pin_map_list]

Data Types

object_list list
design_name string
pin_map_list list

ARGUMENTS
object_list

Specifies the cells or references in the current design for which to change the link.

design_name

Specifies the name of the design to which to link the cells or references in the object list.

-all_instances

Enables the command to accept instance cells in the object list.

-force

Enables the command to allow mismatched pin counts, as long as any mismatched cells in the object list have fewer pins than the
specified design.

-pin_map pin_map_list

Specifies the pin mapping used to map old pin names to new pin names. The pin name must be the reference cell pin name.

To specify the pin mapping, use the following syntax:

{{old_pin1 new_pin1} ... {old_pin_n new_pin_n}}

New pins maintain the same net connections as the corresponding old pins.

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DESCRIPTION
The change_link command specifies a design for which to change the link for a cell or reference.

If you specify a cell in the object list, the command changes it to one occurrence of the specified design. If you specify a reference in
the object list, the command changes all cells of the specified reference type to occurances of the design.

You can change the cell or reference link only to a compatible design. For example, the design must have the same number of ports
with the same name and direction as the cell or reference.

Although the design_name argument accepts names in the format library/library_cell, it does not imply that the actual library cell used
for the new cell will be from the specified library. The actual library cell used is determined by the current link library settings.

During change_link activity, all Synopsys database format link information is copied from the old design to the new design. If the old
design is a synthetic module, all attributes of the old synthetic module are moved to the new link. After running the change_link
command, link the design with the link command.

Use the -all_instances option when any cell in the object_list argument is an instance in the lower hierarchy and its parent cell is not
unique. All similar instance cells under the same parent design are automatically linked to the new reference design. You do not have
to change the current design to change the link for the instance cells in the lower design hierarchy. You do not need to use the -
all_instances option if none of the cells in the object_list argument is an instance in the lower hierarchy or its parent cell is unique.

A common use of the change_link command for hierarchical cells is to rename designs and to change the cell links to the designs of
the new names. In these cases, use the rename_design command with the -update_links option instead of the copy_design,
rename_design, change_link and remove_design command set. The rename_design command provides faster runtime. For more
information, see the rename_design command man page.

EXAMPLES
The following example shows a common use of the change_link command. The ADDER design is copied to a new design named
MY_ADDER. The U1 and U2 cells are then linked from the current design to MY_ADDER.

prompt> copy_design ADDER MY_ADDER

Copying design 'ADDER' to 'MY_ADDER'

prompt> change_link {U1 U2} MY_ADDER

The following example shows an improper use of the change_link command. The specified cell does not have the same number of
ports as the design to which it is being linked.

prompt> change_link U3 HALF_ADDER

Error: Number of pins on cell 'U3' don't equal design 'HALF_ADDER'

The following example uses the -all_instances option:

prompt> current_design
Current design is 'top'.
{top}

prompt> get_cells -hierarchical -filter "ref_name == bot"

{mid1/bot1 mid1/bot2}
1

prompt> get_cells -hierarchical -filter "ref_name == IVA"

{mid1/bot1/inv1 mid1/bot2/inv1 mid1/bot1/inv2 mid1/bot2/inv2 mid1/inv3}
1

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prompt> change_link mid1/bot1/inv1 lsi_10k/IVAP -all_instances

Information: Changed link for all instances of cell 'inv1' in subdesign 'bot'. (UID-193)
1

prompt> get_cells -hierarchical -filter "ref_name == IVAP"

{mid1/bot1/inv1 mid1/bot2/inv1}
1

prompt> get_cells -hierarchical -filter "ref_name == IVA"

{mid1/bot1/inv2 mid1/bot2/inv2 mid1/inv3}
1

In the previous example, the bot design has cells named inv1 and inv2 that were linked to lsi_10k/IVA. The mid1/bot1 and mid1/bot2
cells instantiate the bot design. The mid1/inv3 cell is also linked to lsi_10k/IVA. After running the change_link command in the
example, the mid1/bot1/inv1 and mid1/bot2/inv1 cells are relinked to lsi_10k/IVAP, because they are the instances of the same inv1
cell in the bot design. The mid1/bot1/inv2 and mid1/bot2/inv2 cells are not relinked because they are not the instances of the inv1 cell
in the bot design. The mid1/inv3 cell is not relinked because it is not in an instance that instantiates the bot design.

The following example uses the change_link command to change the reference of cell using the -pin_map option:

prompt> change_link U3 lsi_10k/IVDA -pin_map { {A B} {Z X}}

SEE ALSO
copy_design(2)
current_design(2)
link(2)
rename_design(2)

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change_names
Changes the names of ports, cells, and nets in a design.

SYNTAX
status change_names
[-rules name_rules]
[-hierarchy]
[-verbose]
[-names_file names_file]
[-log_changes log_file]
[-restore]
[-dont_touch object_list]
[-instance instance]
[-new_name new_name]
[-skip_inactive_constraints]
[-dont_touch_collection object_list]

Data Types
name_rules string
names_file string
log_file string
object_list list
instance string or instance object
new_name string

ARGUMENTS
-rules name_rules

Specifies a name rule set that details the rules to which the object names must conform. The name_rules file is defined by using the
define_name_rules command.

By default, this value is the name_rules file specified by the default_name_rules variable.

The tool ignores the -rules option if you specify the -names_file option.

-hierarchy

Modifies all names in the design hierarchy.

By default, the tool changes only objects in the current design.

-verbose

Reports every name change.

By default, the tool provides only a summary of the number of name changes in the design.

-names_file names_file

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Specifies a file of manual name changes. These name changes are not subject to any name rules, but an error is reported if any
name changes are not unique.

By default, the command automatically makes name changes based on the naming rules.

If you specify this option, the tool ignores the -rules option.

-log_changes log_file

Specifies the log file in which to record all name changes.

If you run multiple change_names commands, the log_file must be empty before running the first change_names command.

-restore

Reverses the changes recorded in the names_file during the current session and restores the contents of the file to the state it was
in when opened.

-dont_touch object_list

Specifies the designs on which the change_names command is not to be applied. You can specify any design under the hierarchy
of the current design in the object list to ensure that the change_names command does not apply any changes to them. The dot (.)
character represents the current design.

By default, there are no designs in the list.

-instance instance

Specifies the instance on which to apply the change_names command.

This option must be used with the -new_name option to specify a new instance name.

This option is mutually exclusive with all other options except -new_name and -verbose.

-new_name new_name

Specifies the new instance name when the -instance option is used. The new name must consist of only alphanumeric characters
and the underscore (_) and must start with an alphabetical character. Specify only the instance name, not a hierarchical name. The
new name cannot be a reserved word used by Verilog, SystemVerilog, or VHDL. The new name must not conflict with an existing
instance, port, and net name within the same design. The leading backslash will be removed from the new name.

-skip_inactive_constraints

When you specify this option, the inactive constraints (that are part of the non-current design or part of inactive scenarios) are not
preserved when you use the -instance option with change_names. This option has no impact when you do not specify the -
instance option.

-dont_touch_collection object_list

Specifies the collection on which the change_names command is not to be applied. The collection can include designs, cells,
ports, nets. You can specify a collection in the object list to ensure that the change_names command does not apply any changes
to them.

DESCRIPTION
The change_names command changes the names of ports, cells (including physical-only cells), and nets in a design to conform to
specified name rules.

This command cannot be used to change the name of library cells or bus ports.

To change the name of bus ports, you must first use the remove_bus command to remove the bus property from the port.

If an object name does not conform to the specified rules, the tool changes the name and ensures that the new name is unique within

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the design.

By default, the tool changes the names of bus members to force them to use the same base name as their owning bus. If you do not
want the names of bus members, set the change_names_dont_change_bus_members variable to true before running the
change_names command.

To show the effects of running this command without actually making the changes, use the report_names command.

There are two primary reasons for using the change_names command:

It enables you to modify design object names in the tool so that the names match those that are ultimately created for a saved
design. The names the tool displays in reports and in other information match those used in your target system.

It enables you to define naming rules specific to your target system. For example, you might be using VHDL as a design transfer
mechanism, but the naming rules of your system might be more restrictive than those supported by the true VHDL format.

To obtain a list of available name rules, use the report_name_rules command. For information about naming rules that can be
affected during the execution of the change_names file, see the define_name_rules man page.

When you run the change_names command with no options, it operates on the ports, cells, and nets in the current design. When you
specify the -hierarchy option, changes are expanded to include all design objects within the current design hierarchy.

For runtime reasons, it's best to use the -instance option only when you have a small list of instances to be renamed. If you have a big
list of instances to be renamed, you must use the -rule option with change_names or use the -skip_inactive_constraints option and
apply the constraints after running change_names -instance.

Names File Format

To specify a name change, you must specify the following four fields:

design_name object_type object_name new_name

The design_name field is a design currently read into the tool. The object_type field is port, cell, or net. The object_name field is the
name of an object within the specified design. The new_name field is the name that replaces the existing name.

If the file contains a report bar formed by a dashed line (--------), the tool ignores all information above the report bar. The tool
parses all lines after the report bar (or all lines, if the file does not contain a report bar).

By default, the tool parses each line into four fields, which are separated by whitespace characters, such as blanks, tabs, or new
lines.

This format matches the format of the report_names command output, which allows you to redirect the output of the
report_names command to a file, edit it, and then use it as input to the change_names command.

The tool also supports the use of a semicolon (;) as a delimiter to separate the name change specifications in the file. If you use a
delimiter, you must add the following line above the report bar formed by the dashed line (--------):

use delimiter:true

The following example shows a names file without a delimiter:

****************************************
Report : names
-rules MY_RULES
Design : TOP
Version: v3.0
Date : Tue Aug 13 14:24:23 2007
****************************************

Design Type Object New Name

-------------------------------------------------------------
TOP cell U$1 U_1
TOP net NET_NAME_IS_WAY_TOO_LONG
NET_NAME_IS_WAY_TOO
TOP net 12345 N12345

The following example shows a names file with a delimiter:

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use delimiter:true

Design Type Object New Name

-------------------------------------------------------------
TOP cell U$1 U_1 ;
TOP net NET_NAME_IS_WAY_TOO_LONG
NET_NAME_IS_WAY_TOO ;
TOP net 12345 N12345 ;

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example shows how to change the names in the current design to conform to the rules defined by the
default_name_rules variable:

prompt> list default_name_rules

default_name_rules = "EXAMPLE"

prompt> change_names
Information: Using name rules 'EXAMPLE'.
Information: 4 names changed in design 'TOP'.

The following example shows how to use the -verbose option to show each name changed by the change_names command.

prompt> change_names -verbose

Information: Using name rules 'EXAMPLE'.

Design Type Object New Name

-------------------------------------------------------------
TOP port A1 a_
TOP port A2 a_a
TOP port A3 a_b
TOP port A4 a_c

The following example shows how to use the -hierarchy option to change names throughout the design hierarchy. Typically, you want
to change the names of all designs in the hierarchy to conform to your name rules.

prompt> change_names -hierarchy

Information: Using name rules 'EXAMPLE'.
Information: 12 names changed in design 'HALF_ADDER'.
Information: 35 names changed in design 'SUBTRACTOR'.
Information: No names changed in design 'TOP'.

The following example shows how to use the define_name_rules command to create a set of simple name rules. In this example, the
name rules require that all names use uppercase characters or numerals.

prompt> define_name_rules CAPS_ONLY -allow "A-Z 0-9"

prompt> change_names -rules CAPS_ONLY -verbose

Information: Using name rules 'CAPS_ONLY'.

Design Type Object New Name

-------------------------------------------------------------
MY_BUFFER port a1 A1
MY_BUFFER port a2 A2
MY_BUFFER port b1 B1
MY_BUFFER port b2 B2

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MY_BUFFER cell u1 U1
MY_BUFFER cell u2 U2

The following example shows how to make manual name changes to design objects by using the report_names and change_names
commands. First, redirect a report of all the original design objects to a file and edit the file to make manual changes. Use the edited
names file to direct the name changes made by the change_names command. In this case, the tool ignores the name rules and
makes only the specified changes.

prompt> report_names -original > TOP.names

/* Edit the TOP.names names file */
prompt> change_names -names_file TOP.names
Information: 15 names changed using names file 'TOP.names'

The following example shows how to use the -instance option to change one instance name:

prompt> change_names -instance a1 -new_name a2

The following example shows how to rename a bus port by first removing the bus property and then using the change_names
command to change the name.

prompt> remove_bus -type port -name my_bus

prompt> change_names -names_file name.change -verbose

The following example shows how to specify a dont_touch_collection to avoid name changes on the objects in the collection.

prompt> change_names -rules verilog -hierarchy -verbose -dont_touch_collection [list [get_designs top]]
prompt> change_names -rules verilog -hierarchy -verbose -dont_touch_collection [list [get_nets n*]]
prompt> change_names -rules verilog -hierarchy -verbose -dont_touch_collection [list [get_ports a[0]] [get_nets a[0]]]
prompt> change_names -rules verilog -hierarchy -verbose -dont_touch_collection [list [get_cells a_reg*] [get_ports a[0]] [get_nets a

SEE ALSO
define_name_rules(2)
report_name_rules(2)
report_names(2)
default_name_rules(3)

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change_selection
Changes the selection in the GUI, taking a collection of objects and changing the selection according to the type of change specified.

SYNTAX
status change_selection
[-name slct_bus]
[-replace]
[-add]
[-remove]
[-toggle]
[-type object_type]
collection

Data Types
slct_bus string
object_type list
collection list

ARGUMENTS
-name slct_bus

Specifies to change the selection bus by using the value of slct_bus. By default, the command changes the selection bus by using
the name global.

-replace

Replaces the current selection with the objects in the collection. This is the default behavior when no options are specified.

-add

Adds the objects in the collection to the current selection. By default, this option is off.

-remove

Removes the objects that are specified in the collection from the current selection. By default, this option is off.

-toggle

Adds each item that is specified in the collection to the selection bus if it is not currently contained in the selection bus. If it is
currently contained in the selection bus, it is removed. By default, this option is off.

-type object_type

Specifies the type to change. Only those items from the collection that are of the type specified by object_type are used to change
the selection. The valid values are design, port, net, cell, pin, and path (timing path). By default, the command uses the entire
collection.

collection

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Specifies the collection of objects to use to change the selection. The type of change that is applied to the current selection with the
collection is specified by the options listed above. By default, this option is off.

DESCRIPTION
The change_selection command changes the selection in the GUI. When selections are changed, the GUI updates all relevant
windows to reflect it.

A collection of objects and the type of change are given as input to the command. The collection of objects might be returned as the
result of another command, such as the get_designs command. If the collection is empty and you use the -replace option (or let the
command default by specifying no option), the current selection is cleared.

If you use the -type option, only the type of objects specified are used to change the current selection. For example, if you use -type
design, the command uses only the design objects in the collection to change the current selection. If you do not use the -type option,
all objects in the collection are used to change the current selection. For example, if you use the -add option without using the -type
option, all objects, regardless of their type, are added to the current selection.

For information about collections, see the collections man page.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example replaces the current selection with the collection of design objects, regardless of type:

prompt> change_selection [get_designs]

The following example adds a cell named U5 to the selection made in the example above:

prompt> change_selection -add [get_cells U5]

The following example removes all pin objects from the current selection:

prompt> change_selection -remove -type pin [get_selection]

The following example clears the selection:

prompt> change_selection ""

The following example creates a new selection bus and adds a net named n1 to the selection:

prompt> set slct [create_selection_bus]

prompt> change_selection -name $slct [get_nets 1]

SEE ALSO
collections(2)
filter(2)
filter_collection(2)
get_selection(2)

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query_objects(2)

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characterize
Captures information about the environment of specific cell instances and assigns the information as attributes on the design to which
the cells are linked.

SYNTAX
status characterize
cell_list
[-no_timing]
[-constraints]
[-connections]
[-power]
[-verbose]

Data Types
cell_list list

ARGUMENTS
cell_list

Specifies the cells in the current design whose designs are to be characterized.

-no_timing

Indicates not to characterize the timing characteristics of the design. Attributes representing the timing environment or requirements
are not placed on the subdesigns.

-constraints

Places area, power, connection class, and design rule constraint information on the subdesigns.

-connections

Characterizes the connection attributes of the design.

-power

Uses the switching activity information of the specified cells to annotate the corresponding subdesigns.

-verbose

Echoes the equivalent commands that are applied to the subdesign being characterized.

DESCRIPTION

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The characterize command places on a design the information and attributes that characterize its environment in the context of a
specified instantiation in another design.

The primary purpose of the characterize command is to capture the timing environment of the subdesign. This occurs if the
characterize command is run without the -no_timing option.

The command derives and asserts the following on the design to which the instance is linked:

Unless the -no_timing option is used, the characterize command places on the subdesigns any timing characteristics
previously set by the following commands:

create_clock
group_path
read_sdf
read_clusters
set_annotated_check
set_annotated_delay
set_auto_ideal_net
set_disable_timing
set_drive
set_driving_cell
set_false_path
set_ideal_latency
set_ideal_net
set_ideal_transition
set_input_delay
set_load
set_max_delay
set_min_delay
set_multicycle_path
set_operating_conditions
set_output_delay
set_resistance
set_timing_ranges
set_wire_load_model
set_wire_load_mode
set_wire_load_selection_group
set_wire_load_min_block_size

If the -constraint option is used, the characterize command places on the subdesigns any area, power, connection class, and
design rule constraints previously set by the following commands:

set_cell_degradation
set_connection_class
set_dont_touch_network
set_fanout_load
set_fix_multiple_port_nets
set_ideal_network
set_ideal_net
set_max_area
set_max_capacitance
set_max_fanout
set_max_power
set_max_transition
set_min_capacitance
set_min_porosity

If the -connections option is used, the characterize command places on the subdesigns any connection attributes previously
set by the following commands:

set_equal
set_logic_one
set_logic_zero
set_logic_dc
set_opposite

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set_unconnected

Note that connection class information is applied only if the -constraint option is used.

If the -power option is used, the characterize command places on the subdesigns any switching activity information, toggle
rates, and static probability previously set, calculated, or saved by the following commands:

report_power
set_switching_activity

In most cases, characterizing a design removes the effects of any previous characterization and replaces all relevant
information. However, in the case of back-annotation (the set_load, set_resistance, read_sdf, set_annotated_delay, an
set_annotated_check commands), the annotations are moved during the characterize step, and cannot overwrite existing
annotations made on the subdesign. In this case, annotations must be explicitly removed from the subdesign by using the
reset_design command before running the characterize command the next time.

The characterize command can be used with set_dont_touch to maintain the hierarchy during optimization. This method of
optimization is known as bottom-up optimization. It can be applied using a golden instance or a uniquify approach. An alternative
to bottom-up optimization is top-down optimization, otherwise known as hierarchical compile. In top-down optimization, the tool
performs characterization and optimization of subdesigns automatically.

Multicorner-Multimode Support
This command uses information from the current scenario only.

EXAMPLES
The following example shows the golden instance approach to bottom-up optimization. This is useful when the same design is used in
several places, with a similar environment. The characterize and set_dont_touch commands are used to optimize the subdesign
once and reference that optimized design in several places. The characterization is done using a golden instance (U1 in this case) and
reflects the environment of that instance. Assume that U1 and U2 both reference the design named ADDER and have similar
environments.

Characterize the ADDER design with respect to instance "U1" and compile it:

prompt> current_design TOP

prompt> characterize U1
prompt> current_design ADDER
prompt> compile

Compile the top level while preserving "U1" and "U2":

prompt> current_design TOP

prompt> set_dont_touch {U1 U2}
prompt> compile

The following example shows the uniquify approach to bottom-up optimization. If a design is used in more than one place with
different environments, use the uniquify command to create a design for each instance. You can now characterize the new designs
and optimize each separately.

Uniquify the hierarchy so that all hierarchical cells reference different designs. This creates new design names such as ADDER_1 and
ADDER_2:

prompt> current_design TOP

prompt> uniquify

Characterize the unique designs with respect to their environments, and compile each design:

prompt> characterize {U1 U2}

prompt> current_design ADDER_1
prompt> compile
prompt> current_design ADDER_2

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prompt> compile

Compile the top-level design while preserving U1 and U2:

prompt> current_design TOP

prompt> set_dont_touch {U1 U2}
prompt> compile

The following example shows top-down optimization. In top-down optimization, the tool implicitly performs characterization for each
subdesign.

prompt> current_design TOP

prompt> uniquify
prompt> compile

SEE ALSO
compile(2)
create_clock(2)
current_design(2)
group_path(2)
link(2)
read_sdf(2)
remove_annotated_check(2)
remove_annotated_delay(2)
remove_constraint(2)
reset_design(2)
set_annotated_check(2)
set_annotated_delay(2)
set_cell_degradation(2)
set_connection_class(2)
set_disable_timing(2)
set_dont_touch(2)
set_dont_touch_network(2)
set_drive(2)
set_driving_cell(2)
set_equal(2)
set_false_path(2)
set_fanout_load(2)
set_fix_multiple_port_nets(2)
set_ideal_latency(2)
set_ideal_net(2)
set_ideal_network(2)
set_ideal_transition(2)
set_input_delay(2)
set_load(2)
set_logic_one(2)
set_logic_zero(2)
set_logic_dc(2)
set_min_capacitance(2)
set_max_area(2)
set_max_capacitance(2)
set_max_delay(2)
set_max_fanout(2)
set_max_transition(2)
set_min_delay(2)
set_multicycle_path(2)
set_operating_conditions(2)
set_opposite(2)
set_output_delay(2)

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set_resistance(2)
set_target_library_subset(2)
set_timing_ranges(2)
set_unconnected(2)
set_wire_load_model(2)
set_wire_load_mode(2)
set_wire_load_selection_group(2)
set_wire_load_min_block_size(2)
uniquify(2)

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check_bindings
Checks the bindings in a synthetic library module definition.

SYNTAX
status check_bindings
[-bindings binding_list]
[-pin_widths pin_width_list]
module_name

Data Types
binding_list list
pin_width_list list
module_name string

ARGUMENTS
-bindings binding_list

Lists the bindings of the module to check. The default is to check all bindings.

-pin_widths pin_width_list

Lists the pin width that is checked for the bound_operator. The default is specified by the operator's check_pin_widths attribute.
The -pin_widths option can be used only if all specified bindings bind to the same operator.

module_name

Specifies the name of the synthetic library module whose bindings you want to check. This parameter is required.

DESCRIPTION
The check_bindings command ensures that bindings from a synthetic library module to synthetic library operators are correct.

By default, check_bindings checks every binding of the specified module. The check_bindings command verifies that a binding
implements a particular operator correctly. The binding under test is correct if it generates a design that is functionally the same as the
"golden" binding. All Synopsys operators are associated with thoroughly-tested golden bindings.

To check a binding for a particular operator, that operator must be annotated with a module and binding known to be correct. Do this
using the check_module and check_binding attributes. For example:

operator (ADD_UNS_OP) {
check_module : "add";
check_binding : "b1";
check_pin_widths : "A=1,B=1,Z=1; A=3,B=4,Z=5";

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/* other declaration go here */

}

By default, each binding to an operator is verified for a number of different operator pin widths. The default pin widths are specified by
a check_pin_widths attribute on the operator. The check_pin_widths attribute is a list of pin-width specifications, separated by
semicolons (;). Each pin-width specification is a comma (,) separated list of pin sizes. Pin sizes are specified by a pin name, followed
by an equal sign (=), followed by a pin width.

The preceding example runs one verification for operators with all pins of width 1 and a second verification with the pin A pin of width 3,
pin B of width 4, and pin Z of width 5.

LIMITATIONS
Because check_bindings is based on check_design, it inherits the same limitations. The check_bindings command does not
verify noncombinational parts unless the flip-flop names are identical. The check_bindings command also does not check very
large multipliers because the verification is too expensive.

EXAMPLES
The following example checks the bindings to the SYNTH_ADD module:

prompt> check_bindings SYNTH_ADD

The next example checks binds b1 and b2 for specific pin widths. Note that -pin_widths lists are specified in the list format of
dc_shell, not as a single string (as used in the previous check_pin_widths attribute).

prompt> check_bindings
-binding { b1 b2 }
-pin_widths { "A=2,B=2,Z=2" "A=31,B=31,Z=32" }
SYNTH_ADD

SEE ALSO
check_implementations(2)
synthetic_library(3)

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check_block_abstraction
Checks the readiness of a block abstraction for usage in a top-level design at various stages of the flow.

SYNTAX
status check_block_abstraction

ARGUMENTS
The check_block_abstraction command has no arguments.

DESCRIPTION
The check_block_abstraction command checks the blocks linked to the top-level design to ensure they are ready for the top-level
compile flow. The following general checks are performed:

Scenario consistency in multicorner-multimode blocks.

The existence of dont_touch attribute settings on blocks and cells.

If any error messages are reported by this command, you should resolve them before proceeding further. If any warning messages
are reported by this command, you should review them before proceeding further.

Multicorner-Multimode Support
This command uses information from active scenarios only.

EXAMPLES
The following example checks the blocks in the current design and reports the errors to be resolved:

prompt> check_block_abstraction
Error: No scenario data loaded from block reference 'blk1'. (ILM-151)
Error: dont_touch attribute incorrectly set to false on block design 'blk2'. (ILM-121)
0

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SEE ALSO
create_block_abstraction(2)
set_top_implementation_options(2)
report_block_abstraction(2)

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check_bsd
Checks whether a design's boundary-scan implementation is compliant with IEEE Std 1149.1.

SYNTAX
status check_bsd
[-verbose true | false]
[-infer_instructions true | false]
[-effort low | medium | high]

ARGUMENTS
-verbose true | false

Generates multiple warning or error messages for a set of similar violations during a single step when set to true. By default, a
warning or error message is generated for only the first violating cell or port.

-infer_instructions true | false

Specifies whether check_bsd should analyze the logic to identify the implemented instructions.

When set to false, the tool uses only instruction information that was previously specified with the set_bsd_instruction command.
In the insertion flow, this is provided by set_bsd_instruction -view spec commands for specified instructions and by the tool for
automatically implemented mandatory instructions. In the existing-logic flow, this is provided with the set_bsd_instruction -view
existing_dft command. The check_bsd command reports this as follows:

...Using the implemented instructions information.

When set to true, the tool uses logic analysis to identify the implemented instructions, with an analysis effort optionally specified by
the -effort option. The check_bsd command reports this as follows:

...Inferring the implemented INTEST instruction.

...Inferring the implemented CLAMP instruction.
...Inferring the implemented HIGHZ instruction.
...Inferring the implemented IDCODE & USERCODE instruction.
...Inferring the implemented RUNBIST instruction.

If any instructions have been specified with the set_bsd_instruction command, the default is false. If no instructions have been
specified, the default is true.

When this option is set to true, note the following:

Any instruction information specified with the set_bsd_instruction command is ignored. If you write out a BSDL file,
nonstandard (user-defined) instructions will have USER<n> names and all user-defined test data registers will have UTDR<n>
names.

All unused encodings are assigned to the BYPASS instruction in the BSDL file.

-effort low | medium | high

Controls the effort used to search for implemented instructions when the -infer_instructions option is set to true and the instruction

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register width is 16 or greater. The effort levels are:

low - uses only heuristics

medium - uses heuristics first, then random opcode generation for limited sequential search

high - uses a full sequential search

If the -infer_instructions options is set to true and the instruction register width is less than 16, this option is ignored and a full
sequential search (the high effort level) is used.

Instruction register masking can be used to reduce search runtime. See the DESCRIPTION section for more information.

DESCRIPTION
The check_bsd checks whether the current design's boundary-scan implementation is compliant with IEEE Std 1149.1. You must
specify the Test Access Ports (TMS, TCK, TRST, TDI, and TDO) using the set_dft_signal -view existing command. If violations to
any of the IEEE Std 1149.1 rules are found, the appropriate messages are generated. Check the design for any unresolved references
before using this command. Set system clocks using the set_dft_signal command in order to see correct functionality. Specify any
compliance enable ports using the set_bsd_compliance command.

Fatal error messages indicate that your design violates an IEEE Std 1149.1 rule and the violation is serious enough that the
compliance checker can no longer continue analysis. You cannot use subsequent tools (for example, the BSDL generator) until you
correct the violation.

Error messages indicate that your design violates an IEEE Std 1149.1 rule, but it is still possible to analyze further and gather more
information about the design. However, you cannot use subsequent tools (for example, the BSDL generator) until you correct the
violation.

Warning messages indicate that your design violates an IEEE Std 1149.1 rule, but the violation does not prevent the BSDL generator
from generating BSDL.

When the tool must infer the implemented instructions, you can shorten the sequential search space by masking bits within the IR
instruction opcodes using the following two application variables:

The test_cc_ir_masked_bits variable specifies the IR bits to be masked. The compliance checker masks the IR bits that contain
"1" in the binary equivalent to the decimal integer value assigned to this variable. For details, see the man page for the
test_cc_ir_masked_bits variable.

The test_cc_ir_value_of_masked_bits variable specifies a predefined value to be forced onto the masked IR bits. The decimal
integer value assigned to this variable is converted to binary for the bit width of the IR, and the masked bits are forced with the
corresponding values during the search operation. For details, see the man page for the test_cc_ir_value_of_masked_bits
variable.

The least significant bit of the IR is considered to be the bit closest to the TDO port.

By default, compliance check is done in accordance with the IEEE1149.1-2001 standard version. You can switch back to the
IEEE1149.1-1993 standard version, by setting the -ieee1149.1_1993 option of the set_bsd_configuration command.

For more details about the IEEE Std 1149.1 rules, refer to the EEE Std Test Access Port and Boundary-Scan Architecture.

EXAMPLES
The following command performs compliance checking for the current design, and illustrates the types of messages that are output:

prompt> current_design my_boundary_scan

prompt> set_dft_signal -view existing -port my_tdi -type TDI

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prompt> set_dft_signal -view existing -port my_tdo -type TDO

prompt> set_dft_signal -view existing -port my_tms -type TMS

prompt> set_dft_signal -view existing -port my_trst -type TRST -active_state 0

prompt> set_dft_signal -view existing -port my_tck -type TCK -timing {45 55}

prompt> set_bsd_compliance -name p1 \

-pattern {my_compliance_port, 0}

prompt> set_dft_signal -view spec -port my_system_clock \

-type ScanMasterClock -timing (1 2}

prompt> check_bsd -v true

Loading target library 'lsi_10k'
Loading design 'my_boundary_scan'
...Starting IEEE 1149.1 Compliance Checking.
...Finding set of sequential elements.
...Analyzing TAP and TAP Controller.
......Analyzing TAP.
......Finding the set of TAP controller sequential elements.
......Pruning set of TAP Controller sequential Elements
...Checking the TAP controller initialization.
...Analyzing the TAP controller reset condition.
...Traversing the TAP controller states.
...Inferring TAP controller clock outputs.
...Analyzing TRST port.
Warning: Undriven input port TRST is floating. When undriven,
this port should behave as though it was driven by logic one. (TEST-819)
...Analyzing TMS Port.
Warning: Undriven input port TMS is floating. When undriven,
this port should behave as though it was driven by logic one. (TEST-819)
...Analyzing TCK halt state.
Warning: Undriven input port TDI is floating. When undriven,
this port should behave as though it was driven by logic one. (TEST-819)
...Analyzing the instruction register.
......Finding the set of Shift Elements forming the shift register
......Finding the update flops.
...Analyzing the BYPASS register.
......Finding the set of Shift Elements forming the shift register
......Finding the set of Synchronous Shift Elements forming the shift register
Error: Illegal capture value of BYPASS register. (TEST-881)
...Analyzing the DIR register.
......Finding the set of Shift Elements forming the shift register
...Analyzing the boundary-scan register.
......Finding the set of Shift Elements forming the shift register
......Finding the update flops.
......Finding the BSR cells controlling the design ports.
......Finding the BSR cells sensing the design ports.
......Finding the BSR cells driving the design ports.
...Finding the set of IR decoding pins.
...Analyzing the different signatures at the decoding pins.
...Inferring the different test data registers selected by instructions.
...Checking output conditioning of the implemented instructions.
...Inferring the implemented SAMPLE/PRELOAD instructions.
...Finding the BSR controlling cells PIs.
...Finding the BSR controlling cells POs.
...Finding the BSR non-controlling cells PIs.
...Finding the BSR cells POs.
...Inferring the implemented INTEST instruction.
...Inferring the implemented CLAMP instruction.
...Inferring the implemented HIGHZ instruction.

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...Inferring the implemented IDCODE & USERCODE instruction.

...Inferring the implemented RUNBIST instruction.
...Analyzing the EXTEST instruction.
...Analyzing the BYPASS instruction.
...Analyzing the SAMPLE/PRELOAD instruction.
...Analyzing the INTEST instruction.
...Analyzing the RUNBIST instruction.
...Analyzing the IDCODE and USERCODE instructions.

***************************************************

IEEE 1149.1 Summary

***************************************************
4 state elements found in the TAP controller
5 cells found in the Instruction Register
5 standard instructions found.
11 user defined instructions found.
1 cells in BYPASS register
32 cells in DEVICE ID register
5 cells in boundary-scan register

***************************************************

IEEE 1149.1 Violation Summary

***************************************************
6 Violations found in extraction of TAP Controller
Violates Rules: 3.3.1b 3.6.1b
Violates Rules: 3.3.1b 3.6.1b
Violates Rules: 3.3.1b 3.6.1b
1 Violations found in extraction of BYPASS register
Violates Rules: 9.1.1b

SEE ALSO
set_bsd_compliance(2)
set_dft_signal(2)

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check_budget
Checks that user-specified budgets and fixed delays are consistent with path constraints.

SYNTAX
status check_budget
[-verbose]
[-tolerance tolerance]
[-from object_list]
[-to object_list]
[-no_interblock_logic]
[cell_list]

Data Types

tolerance float
object_list list
cell_list list

ARGUMENTS
-verbose

Shows the path segments that cause violation of timing constraints. By default, only the number of paths that violate timing
constraints are shown.

-tolerance tolerance

Specifies that only paths with a slack greater than tolerance in absolute value are checked and reported. By default, all paths are
checked and reported.

-from object_list

Shows only the paths from the named pins, ports, or endpoints clocked by named clocks. By default, all paths that violate timing
constraints are shown.

-to object_list

Shows only the paths to the named pins, ports, or endpoints clocked by named clocks. By default, all paths that violate timing
constraints are shown.

-no_interblock_logic

Specifies that interblock logic is not to be budgeted. By default, the tool considers interblock logic not fixed.

cell_list

Specifies a list of cells to budget. This option must be set only when the check_budget command is used before the
allocate_budget command.

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DESCRIPTION
The check_budget command checks that the user-specified budgets and fixed delays are consistent with path constraints.
Inconsistencies exist when the sum of user-specified budgets and fixed delays along a path exceed the value of the path constraint. By
default, the report shows only the number of paths that violate the timing constraints. The -verbose option shows details about the
violations. The cell_list option allows you to check user budgets on the specified cells before budget allocation. This option must not be
used after budget allocation.

EXAMPLES
The following example shows a report using only the default values:

prompt> check_budget

****************************************
Check budget
****************************************
Design has 2 violations.
1

The following example shows a report with the verbose option.

prompt> check_budget -verbose

****************************************
Check budget
****************************************

Startpoint: C3/OUT_reg (rising edge-triggered flip-flop clocked by clk)

Endpoint: C3/OUT_reg (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Point Incr Path

-----------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
C3/OUT_reg/CLK (fdmf1i2) 0.00 0.00 r
C3/OUT_reg/Q (fdmf1i2) 0.00 * 0.00 r
C3/OUT_reg/D1 (fdmf1i2) 0.00 0.00 f
data arrival time 0.00

clock clk (rise edge) 500.00 500.00

clock network delay (ideal) 0.00 500.00
clock uncertainty -20.00 480.00
C3/OUT_reg/CLK (fdmf1i2) 0.00 480.00 r
library setup time -504.81 -24.81
data required time -24.81
-----------------------------------------------------------
data required time -24.81
data arrival time 0.00
-----------------------------------------------------------
slack (VIOLATED) -24.81

Startpoint: IN (input port clocked by clk)

Endpoint: C1/rOUT_reg
(rising edge-triggered flip-flop clocked by clk)

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Path Group: clk

Path Type: max

Point Incr Path

-----------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 250.00 250.00 f
C1/IN (D1) 0.00 250.00 f
C1/rOUT_reg/D0 (fdmf1c2) 0.00 250.00 f
data arrival time 250.00

clock clk (rise edge) 500.00 500.00

clock network delay (ideal) 0.00 500.00
clock uncertainty -20.00 480.00
C1/rOUT_reg/CLK (fdmf1c2) 0.00 480.00 r
library setup time -342.00 138.00
data required time 138.00
-----------------------------------------------------------
data required time 138.00
data arrival time -250.00
-----------------------------------------------------------
slack (VIOLATED) -112.00

Design has 2 violations.

1

SEE ALSO
report_path_budget(2)
set_user_budget(2)

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check_design
Checks the current design for consistency.

SYNTAX
status check_design
[-summary]
[-no_warnings]
[-one_level]
[-multiple_designs]
[-no_connection_class]
[-nosplit]
[-unmapped]
[-cells]
[-ports]
[-designs]
[-nets]
[-tristates]
[error-ids]
[-html_file_name html_file]

ARGUMENTS
-summary

Displays a summary of the warning messages instead of one message per warning. This does not affect the way error messages
are issued.

-no_warnings

Suppresses warning messages, so only error messages are printed.

-one_level

Performs checks at only the current level of hierarchy. By default, check_design checks the current level and all designs below the
current level.

-multiple_designs

Reports warning messages related to multiply-instantiated designs. With this option, the tool lists all multiply-instantiated designs
along with instance names and associated attributes, such as dont_touch, black_box, and ungroup. By default, these messages
are suppressed.

-no_connection_class

Suppresses connection class warning messages. This switch is useful while working on GTECH designs and netlists on which
connection class violations are expected. By default, these messages are reported.

-nosplit

Prevents lines from being split when column fields overflow. Most of the design information is listed in fixed-width columns. If the

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information for a given field exceeds the column width, the next field begins on a new line in the correct column.

-unmapped

Reports warning messages for unmapped cells when the cells are being checked. By default, these messages are suppressed.

-cells

Reports the following warning messages for cells: LINT-0, LINT-1, LINT-10, LINT-32, LINT-33, LINT-58, LINT-59, LINT-60, and
LINT-61 (if the -unmapped option is used).

-ports

Reports the following warning messages for ports: LINT-5, LINT-6, LINT-8, LINT-28, LINT-29, LINT-31, and LINT-52.

-designs

Reports the following warning messages for designs: LINT-25, LINT-46, and LINT-55.

-nets

Reports the following warning messages for nets: LINT-2, LINT-3, LINT-4, LINT-35, LINT-38, LINT-47, and LINT-54.

-tristates

Reports the following warning messages for tristates: LINT-34 and LINT-63.

error-ids

Reports warning messages for specified error IDs, such as LINT-2.

-html_file_name html_file

Generates a report for the check_design command in HTML format. By default, the check_design command writes reports in
standard output. The -html_file_name option redirects the output to a specified HTML file.

DESCRIPTION
The check_design command checks the internal representation of the current design for consistency, and issues error and warning
messages as appropriate.

Error messages indicate design problems of such severity that the compile command does not accept the design; for example,
recursive hierarchy in a design (when a design references itself) is an error. Warning messages are informational and do not
necessarily indicate design problems. However, these messages should be investigated.

The check_design command flags multiple instances of a design within a system. If a design is instantiated in two different designs,
a warning message is issued. For information on how to respond to error messages dealing with multiple instances, see the uniquify
command man page.

The check_design -summary command automatically runs on every design that is compiled. However, you can use the
check_design command explicitly to see warning messages.

Potential problems detected by this command include unloaded input ports or undriven output ports, nets without loads or drivers or
with multiple drivers, cells or designs without inputs or outputs, mismatched pin counts between an instance and its reference, tristate
buses with non-tristate drivers, wire loops (timing loops with no cells in them) across hierarchies, and so forth.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

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EXAMPLES
The following command checks the current design for problems and issues error and warning messages:

prompt> check_design

The following command checks only the current level of the design:

prompt> check_design -one_level

SEE ALSO
check_library(2)
check_timing(2)
compile(2)
current_design(2)
set_boundary_optimization(2)
set_dont_touch(2)
uniquify(2)
check_design_allow_non_tri_drivers_on_tri_bus(3)
check_design_check_for_wire_loop(3)

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check_error
Reports extended information on message IDs from the last command.

SYNTAX
status check_error
[-verbose]
[-reset]

ARGUMENTS
-verbose

Displays the list of message IDs found during previous commands.

By default, the command only returns the error status.

-reset

Resets the list of previously found message IDs. After resetting the error list, the check_error -verbose command returns an empty
list.

By default, the command does not modify the message list.

DESCRIPTION
The check_error command is used to compare error, warning, or informational messages issued by previous commands to the list of
message IDs specified by the check_error_list variable. While it is most commonly used for error messages, the variable may contain
error, warning, or informational message IDs.

If the check_error command finds message IDs that are specified in the check_error_list variable, the command returns 1. If the
check_error command does not find any messages that are specified by the check_error_list variable, the command returns 0.

Messages that are suppressed by the suppress_message command are reported by check_error. If you want suppressed
messages to be ignored by check_error then you must remove their message IDs from the check_error_list variable.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES

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The following example shows how to use the check_error command to check if execution errors are specified by the
check_error_list variable:

prompt> printvar check_error_list

check_error_list = "UID-3 UID-4 EQN-18 EQN-19"

prompt> check_error
0

prompt> link
Error: Current design is not defined. (UID-4)
0

prompt> check_error
1

prompt> check_error -verbose

{UID-4}
1

The following command resets the error list:

prompt> check_error -reset -verbose

{UID-4}
1

prompt> check_error -verbose

0

To use the check_error command in a script to see if specified errors occurred in the previous commands, use the following
command:

prompt> if { [check_error] } {
echo failure_message
exit
} else {
echo success_message
}

SEE ALSO
check_error_list(3)
suppress_message(2)

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check_implementations
Checks the implementations in a synthetic library module definition.

SYNTAX
status check_implementations
[-implementations implementation_list]
[-parameters parameter_list]
module_name

Data Types
implementation_list list
parameter_list list
module_name string

ARGUMENTS
-implementations implementation_list

Lists the implementations of the module to check. The default is all implementations.

-parameters parameter_list

Lists the module parameters to use when checking. The default is to use the parameters specified by the check_params attribute
of the module.

module_name

Specifies the name of the synthetic library module whose implementations you want to check. This argument is required.

DESCRIPTION
The check_implementations command ensures that when you add a new implementation to an existing module, the new
implementation works in the same manner as the old implementation.

Check implementations are provided by Synopsys for all Synopsys modules. They are never used to implement hardware, only for
verification.

module (mod1) {
/* Other declarations go here */
check_implementation(check_add) {
}
/* other implementations go here */
}

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By default, every implementation of a module is compared to the verify implementation. For parameterized modules, a verification is
performed for each of the check_params that is specified for the module.

The check_params attribute is a list of parameter specifications, separated by semicolons (;), which specifies a test to be run. Each
parameter specification is a comma (,) separated list of parameter names, followed by an equal sign (=), followed by a value. For
example, the specification below runs one verification with n=2 and m=3, and a second verification with n=5 and m=8 for each
implementation:

<examplelast>
check_params : "n=2,m=3; n=5,m=8" ;
<body>

check_implementations -impl {rpl cla}add

LIMITATIONS
Because check_implementations is based on check_design, it inherits the same limitations. The check_implementations
command does not verify noncombinational parts unless the flip-flop names are identical. The check_implementations command
also does not check very large multipliers because the verification is too expensive.

EXAMPLES
The following example checks all implementations of the SYNTH_ADD module:

prompt> check_implementations SYNTH_ADD

This example checks the ripple and carry-lookahead implementations for parameter values of 33 and 63:

prompt> check_implementations -impl { rpl_add cla_add } \

-param { "n=33" "n=63" } SYNTH_ADD

SEE ALSO
check_bindings(2)
synthetic_library(3)

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check_library
Performs consistency checks between logic and physical libraries, across logic libraries, and within physical libraries.

SYNTAX
status check_library
[-logic_library_name logic_library_name_list]
[-mw_library_name phys_library_name_list]
[-physical_library_name phys_library_name_list]
[-cells cell_list]

Data Types
logic_library_name_list list
phys_library_name_list list
cell_list list

ARGUMENTS
-logic_library_name logic_library_name_list

Specifies the logic libraries (.db) to be checked. Other types of libraries such as .ILM are not supported.

For logic versus logic library checking, specify two or more libraries, such as the minimum and maximum libraries. If you have set
the -compare or -validate options of the set_check_library_options command, specify only two libraries.

If you do not specify this option, the command determines the logic libraries in the following order:

The minimum and maximum libraries that were set with the set_min_library command.

If you have set the -scaling option of the set_check_library_options command, the scaling libraries that were set with the
define_scaling_lib_group command.

The link libraries that were set with the link_library and search_path variables.
For logic versus logic library checking, the command first groups the link libraries by cell set, and within each group or family
the command checks consistencies across all libraries in the same group. The grouping is by majority (> 50%) of same name
cells. For example, if lib1 has 9 cells and lib2 has 6, and 5 of them are the same, then they are grouped together.

This option is ignored for physical library checking.

-mw_library_name phys_library_name_list

Specifies Milkyway reference libraries to be checked.

If you do not specify this option, the command uses the reference libraries from the open Milkyway design library. If there is no
open Milkyway design library, the command uses the reference libraries specified in the mw_reference_library variable.

-physical_library_name phys_library_name_list

Specifies NDM based physical libraries (.frame) to be checked. You can specify multiple physical libraries. For cross checking,
specify both logic and physical libraries. If libraries are not specified explicitly in check_library, the ones loaded/opened at runtime

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will be used. The libraries to be checked are in the following priority:

1) explicitly specified in check_library command

2) logic libraries associated with the specified physical library

3) loaded or opened logic and physical libraries at runtime -mw_library_name and -physical_library_name cannot be specified
together.

-cells cell_list

Specifies a list of cell names to be checked. If not specified, all cells in the libraries are checked.

DESCRIPTION
The check_library command checks and reports the items described below, based on the settings of the set_check_library_options
command.

If you do not run the set_check_library_options command and do not specify any options with the check_library command, the
check_library command checks logic versus physical library consistency for the libraries that are set up for the current design. If there
are no libraries set up for the current design, the command does not perform any checks.

During logic library checking, to report the delay, power, and noise characterization values in the libraries, the Liberty-format
description of the libraries must have the library_features attribute set to the respective values: report_delay_calculation,
report_power_calculation, and report_noise_calculation.

Use the check_library command to verify the libraries before reading in a design.

This command checks library qualities in three main areas:

Physical library quality

Logic versus physical library consistency

Logic versus logic library consistency

All of the checking functions are available in Design Compiler and the functions of logic versus logic library checking are also available
in Library Compiler.

Physical Library Quality Checking

Physical library qualities are checked as follows:

Technology data consistency between the specified main library and each linked reference library

CEL view versus FRAM view in the library for missing views and mismatched views

Cells with identical names in different reference libraries and the specified main library

Signal electromigration rules

Antenna rules and missing antenna properties

Rectilinear cells

Physical-only cells

Physical properties for place and route including unit tiles for the libraries

Pin routability

Technology data quality

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DRC for each cell in the library

Logic Versus Physical Library Consistency Checking

The command performs the following consistency checks between logic and physical libraries:

Missing cells in the logic or physical library

If you specify multiple logic libraries and no cells are found in any of the libraries that match the physical library, the cells are
counted as missing in the logic library unless they are physical-only cells. Otherwise, if the cells are found in any of the logic
libraries, such as the first library, they are counted as consistent in cell names.

Missing or mismatched pins (pin names, directions, and types) in the logic and physical library.
Note that the input pin direction keyword in a logic cell versus the Input keyword in a physical cell is not a mismatch.

Area values of each standard cell between the logic (.lib or .db) model and FRAM view (PRBoundary and CellBoundary)

Cell footprint (cell_footprint attribute)

Bus character naming style in logic and physical libraries.

By default, missing cells and pins and mismatched pins are checked.

For logic versus physical library checking, at the end of checking the command reports a cross-check summary that includes the
following information:

Number of cells missing in the logic library (excluding physical-only cells)

Number of cells missing in the physical library

Number of cells with missing or mismatched pins in libraries, if any

The logic versus physical library quality checking PASSED or the logic library is INCONSISTENT with the physical library

Logic Versus Logic Library Consistency Checking

Logic versus logic library consistency checks include:

General checking at library, cell, pin, and timing group levels for missing cells, missing and mismatched pins or pg_pins, and
timing arcs.

Special checking for timing, noise, and power scaling

Special checking for the UPF or multivoltage flow, such as pg_pins, power management cells, and power data

Special checking for the multicorner-multimode flow, such as operating conditions and power-down functions

Library characterization and validation

For logic versus logic library checking, at the end of checking the command reports a summary for each specified option. For
example, for the -mcmm option, it reports:

Logic library consistency check FAILED for MCMM.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
In the following example, the lib1.db and lib2.db logic libraries are checked against the phys_lib physical libraries for missing cells and
pins, mismatched pins, the cell footprint, and the bus delimiter:

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prompt> set_check_library_options -cell_footprint -bus_delimiter

1

prompt> check_library -mw_library_name {phys_lib} \

-logic_library_name {lib1.db lib2.db}

#BEGIN_XCHECK_LIBRARY

Logic Library: lib1

lib2
Physical Library: phys_lib
check_library options: -cell_footprint -bus_delimiter
Version: E-2010.12
Check date and time: Tue Sep 28 20:34:26 2010

List of logic library and file names

--------------------------------------------------------------------
Logic library name Logic library file name
--------------------------------------------------------------------
lib1 /usr/lib/lib1.db
lib2 /usr/lib/lib2.db
--------------------------------------------------------------------

#BEGIN_XCHECK_LOGICCELLS

Number of cells missing in logic library: 3 (out of 3348)

Information: List of cells missing in logic library (LIBCHK-210)

--------------------------------------------------------------------
Cell name Cell type Physical library
--------------------------------------------------------------------
AND2 Core phys_lib
NOR1 Core phys_lib
XOR3 Core phys_lib
--------------------------------------------------------------------

List of physical only cells

--------------------------------------------------------------------
Cell name Cell type Physical library
--------------------------------------------------------------------
GFILL Filler phys_lib
GFILL10 Filler phys_lib
FILL8 Filler phys_lib
--------------------------------------------------------------------

#END_XCHECK_LOGICCELLS

#BEGIN_XCHECK_PHYSICALCELLS

Number of cells missing in physical library: 0 (out of 846)

#END_XCHECK_PHYSICALCELLS

#BEGIN_XCHECK_PINS

Number of cells with missing or mismatched pins in libraries: 1

Error: List of pins mismatched in logic and physical libraries (LIBCHK-213)

Logic library: lib1
Physical library: phys_lib
-------------------------------------------------------------------
Pin direction Pin type
Cell name Pin name Logic Physical Logic Physical

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-------------------------------------------------------------------
pnl123 VSSO output Output signal ground
SGND input Input signal ground
-------------------------------------------------------------------

#END_XCHECK_PINS

#BEGIN_XCHECK_BUS

Information: List of bus naming styles (LIBCHK-214)

-----------------------------------------------------------------
Library name Library type Bus naming style
-----------------------------------------------------------------
phys_lib Physical library _<%d>
lib1 Logic library
-----------------------------------------------------------------

#END_XCHECK_BUS

#BEGIN_XCHECK_FOOTPRINT

Number of footprints: 1

Warning: List of cells with cell_footprint attribute (LIBCHK-215)

-------------------------------------------------------------------
Footprint Logic library name Cell name PR boundary
-------------------------------------------------------------------
TIEH lib1 GTIEH (0,0)(0.8,1.8)
lib1 TIEH (0,0)(0.6,1.8)
-------------------------------------------------------------------

#END_XCHECK_FOOTPRINT

Logic vs. physical library check summary:

Number of cells missing in logic library: 3
Number of cells with missing or mismatched pins in libraries: 1
Information: Logic library is INCONSISTENT with physical library. (LIBCHK-220)

#END_XCHECK_LIBRARY

SEE ALSO
open_mw_lib(2)
report_check_library_options(2)
set_check_library_options(2)
link_library(3)
mw_reference_library(3)

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check_license
Checks the availability of a license for a feature.

SYNTAX
status check_license
feature_list

Data Types
feature_list list

ARGUMENTS
feature_list

Specifies the list of features to be checked. If more than one feature is specified, they must be enclosed in curly braces ({}). By
looking at your key file, you can determine all of the features licensed at your site.

DESCRIPTION
The check_license command checks on a license for the named features. It does not check out the license.

The list_licenses command provides a list of the features that you are currently using.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
This example checks on the license for the multivoltage feature:

prompt> check_license {Galaxy-MV}

SEE ALSO

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get_license(2)
license_users(2)
list_licenses(2)
remove_license(2)

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check_mv_design
Checks for violations in a multivoltage design.

SYNTAX
status check_mv_design
[-verbose]
[-isolation]
[-target_library_subset]
[-opcond_mismatches]
[-connection_rules]
[-level_shifters]
[-power_nets]
[-clock_gating_style]
[-objects object_name_list]
[-models]
[-max_messages message_count]
[-output output_file_name]

Data Types
message_count unsigned integer
output_file_name string

ARGUMENTS
-verbose

Reports the violations in detail. When this option is not used, only a summary of the violations is reported in the log file.

-isolation

Reports electrical isolation issues:

Nets that require isolation, but the isolation cell is missing

Nets that do not require isolation, but an isolation cell is present

Isolation cells that do not cross a power domain boundary

-target_library_subset

Checks for inconsistent settings between the target library, target library subset, and operating conditions. This option reports the
following conditions:

Conflicts between the target library subset and the global target_library variable setting. The target library subset must be a
subset of the library set specified by the target_library variable.

Conflicts between the operating condition and target library subset. There must be at the least one library from the target
library subset that has the same process, voltage, and temperature as the operating condition being used on a block.

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Conflicts between a cell and the target library subset specification on the parent design of the cell. This check ensures that the
cells from the specified target library subset are used.

-opcond_mismatches

Reports the technology cells instantiated in the design with incompatible operating conditions. The option checks for conflicts
between a cell and the operating condition specified on the parent design of the cell. This check ensures that the operating condition
at which the cell is characterized matches the operating condition specified on the design.

-connection_rules

Reports violations in the always-on synthesis and pass-gate connections:

Always-on net driven by a normal cell

Always-on net or a net from an always-on domain driving a pass gate

Always-on cell driving a normal net

Two pass gates connected to each other

-level_shifters

Reports level shifter violations:

Net requiring level-shifting with no level-shifter cell

Net on which a level-shifter cell cannot be added because either the net is marked as dont_touch or the net is driven by a pin
operating at a different voltage

Level-shifter cell shifting an incorrect voltage difference

Input pin of a level-shifter cell driven by a pin operating at a different voltage

Output pin of a level-shifter cell driving pins operating at a different voltage

Level-shifter cell that violates level-shifter strategy settings

-power_nets

Reports power and ground pin connections, including the following information:

PG pin mismatch between the logical library and FRAM library

Power and ground connection summary

Power and ground pins whose connections cannot be derived and the reason that the derivation fails

Power and ground pins whose existing connections do not match with the derived connection from the power domains.

A mismatch between an existing PG connection and the connection derived from the power domains can occur for any of the
following reasons:

"Unknown power pin type" indicates either the power pin does not have a type or the pin has a type without connection
semantics. Automatic power connection supports the following power pin types: primary_power_pin, primary_ground_pin,
backup_power_pin, backup_ground_pin, internal_power_pin, and internal_ground_pin.

"Invalid pin type for the cell or the cell's power domain" indicates that the cell's power domain does not have a power net
connection with the matching type for the power pin type. For example, this situation occurs when a regular cell has a backup
ground pin, but the cell's power domain does not have a backup ground net connection.

"No signal pin that uses this PG pin as the related_power_pin/related_ground_pin." This issue occurs only on level-shifter and
isolation cells. The power connection of a power pin on a level-shifter or isolation cell is obtained through tracing cells
connected to related signal pins of the power pin. The power connection fails if a power pin has no related signal pin, for
example, when no signal pin uses the power pin as the related_power_pin or related_ground_pin in the logical library cell
definition.

"Cells connected to the related signal pins of the level shifter or isolation cell requiring different PG nets." This issue occurs

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only on level-shifter and isolation cells. The tool cannot derive a proper power net for a specific pin because different nets are
needed for the same pin, based on cells connected to the related signal pins.

"Back-to-back connection of level-shifter and isolation cell" occurs when a level-shifter or isolation cell is directly connected to
another level-shifter or isolation cell. The automatic connection of a power pin on such level-shifter or isolation cells might fail
if the tracing of related signal connections reaches only other level-shifter or isolation cells.

This option also reports bias pin connections, when a supply net and its connected supply nets through supply ports or power
switches are used as the power/nwell/deepnwell net, and also as the ground/pwell/deeppwell net.

-clock_gating_style

Reports hierarchical blocks for which there is no library cell that meets its operating condition and specified clock-gating style.
Clock-gate insertion cannot be performed.

-objects object_name_list

This option takes a list of pins, or ports as input. It checks level shifting and isoltion violations on the paths through the given pins.
The option must be specified with one of -level_shifter and -isolation, or both, and it is an error to specify-objects with the options
other than -level_shifter, -isolation, or -verbose. The same violation will not be reported more than once.

-models

Reports any modeling errors found in the available library models.

-max_messages message_count

Sets a maximum limit on the number of messages written into the log file and output file.

-output output_file_name

Writes the output of the check_mv_design command to a file specified by the file name argument. If a file of the specified name
already exists, it is over-written.

This file can be opened in the MV Advisor browser in the Design Vision GUI. Alternatively, the same file can be opened in an
HTML browser by using the absolute path of the file.

The output file contains the details of all violations reported, even when the -verbose option is not used.

DESCRIPTION
The check_mv_design command checks the design, multivoltage constraints, electrical isolation requirements, and connection rules.
It issues error and warning messages as appropriate.

The checker options can be combined to adjust the level of detail in the final report. If the command is used without any checker
options, it reports only a summary of all violations found.

If the -verbose option is used, the command reports details of all violations in the log file. The -max_messages option limits the
number of violations reported. When other checker options are specified, the message count specified by the -max_messages option
applies to each type of check performed. If no specific checker is specified, the message count applies to the total number of
messages generated by all types of checks performed. If -max_messages is not specified, the command writes out all messages
without limit.

Multicorner-Multimode Support
This command uses information from the current scenario only.

EXAMPLES

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The following command reports all multivoltage violations in the design:

prompt> check_mv_design -verbose

------------------------------------------------------------------------
Target Library Subset Checks
------------------------------------------------------------------------

No Errors/Warnings Found.

------------------------------------------------------------------------
Power Domain Checks
------------------------------------------------------------------------

Warning: Isolation cell is required on net A_INST/OUTPUT connecting

A_INST and B_INST. (MV-042)

Warning: Isolation cell is required on net B_INST/OUTPUT connecting

B_INST and top. (MV-042)

Warning: Isolation cell A_INST/iso1 is used to isolate a net that is

not crossing power domain boundary. (MV-044)

------------------------------------------------------------------------
Power Domain Checks Summary
------------------------------------------------------------------------

Warning: Found 2 net(s) without isolation. (MV-046)

Warning: Found 1 isolation cell(s) on net(s) not crossing power

domain boundaries. (MV-048)

------------------------------------------------------------------------
Cell Operating Condition Checks
------------------------------------------------------------------------

No Errors/Warnings Found.

------------------------------------------------------------------------
Power Domain and Operating Condition Consistency Checks
------------------------------------------------------------------------

No Errors/Warnings Found.

The following command generates a summary of all violations in the design:

prompt> check_mv_design

------------------------------------------------------------------------
Target Library Subset Checks
------------------------------------------------------------------------

No Errors/Warnings Found.

------------------------------------------------------------------------
Power Domain Checks
------------------------------------------------------------------------

Warning: Found 2 net(s) without isolation. (MV-046)

Warning: Found 1 isolation cell(s) on net(s) not crossing power domain

boundaries. (MV-048)

------------------------------------------------------------------------
Cell Operating Condition Checks

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------------------------------------------------------------------------

No Errors/Warnings Found.

------------------------------------------------------------------------
Power Domain and Operating Condition Consistency Checks
------------------------------------------------------------------------

No Errors/Warnings Found.

The following example reports violations related to electrical isolation:

prompt> check_mv_design -verbose -isolation

------------------------------------------------------------------------
Power Domain Checks
------------------------------------------------------------------------

Warning: Isolation cell is required on net A_INST/OUTPUT connecting

A_INST and B_INST. (MV-042)

Warning: Isolation cell is required on net B_INST/OUTPUT connecting

B_INST and top. (MV-042)

Warning: Isolation cell A_INST/iso1 is used to isolate a net that is not

crossing power domain boundary. (MV-044)

------------------------------------------------------------------------
Power Domain Checks Summary
------------------------------------------------------------------------

Warning: Found 2 net(s) without isolation. (MV-046)

Warning: Found 1 isolation cell(s) on net(s) not crossing power domain

boundaries. (MV-048)

The following example reports violations related to power nets:

prompt> check_mv_design -verbose -power_nets

--------------------------------------------------------------------------------
Power/Ground Pin Connection Checks
--------------------------------------------------------------------------------
Error: Supply net sn1 and its connected supply net(s) are used as both
power/nwell/deepnwell net and ground/pwell/deepnwell net. (MV-601)

Error: Supply net sn2 and its connected supply net(s) are used as both
power/nwell/deepnwell net and ground/pwell/deepnwell net. (MV-601)

Error: Power net hookup for power domains is not specified properly (MV-503)
--------------------------------------------------------------------------------

The following example shows how to use the -output option of the check_mv_design command.

prompt> check_mv_design -verbose -output my_file.cmvd

SEE ALSO
check_library(2)
compile_ultra(2)

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remove_target_library_subset(2)
set_operating_conditions(2)
set_target_library_subset(2)

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check_rp_groups
Checks the relative placement constraints and reports any failures.

SYNTAX
collection check_rp_groups
{rp_groups | -all}
[-output filename]
[-verbose]
[-critical]

Data Types
rp_groups list or collection
filename string

ARGUMENTS
rp_groups

Specifies the relative placement groups that will be checked for failures. This option and the -all option are mutually exclusive.

-all

Specifies that all relative placement groups will be checked. This option and the rp_groups argument are mutually exclusive.

-output filename

Specifies the name of the output file for the report.

If you do not specify this option, the report is written to the standard output.

-verbose

Reports relative placement cell orientation failures that are not reported otherwise. It also returns more detailed alignment and
utilization failure messages that include the exact location details of the failures.

DESCRIPTION
The check_rp_groups command checks any violations of relative placement constraints for the specified relative placement groups.
The violations include failing to place the specified relative placement groups and the placed relative placement groups not meeting
relative placement constraints.

The command returns a collection containing the relative placement groups that are checked. If no groups are checked, an empty
string is returned.

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Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following examples use check_rp_groups to check for relative placement failures:

prompt> get_rp_groups
{compare::g1 compare::g2 compare::g4 compare::g7}

prompt> check_rp_groups -all -out failures

{compare::g7 compare::g4 compare::g2 compare::g1}

prompt> check_rp_groups compare::g4 -out g4_failures

{compare::g4}

prompt> check_rp_groups compare::g4

********************************************
Report: The relative placement groups not meeting all constraints but placed.
Version: B-2008.09
Date: Mon Sep 11 04:44:34 2008
Number of relative placement groups: 1
********************************************

relative placement GROUP: compare::g4

---------------------------------------
Warning: Possible placement failure of relative placement group 'compare::g4'
(RPGP-027)
{compare::g4}

prompt> check_rp_groups compare::g1

****************************************
Report: The relative placement groups that could not be placed.
Version: B-2008.09
Date: Mon Sep 11 04:47:25 2008
Number of relative placement groups: 1
****************************************

relative placement GROUP: compare::g1

---------------------------------------
Warning: Possible placement failure of relative placement group 'compare::g1'
(RPGP-027)
{compare::g14}

SEE ALSO
add_to_rp_group(2)
create_rp_group(2)
remove_rp_groups(2)

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check_scan_def
Performs scan chain structural consistency checking based either on the scan chain information stored as an attribute in the current
.ddc file, or an ASCII SCANDEF file.

SYNTAX
status check_scan_def
[-file file_name]

Data Types
file_name string

ARGUMENTS
-file file_name

Specifies an optional SCANDEF file containing scan chain information to be used for checking.

If this option is not specified, the command looks for the SCANDEF information stored in the current design database.

DESCRIPTION
The check_scan_def command performs a scan chain structural checking based on the scan chain information stored in the current
.ddc input file. If the scan chain passes all structural checks, the scan chain status will be "VALIDATED" (V). If the scan chain fails a
structural check, the scan chain status will be "FAILED" (F).

If the -file option is not used, the write_scan_def command must first be issued to annotate the SCANDEF information to the current
design database; otherwise this command issues an error message. See the write_scan_def man page for more information.

This command is used in the Design Compiler environment. In the IC Compiler environment, use the check_scan_chain command
instead.

This command does not support scan chain validation against SCANDEF files written with the write_scan_def -expand command.
When the -expand option is used, scan chain elements inside black-box CTL models are included in the SCANDEF file. This is
needed when moving to IC Compiler, where the CTL models are replaced by the actual subdesigns. If the check_scan_def command
used with such an expanded SCANDEF file, the report shows FAILED for all scan chains that have elements in black box subdesigns.

EXAMPLES
The following is an example of the output of the check_scan_def command when no file is specified:

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prompt> check_scan_def
Checking SCANDEF...
Checking scan cell correspondence between SCANDEF and netlist...
Checking scan chain checking...
All checks completed.

****************************************

Report : Scan DEF check

Design : design name
Version: software version
Date : current date

****************************************

Information from SCANDEF file:

Number of SCANCHAINS: 2

Checking between SCANDEF file and design:

Total SCANCHAINS checked: 2
VALIDATED : 2
FAILED : 0

Chain name Status #cells Scan IN Scan OUT

---------- ------ ------ ------- --------
1 V 62 U10/C alu1/U381/A
2 V 61 U11/C U9/B

The following example shows the result when a file is specified with the check_scan_def command:

prompt> check_scan_def -file temp.def

Reading DEF file temp.def
Checking SCANDEF...
Checking scan cell correspondence between SCANDEF and netlist...
Checking scan chain checking...
All checks completed.

****************************************

Report : Scan DEF check

Design : design name
Version: software version
Date : current date

****************************************

Information from SCANDEF file:

Number of SCANCHAINS: 2

Checking between SCANDEF file and design:

Total SCANCHAINS checked: 2
VALIDATED : 2
FAILED : 0

Chain name Status #cells Scan IN Scan OUT

---------- ------ ------ ------- --------
1 V 62 U10/C alu1/U381/A
2 V 61 U11/C U9/B

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SEE ALSO
report_scan_chain(2)
write_scan_def(2)

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check_scenarios
Performs consistency checks between the scenarios, for scenario specific information such as TLUplus files, operating conditions on
the libraries, clocks and so on.

SYNTAX
status check_scenarios
[-output ]
[-display]

ARGUMENTS
-output

Specifies the directory to store the output. By default output is stored in HTML format in the directory,
design_dir/check_scenarios_mmddyyyy_pid

-display

Opens a HTML browser to display the data. The browser to be used is defined by the Tcl variable, gui_online_browser.

DESCRIPTION
The check_scenarios command checks and reports issues with the scenarios. The command performs the following checks:
TLUplus, clock related information such as clock periods, default versus nominal PVT on libraries, PVT from blocks versus parent, and
PVT of library cells.

Multicorner-Multimode Support
This command uses information from all active scenarios. This command also supports designs that are not multicorner-multimode
designs.

EXAMPLES
The following is an example of the check_scenarios command:

prompt> check_scenarios
check_scenarios
Warning: The complexity of the scenario (s1) might cause long runtime and high
memory usage. (MCMM-212)
Warning: Scenario (s1) has instances which referenced library cells that are

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marked as "dont_use". (MCMM-225)

Warning: Scenario (s2) has a library setup issue with regard to the PVT values
and the operating condition. (MCMM-213)
Information: HTML report can be found at
/WORKING_DIRECTORY/run/check_scenarios_7132009_21451/check_scenarios_0.html

SEE ALSO
gui_online_browser(3)

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check_synlib
Performs semantic checks on synthetic libraries.

SYNTAX
status check_synlib

ARGUMENTS
This command has no arguments.

DESCRIPTION
The check_synlib command performs checking on synthetic libraries found in the synthetic library search path (synthetic_library)
and listed by the link_library variable. Synthetic libraries can contain errors that cannot be detected using the read_lib command.
Note that check_synlib also implicitly checks against standard.sldb.

The check_synlib command returns one of the following two values:

0 : Errors were reported.

1 : No critical errors were found.

Run check_synlib after you set the synthetic_library variable and the .sldb files exist, but before commands such as compile or
replace_synthetic use any of these libraries.

EXAMPLES
The following example checks the synthetic libraries named in the synthetic_library variable for compatibility. The two libraries are
my_synlib_0.sldb and my_synlib_1.sldb.

prompt> synthetic_library = {"my_synlib_0.sldb", "my_synlib_1.sldb"}

prompt> check_synlib

SEE ALSO

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compile(2)
read_lib(2)
replace_synthetic(2)
report_synlib(2)
synthetic_library(3)

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check_target_library_subset
Checks and prints out the inconsistent settings among target library, target library subset, and operating conditions.

SYNTAX
status check_target_library_subset
[-verbose]
[-max_messages int]

ARGUMENTS
The check_target_library_subset command has no arguments.

DESCRIPTION
This command checks and prints out the inconsistent settings among target library, target library subset, and operating conditions.
The command checks for the following:

Conflicts between the target library subset and the global target_library variable. The target library subset should be a subset of
the library set being specified by the target_library variable.

Conflicts between operating condition and target library subset. There should be at least one library from the target library subset
that has the same process, nom_voltage, and temperature as the operating condition being used on that block.

Conflicts between the library cell of the mapped cell and target library subset. A warning is issued if the library cell of a mapped
cell is not from any of the libraries of the target library subset. Note that this is not an error, because the subset applies only to
new cells being created during optimization, not to existing cells in the block.

Multicorner-Multimode Support

Depending on the options used, this command either uses the current scenario or has no dependency on scenario-specific
information.

SEE ALSO
check_library(2)
compile(2)
remove_target_library_subset(2)
report_target_library_subset(2)
set_operating_conditions(2)
set_target_library_subset(2)

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target_library(3)

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check_timing
Checks for possible timing problems in the current design.

SYNTAX
status check_timing
[-overlap_tolerance minimum_distance]
[-override_defaults check_list]
[-multiple_clock]
[-sdc_runtime]
[-retain]
[-include check_list]
[-exclude check_list]

Data Types
minimum_distance float
check_list list

ARGUMENTS
-overlap_tolerance minimum_distance

Specifies the minimum distance allowed between the master-close edge and the slave-open edge. If the distance is less than the -
overlap_tolerance value, the tool issues a warning message. Use this option to check for the master-slave clock overlap. By
default, this option is off.

-override_defaults check_list

Overrides the checks defined by the timing_check_defaults variable by using the check_list argument. If you use the -
override_defaults option with a check_list, you need to perform the final list of checks with the check_list argument of the -
override_defaults option.

-multiple_clock

Issues a warning when multiple clocks reach a register clock pin. If more than one clock signal reaches a register clock pin, and the
timing_enable_multiple_clocks_per_reg variable is set to false, the clock to use for analysis is undefined, and the tool issues a
warning message. In this case, use either the set_case_analysis or set_disable_timing command so that only one clock can
propagate from the sources to the register clock pin. By default, this option is off.

-sdc_runtime

Issues a report on the dirty constraints set on the design, which can contribute to high runtime. The default file name is
sdc_runtime.log. Use the sdc_runtime_analysis_log_file variable to generate report with a different log file name. You can also
generate this report by setting the sdc_runtime_analysis_enable variable to true and compile the design. When you use the -
sdc_runtime option, the tool ignores all other options of the check timing command and generates only the SDC dirty constraint
report. These checks are not influenced by the timing_check_defaults variable. By default, this option is off.

-retain

Issues a warning if any of the RETAIN values are larger than its corresponding delay value. The RETAIN values should be less

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than their corresponding delay values so that they can be considered for hold violations. Otherwise, the RETAIN values might be
considered for setup violations. By default, this option is off.

-include check_list

Adds the checks listed in check_list to the checks defined by the timing_check_defaults variable.

-exclude check_list

Subtracts the checks listed in check_list from the checks defined by the timing_check_defaults variable.

DESCRIPTION
This command checks the timing attributes placed on the current design and issues warning messages as needed. The warning
messages provide information that identifies and corrects potential errors. The warning messages do not necessarily indicate design
problems.

This command without any options performs the checks defined by the timing_check_defaults variable. Redefine this variable to
change the value. If the -override_defaults option is not used, the final list of checks to be performed is the list of checks specified by
the timing_check_defaults variable, plus the list of checks specified by the -include option, minus the list of checks specified by the -
exclude option. If you use the -override_defaults option with a check_list, you need to perform the final list of checks with the
check_list argument of the -override_defaults option.

The alphabetically ordered list below shows the meaning of each check:

clock_crossing

Checks clock interactions when there are multiple clock domains. If a clock launches one or more paths that are captured by other
clocks, it will have an entry in the clock crossing report. If all paths between two clocks are false paths or they are exclusive or
asynchronous clocks, the path is marked with an asterisk (*). If only some of the paths are set as false paths, the path is marked by
a number sign (#).

clock_no_period

Warns if clocks with no period are specified.

data_check_multiple_clock

Warns if multiple clocked signals reach a data check register reference pin. The analysis is done separately for each of the clocked
domains. If the timing_enable_multiple_clock_per_reg variable is set to false, only one of the clocked signals is analyzed.

data_check_no_clock

Warns if no clocked signal reaches a data check register reference pin. In this case, no setup or hold checks are performed on the
constrained pin.

gated_clock

Warns about the gated clocks. Disables the gating timing arcs only if the propagated_clock attribute is set on that clock.

generated_clock

Checks the generated clock network. The following types of issues are reported:

The source pin (master point) is not the clock source.

The definition point of the generated clock has no path to the sourcepoint.

The generated clocks form a loop.

generic

Warns about generic (unmapped) cells in the design. The timing of paths through generic cells is inaccurate, because the generic

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cells have zero delay.

ideal_clocks

Warns about any clock networks that are ideal. Generally, all clocks should be propagated so that the clock network timing is
accurately calculated. Especially in the presence of crosstalk, the delay changes induced by other nets on the clock network are
not reflected in the calculated slacks in the design.

ideal_timing

Warns when the user-defined ideal transition or latency is set on a normal pin (not ideal).

loops

Warns about combinational feedback loops. If the feedback loop is not broken by the set_disable_timing command, it is
automatically broken by disabling one or more timing arcs.

multiple_clock

This item should be specified with the -multiple_clock option.

net_no_driving_info

Warns about any net that does not have driving pins or that there are no timing arcs on the driver pins. The warning is issued only
when the net has coupled parasitic.

no_driving_cell

Warns about any port that does not have a driving cell. The warning is issued only when the net connected to the port has parasitic.
When no driving cell is specified, the net is assigned to a strong driver for modeling aggressor effects, which can be pessimistic.
Also, a port with no driving cell could act as a strong victim, which could underestimate the crosstalk effect.

no_input_delay

Warns if no clock-related delay is specified on an input port, where it propagates to a clocked latch or output port. If the
timing_input_port_default_clock variable is set to true, a default clock is assumed for the input port. Otherwise, it will not be
clocked, and the paths are unconstrained. In this case, if there is no input delay specified, the check_timing command does not
generate warnings.

partial_input_delay

Warns about any ports have partially defined input delay; only the minimum or only the maximum delay defined with the
set_input_delay command. As a result, some paths starting from the port with partially defined input delay might become
unconstrained and some potential violations could be missed.

pulse_clock_cell_type

Warns if an instance cell has a mismatched pulse type defined from its library cell.

retain

This check item should also be specified by the -retain option.

unconstrained_endpoints

Warns about unconstrained timing endpoints. This warning identifies timing endpoints that are not constrained for maximum delay
(setup) checks. If the paths to the endpoint are all false paths, endpoints are not reported as unconstrained endpoints.

The warning messages that can occur when you use this command are described below.

The following warning message is issued when the waveforms applied to a master-slave register are overlapping or have
different periods. Use the create_clock command to modify one of the waveforms.

The overlap check first determines the intended master-slave waveform relationships based on the ideal clock waveforms. Then,
the clock network delay and uncertainty is applied to the waveforms and if the distance between the related edges is less than
the overlap tolerance, the tool issues a warning message.

WARNING: The following master-slave registers have overlapping clock violations. The waveforms or periods might be

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invalid.

The following warning message identifies timing endpoints (output ports and register data pins) that are not constrained. If the
endpoint is a register data pin, use the create_clock command for the appropriate clock source to constrain the pin. Use the
set_output_delay or set_max_delay command to constrain output ports. The set_output_delay command constrains only the
path when the delay is relative to a clock.

WARNING: The following endpoints are not constrained for maximum delay.

The following warning message identifies gated clocks. Disable the gating timing arcs only if the propagated_clock attribute is
set on that clock.

WARNING: The clock network starting at "clk" is gated by the following input pins. The gating timing arcs might need to be
disabled for clocks with the "propagated_clock" attribute.

The following warning message is issued when the design contains unmapped cells (generic logic), which causes the timing of
the paths through the generic cells to be inaccurate because generic cells have zero delay.

WARNING: Design "design_name" contains unmapped cells.

Multicorner-Multimode Support
This command uses information from the current scenario only.

EXAMPLES
The following example checks the timing of the current design and issues warning messages as needed:

prompt> check_timing
Information: Checking 'unexpandable_clocks'...
Information: Checking 'generic'...
Information: Checking 'latch_fanout'...
Information: Checking 'loops'...
Information: Checking 'generated_clocks'...

SEE ALSO
check_design(2)
check_library(2)
compile(2)
compile_ultra(2)
create_clock(2)
current_design(2)
set_case_analysis(2)
set_disable_timing(2)
set_max_delay(2)
set_output_delay(2)
timing_enable_multiple_clocks_per_reg(3)

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check_tlu_plus_files
Checks the files used for TLUPlus extraction.

SYNTAX
status check_tlu_plus_files

ARGUMENTS
This command has no arguments.

DESCRIPTION
The check_tlu_plus_files command performs consistency checks on the TLUPlus files used for virtual route and postroute extraction,
which are specified by using the set_tlu_plus_files command. If the TLUPlus files are from a Milkyway design library attachment, this
command does not do any checking because the attachment was already checked when it was attached.

The following items are checked for consistency:

Layer names
The consistency check ensures that the conductor and via layer names are consistent across the Milkyway, ITF, and mapping
files. The tool also checks that the number of layers are consistent between the ITF files and the Milkyway technology files. The
tool issues error messages if there are inconsistencies.

Etch values
The tool checks that the etch values in the ITF files are consistent with the delta width values in the Milkyway technology files
under minimum, nominal, and maximum conditions. The signs used to indicate expand and shrink are opposite in the ITF files
and the Milkyway technology files. The tool issues warning messages if there are inconsistencies.

Minimum width and minimum spacing

The tool checks that the minimum width and minimum spacing are consistent between the ITF files and the Milkyway technology
files, and among different minimum, nominal, and maximum ITF files. The tool issues warning messages if there are
inconsistencies.

Conductor thickness
The tool checks that the conductor thicknesses are consistent between the ITF files and the Milkyway technology files. The tool
issues warning messages if there are inconsistencies.

Multicorner-Multimode Support
This command uses information from all scenarios.

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EXAMPLES
The following example runs the consistency checks:

prompt> check_tlu_plus_files

SEE ALSO
check_library(2)
set_tlu_plus_files(2)

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check_upf
Checks the UPF loaded on a hierarchical design for validity of references across the abstract boundary between the top level and the
block level.

SYNTAX
status check_upf

ARGUMENTS
This command has no arguments.

DESCRIPTION
In hierarchical flow designs, the save_upf command saves only the UPF constraints that apply to the top-level design. This command
tests the UPF loaded into the current design for any reference that crosses the boundary between the top level and the block level, and
generates a warning for each UPF command or argument that will be dropped when the save_upf command is used.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
prompt> check_upf
Warning: The following elements have been dropped from a UPF statement: mid/block (UPF-701)
Warning: UPF statement 'set_isolation' will be dropped because its scope belongs to an
abstract hierarchy. (UPF-702)
0

SEE ALSO
load_upf(2)
save_upf(2)

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clean_buffer_tree
Removes the buffer tree at the specified driver pin, load pin, or driver net on a mapped design.

SYNTAX
status clean_buffer_tree
[-from start_point_list]
[-to object_list]
[-net net_list]
[-source_of object_list]
[-hierarchy]
[-global]
[-threshold integer_in_1]

Data Types
start_point_list list
object_list list
net_list list
integer_in_1 integer

ARGUMENTS
-from start_point_list

Specifies the starting point of the buffer tree to be removed. The start_point_list must contain only pins or ports. This option can be
used in conjunction with the -to and -net options.

-to object_list

The buffer tree removal starts at the immediate buffer source of the specified pins or ports. The object_list must contain only pins or
ports. This option can be used in conjunction with the -from and -net options.

-net net_list

Specifies the driver net that is the starting point for the buffer tree to be removed. The net_list must contain only nets. This option
can be used in conjunction with the -from and -to options.

-source_of object_list

The complete buffer tree in the fanin to the object up to the object itself is removed. The object_list must contain only output ports or
input pins. This option cannot be used in conjunction with the -from, -to or -net options.

-hierarchy

Removes the buffer tree across the hierarchy. By default, the buffer tree removal stops when it reaches the hierarchy boundary.

-global

Searches for high-fanout buffer tree root pins in the net_list. This option is not valid with the -from, -to, and -net options.

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-threshold integer_in_1

Specifies the fanout threshold range that determines which buffer trees are cleaned up. If the number of sink pins driven from the
primary root pin of the buffer tree is larger than the threshold, the buffer tree circuitry is cleaned up. This option is only valid with the
-global option.

Valid -threshold values are from 1 to 1,000,000.

DESCRIPTION
The clean_buffer_tree command removes a buffer tree at a specified driver pin, load pin, or driver net on a mapped design. When
given a driver pin or driver net, the buffer tree is removed with this driver as the root. When given a load pin, the buffer tree is removed
with the immediate driver of the load pin as the root. By default, this command does not remove the buffer tree across the hierarchy. To
enable buffer tree removal across boundaries, specify the -hierarchy option when running the command.

The buffer tree removal process starts at the source and removes all buffer and inverter cells in its transitive fanout cone until it finds
nonbuffer cells or hierarchy boundaries. This does not apply if the -hierarchy option is specified.

Buffer and inverter cells that have the dont_touch attribute or that are connected to a net that has the dont_touch attribute are not
removed. Similarly, any cells that follow these cells in the transitive fanout are not removed.

The clean_buffer_tree command adds an inverter driving all of the original buffer tree's inverted loads after it has removed all buffers
and inverters in the tree.

This command accepts the final implementation of buffer tree removal, even if it negatively impacts the timing or DRC violations in the
design.

EXAMPLES
The following example removes a buffer tree without crossing hierarchical boundaries:

prompt> clean_buffer_tree -from cell1/O

The following example removes a buffer tree that crosses hierarchical boundaries:

prompt> clean_buffer_tree -hierarchy -from cell1/O

SEE ALSO
all_fanout(2)
balance_buffer(2)
report_buffer_tree(2)
report_cell(2)
report_constraint(2)

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close_lib
Decrements the open count of a library. A library is removed from memory when its open count is zero.

SYNTAX
status close_lib
[-save_designs]
[-force]
[-purge]
[-all]
[-compress]
[library]

Data Types

library collection

ARGUMENTS
-save_designs

Saves any designs in the design library that are open and modified but not yet saved. If the design library contains a technology
section that has been modified, it is also saved.

When you use this option, the modified designs and technology section are saved regardless of whether the design library is
removed from memory.

This option is not supported in the library manager.

-force

Removes the library from memory, even if its technology section or some of its designs have been modified but not saved (and you
did not use the -save_designs option).

-purge

Removes the library from memory, regardless of its open count.

-all

Removes all libraries from memory, regardless of their open counts.

-compress

To be used with "-save_designs" to save libraries in compressed format. This option is applicable to design library only. It is error to
use this option without -save_designs.

library

Specifies the library to close. This can either be a name or a collection of a single library.

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By default, the command closes the current library.

DESCRIPTION
This command decrements the open count of the specified library. The command closes the library and removes it from memory when
at least one of the following conditions is satisfied:

The open count is zero.

The -purge option is used.

The -force option is used.

If you try to remove a library from memory that is on the reference library list of another open design library, the tool issues an error
message and does not remove the library from memory.

In the library manager, you can use this command to remove a library from an aggregate library workspace.

This command in supported in Design Compiler NXT topographical mode.

EXAMPLES
The following example removes the current design library from memory after saving saving any open and modified-but-not-saved
designs.

prompt> close_lib -purge -save_designs

1

The following example saves the open and modified-but-not-saved designs in all open design libraries and then removes the design
libraries from memory.

prompt> close_lib -all -save_designs

1

SEE ALSO
create_lib(2)
open_lib(2)
save_lib(2)
copy_lib(2)
move_lib(2)
current_lib(2)
get_libs(2)
set_ref_libs(2)
search_path(3)
shell_is_in_ndm_mode(2)

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close_mw_lib
Closes the current Milkyway library.

SYNTAX
status close_mw_lib

ARGUMENTS
The close_mw_lib command has no arguments.

DESCRIPTION
This command closes the current Milkyway library. It returns a status indicating success or failure.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example closes the current Milkyway library:

prompt> close_mw_lib
1

SEE ALSO
open_mw_lib(2)

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collections
Describes the methodology for creating collections of objects and querying objects in the database.

DESCRIPTION
Synopsys applications build an internal database of objects and attributes applied to them. These databases consist of several classes
of objects, including designs, libraries, ports, cells, nets, pins, clocks, and so on. Most commands operate on these objects.

By definition:

A collection is a group of objects exported to the Tcl user interface.

Collections have an internal representation (the objects) and, sometimes, a string representation. The string representation is
generally used only for error messages.

Collections represent an ordered sequence of database objects. These collections provide constant time random access to the
objects contained in the sequence.

A set of commands to create and manipulate collections is provided as an integral part of the user interface. The collection commands
encompass two categories: those that create collections of objects for use by another command, and one that queries objects for
viewing. The result of a command that creates a collection is a Tcl object that can be passed along to another command. For a query
command, although the visible output looks like a list of objects (a list of object names is displayed), the result is an empty string.

An empty string "" is equivalent to the empty collection, that is, a collection with zero elements.

To illustrate the usage of the common collection commands, the man pages have examples. Most of the examples use PrimeTime as
the application. In all cases, the application from which the example is derived is indicated.

Homogeneous and Heterogeneous Collections

A homogeneous collection contains only one type of object. A heterogeneous collection can contain more than one type of object.
Commands that accept collections as arguments can accept either type of collection.

Lifetime of a Collection
Collections are active only as long as they are referenced. Typically, a collection is referenced when a variable is set to the result of
a command that creates it or when it is passed as an argument to a command or a procedure. For example, in PrimeTime, you can
save a collection of design ports by setting a variable to the result of the get_ports command:

pt_shell> set ports [get_ports *]

Next, either of the following two commands deletes the collection referenced by the ports variable:

pt_shell> unset ports

pt_shell> set ports "value"

Collections can be implicitly deleted when they go out of scope. Collections go out of scope for various reasons. An example would
be when the parent (or other antecedent) of the objects within the collection is deleted. For example, if our collection of ports is
owned by a design, it is implicitly deleted when the design that owns the ports is deleted. When a collection is implicitly deleted, the
variable that referenced the collection still holds a string representation of the collection. However, this value is useless because the
collection is gone, as illustrated in the following PrimeTime example:

pt_shell> current_design
{"TOP"}

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pt_shell> set ports [get_ports in*]

{"in0", "in1"}

pt_shell> remove_design TOP

Removing design 'TOP'...

pt_shell> query_objects $ports

Error: No such collection '_sel26' (SEL-001)

Iteration
To iterate over the objects in a collection, use the foreach_in_collection command. You cannot use the Tcl-supplied foreach
iterator to iterate over the objects in a collection, because the foreach command requires a list, and a collection is not a list. In fact,
if you use the foreach command on a collection, it destroys the collection.

The arguments of the foreach_in_collection command are similar to those of foreach: an iterator variable, the collection over
which to iterate, and the script to apply at each iteration. Note that unlike the foreach command, the foreach_in_collection
command does not accept a list of iterator variables.

The following example is an iterative way to perform a query in PrimeTime. For more information, see the foreach_in_collection
man page.

pt_shell> \
foreach_in_collection s1 $collection {
echo [get_object_name $s1]
}

Manipulating Collections
A variety of commands are provided to manipulate collections. In some cases, a particular command might not operate on a
collection of a specific type. This is application-specific. Consult the man pages from your application.

add_to_collection - This command creates a new collection by adding a list of element names or collections to a base
collection. The base collection can be the empty collection. The result is a new collection. In addition, the add_to_collection
command allows you to remove duplicate objects from the collection by using the -unique option.

append_to_collection - This command appends a set of objects (specified by name or collection) to an existing collection.
The base collection is passed in through a variable name, and the base collection is modified directly. It is similar in function to
the add_to_collection command, except that it modifies the collection in place; therefore, it is much faster than the
add_to_collection command when appending.

remove_from_collection - This command removes a list of element names or collections from an existing collection. The
second argument is the specification of the objects to remove and the first argument is the collection to have them removed
from. The result of the command is a new collection. For example, in PrimeTime:

pt_shell> set dports \

[remove_from_collection [all_inputs] CLK]
{"in1", "in2", "in3"}

compare_collections - This command verifies that two collections contain the same objects (optionally, in the same order).
The result is "0" on success.

copy_collection - This command creates a new collection containing the same objects in the same order as a given
collection. Not all collections can be copied.

index_collection - This command extracts a single object from a collection and creates a new collection containing that
object. The index operation is done in constant time - it is independent of the number of elements in the collection, or the
specific index. Not all collections can be indexed.

sizeof_collection - This command returns the number of objects in a collection.

Filtering
In some applications, you can filter any collection by using the filter_collection command. This command takes a base collection
and creates a new collection that includes only those objects that match an expression.

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Some applications provide a -filter option for their commands that create collections. This allows objects to be filtered out before
they are ever included in the collection. Frequently this is more efficient than filtering after the they are included in the collection.
The following examples from PrimeTime filters out all leaf cells:

pt_shell> filter_collection \
[get_cells *] "is_hierarchical == true"]
{"i1", "i2"}
pt_shell> get_cells * -filter "is_hierarchical == true"
{"i1", "i2"}

The basic form of a filter expression is a series of relations joined together with AND and OR operators. Parentheses are also
supported. The basic relation contrasts an attribute name with a value through a relational operator. In the previous example,
is_hierarchical is the attribute, == is the relational operator, and true is the value.

The relational operators are

== Equal
!= Not equal
> Greater than
< Less than
>= Greater than or equal to
<= Less than or equal to
=~ Matches pattern
!~ Does not match pattern

The basic relational rules are

String attributes can be compared with any operator.

Numeric attributes cannot be compared with pattern match operators.

Boolean attributes can be compared only with == and !=. The value can be only true or false.

Additionally, existence relations determine if an attribute is defined or not defined, for the object. For example,

(sense == setup_clk_rise) and defined(sdf_cond)

The existence operators are

defined
undefined

These operators apply to any attribute as long as it is valid for the object class. See the appropriate man pages for complete details.

Sorting Collections
In some applications, you can sort a collection by using the sort_collection command. It takes a base collection and a list of
attributes as sort keys. The result is a copy of the base collection sorted by the given keys. Sorting is ascending, by default, or
descending when you specify the -descending option. In the following example from PrimeTime, the command sorts the ports by
direction and then by full name.

pt_shell> sort_collection [get_ports *] \

{direction full_name}
{"in1", "in2", "out1", "out2"}

Implicit Query of Collections

In many applications, commands that create collections implicitly query the collection when the command is used at the command
line. Consider the following examples from PrimeTime:

pt_shell> set_input_delay 3.0 [get_ports in*]

1
pt_shell> get_ports in*
{"in0", "in1", "in2"}
pt_shell> query_objects -verbose [get_ports in*]
{"port:in0", "port:in1", "port:in2"}

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pt_shell> set iports [get_ports in*]

{"in0", "in1", "in2"}

In the first example, the get_ports command creates a collection of ports that is passed to the set_input_delay command. This
collection is not the result of the primary command (set_input_delay), and as soon as the primary command completes, the
collection is destroyed. The second example shows how a command that creates a collection automatically queries the collection
when that command is used as a primary command. The third example shows the verbose feature of the query_objects command,
which is not available with an implicit query. Finally, the fourth example sets the variable iports to the result of the get_ports
command. Only in the final example does the collection persist to future commands until iports is overwritten, unset, or goes out of
scope.

SEE ALSO
add_to_collection(2)
as_collection(2)
append_to_collection(2)
compare_collections(2)
copy_collection(2)
filter_collection(2)
foreach_in_collection(2)
index_collection(2)
query_objects(2)
remove_from_collection(2)
sizeof_collection(2)
sort_collection(2)

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compare_collections
Compares the contents of two collections. If the same objects are in both collections, the result is "0" (like string compare). If they are
different, the result is nonzero. The order of the objects can optionally be considered.

SYNTAX
int compare_collections
[-order_dependent]
collection1
collection2

Data Types
collection1 collection
collection2 collection

ARGUMENTS
-order_dependent

Indicates that the order of the objects is to be considered; that is, the collections are considered to be different if the objects are
ordered differently.

collection1

Specifies the base collection for the comparison. The empty string (the empty collection) is a legal value for the collection1
argument.

collection2

Specifies the collection with which to compare to collection1. The empty string (the empty collection) is a legal value for the
collection2 argument.

DESCRIPTION
The compare_collections command is used to compare the contents of two collections. By default, the order of the objects does not
matter, so that a collection of cells u1 and u2 is the same as a collection of the cells u2 and u1. By using the -order_dependent option,
the order of the objects is considered.

Either or both of the collections can be the empty string (the empty collection). If two empty collections are compared, the comparison
succeeds (that is, compare_collections considers them identical), and the result is "0".

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EXAMPLES
The following example from PrimeTime shows a variety of comparisons. Note that a result of "0" from compare_collections indicates
success. Any other result indicates failure.

prompt> compare_collections [get_cells *] [get_cells *]

0
prompt> set c1 [get_cells {u1 u2}]
{u1 u2}
prompt> set c2 [get_cells {u2 u1}]
{u2 u1}
prompt> set c3 [get_cells {u2 u4 u6}]
{u2 u4 u6}
prompt> compare_collections $c1 $c2
0
prompt> compare_collections $c1 $c2 -order_dependent
-1
prompt> compare_collections $c1 $c3
-1

The following example builds on the previous example by showing how empty collections are compared.

prompt> set c4 ""

prompt> compare_collections $c1 $c4
-1
prompt> compare_collections $c4 $c4
0

SEE ALSO
collections(2)

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compare_delay_calculation
Compares the Arnoldi-based delays with the Elmore delays in the current design.

SYNTAX
status compare_delay_calculation
[-verbose]
[-ccs]

ARGUMENTS
-verbose

Creates histogram-style reports showing the distribution of the delay differences when using the Arnoldi-based and Elmore delay
models.

-ccs

Creates histogram-style reports showing the delay differences when using Composite Current Source (CCS) models and nonlinear
delay models (NLDM).

DESCRIPTION
The compare_delay_calculation command calculates and compares the timing results of the current design using the Arnoldi-based
and Elmore delay models. This command reports pin-to-pin delays, max transition, several DRC violations and the worst slack within
each path group for both delay models. In the verbose mode this command creates histogram-style reports showing the distribution of
the Arnoldi-based and Elmore delay differences on the paths with negative slacks. The distribution of the differences is represented by
the two histograms showing the delay differences in the library units and in the percentage.

Multicorner-Multimode Support

This command uses information from the current scenario only.

EXAMPLES
The following is an example of an Arnoldi-based and Elmore delay calculation report:

prompt> compare_delay_calculation -verbose

Percent of Arnoldi-based delays = 66.67%

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+====================+=======================+=======================+
| | Elmore | Arnoldi |
|--------------------|-----------------------|-----------------------|
|Max Transition | 0.195 | 0.521 |
|DRC Violations | 1 | 1 |
|--------------------|-----------+-----------|-----------+-----------|
|Group | WNS | TNS | WNS | TNS |
|--------------------|-----------|-----------|-----------|-----------|
|CLK1 | 1.71 | 3.96 | 1.46 | 2.64 |
|default | 0.00 | 0.00 | 0.00 | 0.00 |
+--------------------+-----------+-----------+-----------+-----------+

Histograms for Delays with Negative Slack

+======================+=====================+=====================+
|Difference (%) | Count | % |
|----------------------|---------------------|---------------------|
|0 -1 | 2 | 8.33 |
|1 -5 | 5 | 20.83 |
| 5 - 10 | 3 | 12.50 |
| 10 - 50 | 10 | 41.67 |
| 50 - 100 | 4 | 16.67 |
| 100+ | 0 | 0.00 |
+======================+=====================+=====================+
|Difference(lib_units) | Count | % |
|----------------------+---------------------+---------------------|
| 0.0 - 0.001 | 0 | 0.00 |
| 0.001- 0.01 | 3 | 12.50 |
| 0.01 - 0.05 | 7 | 29.17 |
| 0.05 - 0.1 | 0 | 0.00 |
| 0.1 - 1.0 | 14 | 58.33 |
| 1.0+ | 0 | 0.00 |
+----------------------+---------------------+---------------------+

Histograms for Slews with Negative Slack

+======================+=====================+=====================+
|Difference (%) | Count | % |
|----------------------|---------------------|---------------------|
|0 -1 | 0 | 0.00 |
|1 -5 | 8 | 33.33 |
| 5 - 10 | 9 | 37.50 |
| 10 - 50 | 3 | 12.50 |
| 50 - 100 | 4 | 16.67 |
| 100+ | 0 | 0.00 |
+======================+=====================+=====================+
|Difference(lib_units) | Count | % |
|----------------------+---------------------+---------------------|
| 0.0 - 0.001 | 0 | 0.00 |
| 0.001- 0.01 | 12 | 50.00 |
| 0.01 - 0.05 | 0 | 0.00 |
| 0.05 - 0.1 | 0 | 0.00 |
| 0.1 - 1.0 | 12 | 50.00 |
| 1.0+ | 0 | 0.00 |
+----------------------+---------------------+---------------------+

SEE ALSO
read_parasitics(2)
report_delay_calculation(2)

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report_timing(2)

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compare_lib
Performs a cross-reference check between a technology library and a symbol library or between a technology library and a physical
library.

SYNTAX
status compare_lib
library1
library2

Data Types
library1 string
library2 string

ARGUMENTS
library1

Specifies the name of a technology library.

library2

Specifies the name of a symbol library or physical library to be compared with the technology library.

DESCRIPTION
The compare_lib command compares the specified libraries consistency. The first library is a technology library and the second
library is a symbol or physical library. For this command to run successfully, the libraries to be compared must be in the Synopsys
internal database format and must also exist in memory. To compile a library, use the read_lib command. To load a compiled library,
use the read_file command.

The compare_lib command performs the following checks:

First, it ensures that each component in the technology library has a corresponding definition in the symbol or physical library.

Second, it crosschecks the pin names of each component in the technology library against the pin names defined for its
corresponding symbol or physical representation.

Third, it ensures that each component in the symbol or physical library has a corresponding definition in the technology library.

Fourth, it crosschecks the pin names of each component in the symbol or physical library against the pin names defined for its
corresponding technology cell.

Multicorner-Multimode Support

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This command has no dependency on scenario-specific information.

EXAMPLES
The following example compares a technology library and a symbol library:

prompt> compare_lib tech_lib.db sym_lib.sdb

SEE ALSO
read_file(2)
read_lib(2)
report_lib(2)
write_lib(2)

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compare_supplies
compares voltage levels or relative ON-ness between two given supplies.

SYNTAX
status compare_supplies
supply_list
[-on_status]
[-voltage_level]

Data Types
supply_list list

ARGUMENTS
supply_list

Specifies a list of 2 supplies. The first supply specified is treated as the 'reference' supply to which the second supply ('specified'
supply) will be compared to. Supplies can either be supply net names or supply set handles.

-on_status

If specified, this option will return one of 4 values: "equal" if the reference supply is equal to the specified supply. "more_on" if the
specified supply is more ON as compared to the reference supply. "less_on" if the specified supply is less ON as compared to the
reference supply. "independent" if the specified supply may be more or less ON as compared to the reference supply depending on
the PST State.

-voltage_level

If specified, this option will return one of 4 values: "equal", if both reference and specified supplies are at the same voltage and no
level-shifting is needed. "higher", if reference supply is lower voltage as compared to the specified supply. "lower", if the reference
supply is higher voltage as compared to the specified supply. "independent, if the reference supply is higher/lower voltage as
compared to the specified supply depending on the PST State. If the two supplies specified belong to the same correlated supply
group, they will be compared based on the rules for supplies in the same correlated supply group.

DESCRIPTION
This command is used to compare voltage levels or relative always-ON levels of two given supplies. Options -on_status and -
voltage_level can be used separately or in combination. Supplies list must consist of exactly 2 supplies.

SEE ALSO
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report_pst(2)

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compile
Performs logic-level and gate-level synthesis and optimization on the current design.

SYNTAX
status compile
[-no_map]
[-map_effort medium | high]
[-area_effort none | low | medium | high]
[-incremental_mapping]
[-exact_map]
[-ungroup_all]
[-boundary_optimization]
[-auto_ungroup area | delay]
[-no_design_rule
| -only_design_rule
| -only_hold_time]
[-scan]
[-top]
[-power_effort none | low | medium | high]
[-gate_clock]

ARGUMENTS
-no_map

Specifies not to map the current design into the target technology library. With this option, generic Boolean equations and generic
flip-flops represent the resulting design.

-map_effort medium | high

Specifies the relative amount of CPU time spent during the mapping phase of compile. Valid values are medium and high. You
can select one value. The default is medium.

-area_effort none | low | medium | high

Specifies the relative amount of CPU time spent during the area recovery phase of compile. Valid values are none, low, medium,
and high. You can select one value. The default is the specified map_effort.

-incremental_mapping

Specifies to attempt only incremental improvements to the gate structure of a design. Portions of a design that are already mapped
are exempt from logic-level optimization, and the resulting design should be the same (if no improvements can be made) or better
in terms of its design constraints. Implementations for DesignWare operators are reselected in an incremental compile run if the
swap can improve the optimization cost based on the optimization constraints on the design.

-exact_map

Specifies that the sequential elements in the final design must exactly match the descriptions specified in the HDL description.
SEQGEN is a technology-independent representation of a sequential element that is inferred by HDL Compiler from HDL
descriptions of sequential circuits. When you specify this option, the tool attempts to find sequential elements in the target

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technology library that match the behavior of only the SEQGEN element (that is, no surrounding logic is considered). In the event
that an exact match for a SEQGEN is not available, a different sequential element is used. Use of the -exact_map option would
disable sequential output inversion. For more information, see compile_seqmap_enable_output_inversion. For improved
sequential inference, use this option in conjunction with the HDL directives sync_set_reset, sync_set_reset_local, and
sync_set_reset_all. The new attributes or directives tell HDL Compiler how to connect nets to the SEQGEN component. Use of the
attributes and directives with the -exact_map option ensures that the results of compile are predictable. Use of the -exact_map
option does not mean the QN pin won't be used in the mapped sequential element.

-ungroup_all

Collapses all levels of hierarchy in a design, except those that have the dont_touch attribute set.

-boundary_optimization

Optimizes across all hierarchical boundaries in the design. This can change the function of the design so that it can operate only in
its current environment. If input or output ports are complemented as a result of using this option, port names are changed
according to the port_complement_naming_style variable.

-auto_ungroup area | delay

Specifies to automatically ungroup hierarchies in the design. A hierarchy is considered for automatic ungrouping only if it satisfies all
of the following criteria:

It does not have the dont_touch or ungroup attribute set on it.

There are no timing constraints or exceptions set on its pins.

Its wire load model is the same as that of its parent, or the compile_auto_ungroup_override_wlm variable is set to true.

It has fewer child cells than the value of the compile_auto_ungroup_area_num_cells variable if you select area.

If you select area, all hierarchies that meet the above criteria are ungrouped. The -auto_ungroup area option is generally used to
ungroup small hierarchies in the design to improve area recovery. It does not have a significant impact on the timing of the design.

The -auto_ungroup delay option employs an intelligent ungrouping strategy that attempts to improve the overall timing of the
design. It chooses hierarchies that are most likely to benefit from the extra boundary optimizations that ungrouping exposes. The
algorithm emphasizes hierarchies containing paths that are either critical, or likely to become critical, after subsequent optimization
steps.

Delay-driven auto-ungrouping offers a less CPU-intensive alternative to using the -ungroup_all option for improving design timing.

-no_design_rule

Determines, along with the -only_design_rule and -only_hold_time options, whether the command fixes design-rule violations
before exiting. The -no_design_rule option specifies for the command to exit before fixing design-rule violations, thus allowing you
to check the results in a constraint report before fixing the violations. The -no_design_rule, -only_design_rule, and -
only_hold_time options are mutually exclusive. You can use only one of the options. The default is to perform both design-rule
fixing and mapping optimizations before exiting.

-only_design_rule

Determines, along with the -no_design_rule and -only_hold_time options, whether the command fixes design-rule violations
before exiting. The -only_design_rule option specifies for the command to perform only design-rule fixing; that is, mapping
optimizations are not performed. The -no_design_rule, -only_design_rule, and -only_hold_time options are mutually exclusive.
You can use only one option. The default is to perform both design-rule fixing and mapping optimizations before exiting.

-only_hold_time

Determines, along with the -no_design_rule and -only_design_rule options, whether the command fixes design-rule violations
before exiting. The -only_hold_time option specifies for the command to perform only hold-time fixing, ignoring other design rules.
The set_fix_hold command must be specified for hold-time fixing to be performed. The -no_design_rule, -only_design_rule, and
-only_hold_time options are mutually exclusive. You can select only one option. The default is to perform both design-rule fixing
and mapping optimizations before exiting.

-scan

Specifies that the command is to consider the impact of scan insertion on mission-mode constraints during optimization. This option

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causes the command to replace all sequential elements during optimization. Some scan-replaced sequential cells might be
converted to nonscan cells later in the test synthesis process because of test design-rule violations or explicit user specifications.
By accounting for the impact of internal scan insertion from the start of the design process, test-ready compile eliminates the need
for future reoptimization.

-top

Fixes design-rule and top-level timing violations for a design but does not perform any mapping on the design. By default, this
option fixes all design-rule violations, but it only fixes the timing violations whose paths cross top-level hierarchical boundaries. If
you want this option to fix timing violations for all paths, set the compile_top_all_paths variable to true.

-power_effort none | low | medium | high

Specifies the relative amount of CPU time spent during the power optimization phase of compile. Valid values are none, low,
medium, and high. You can select one value. The default is the specified map_effort. Since power optimization in compile is
enabled by power constraints, this option is ignored if there is no power constraint on the design.

-gate_clock

Enables clock gating optimization: clock gates are automatically inserted or removed. The -gate_clock option cannot be used in
combination with the -only_design_rule option. When used in combination with the -exact_map option, it may not be possible to
honor the -exact_map option for those registers that are involved with clock-gating optimization.

A clock-gating cell is not modified or removed if it or its parent hierarchical cell is marked dont_touch with the set_dont_touch
command.

DESCRIPTION
The compile command performs logic-level and gate-level synthesis and optimization on the current design. Optimization is controlled
by user-specified constraints on the design. These constraints describe goals for the optimization process, such as making the
smallest circuit possible or trying to make specified outputs arrive by a specified time. The optimization process trades off timing and
area constraints to provide the smallest possible circuit that meets specified timing requirements. Values for the area and speed of
components used in synthesizing and optimizing the design are obtained from user-specified libraries.

Constraints fall into one of two categories: design rule constraints and optimization constraints. Design rule constraints reflect
technology-specific restrictions that must be met for a design to function correctly. Optimization constraints reflect less critical design
goals and restrictions that are desirable but not crucial for the operation of a design.

The design rule constraints are max_transition, max_fanout, max_capacitance, and min_capacitance. All other constraints are
optimization constraints. Examples include maximum delay and maximum area.

During optimization, both types of constraints are considered; however, precedence is given to meeting design rule constraints. The
min_delay and fix_hold constraints are treated similarly to design rule constraints, except that they have lower priority than the
maximum delay constraints. The priority given to various constraints can be modified by using the set_cost_priority command.

Often when a design read from an HDL description is optimized, new designs modeled from the synthetic library are generated. These
designs are named according to the style specified in the synthetic_design_naming_style variable.

When the current design is hierarchical, and there are multiple design instances of a subdesign, it is not necessary to run the uniquify
command before running the compile command. The uniquify command can still be used on multiple design instances so they can
be individually optimized. For all designs marked with the uniquify attribute, compile copies and renames them according to the
uniquify_naming_style variable.

The compile command does not optimize across hierarchical boundaries unless the boundary_optimization attribute is set to true.
All synthetically generated designs are created with this attribute set to true. If boundary optimization causes ports to be
complemented, port names are changed according to the port_complement_naming_style variable.

To customize the way the compile command optimizes subdesigns, use compile directives. Commands for placing these directives
include set_flatten and set_structure. Command-line options pass global directives that affect how the entire design is optimized to
the compile command.

If the current design or any of its subdesigns is represented as a state table, the compile command automatically performs finite state

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machine optimizations on these designs. Finite state machine synthesis is also controlled with compile directives placed directly on
these designs by using commands such as set_fsm_encoding and set_fsm_minimize.

If the current design or any of its subdesigns contains arithmetic operations (additions, subtractions, multiplications, and comparisons),
the compile command automatically transforms them into datapath blocks to be implemented by a datapath generator. Datapath
optimization can be controlled by using the hlo_disable_datapath_optimization variable.

The compile command reports progress in real time by displaying a report. During optimization, the report shows incremental results
each time a transformation is applied to the design. The default fields of the report are ELAPSED TIME, AREA, WORST NEG SLACK,
TOTAL NEG SLACK, DESIGN RULE COST, and ENDPOINT.

ELAPSED TIME

Tracks the elapsed time since the beginning of the current compile or reoptimize_design.

AREA

Shows the area of the design during the optimization.

WORST NEG SLACK

Shows the worst negative slack (max_path violation) in all path groups.

TOTAL NEG

Shows the sum of the negative slack across all endpoints in the design.

DESIGN RULE COST

Measures the distance between the actual results and the user-specified design rule constraints.

ENDPOINT

Shows the endpoint currently being worked on. When a delay violation is being fixed, the object for the ENDPOINT is a pin or a port.
When a design rule violation is being fixed, the object for the ENDPOINT is a net.

You can specify other fields in addition to or instead of any of the default fields. For a list of available fields and other details about
specifying the compile log format, see the compile_log_format variable man page.

To display the same log format as the 1998.02 version, set compile_log_format = "". The fields for the 1998.02 version are
TRIALS, AREA, DELTA DELAY, TOTAL NEGATIVE SLACK, and DESIGN RULE COST. The new default does not have the
TRIALS and DELTA DELAY fields.

TRIALS

Tracks the number of transformations that the optimizer tries before making the current selection.

DELTA DELAY

Shows the current maximum delay cost of the design, which is the sum of the worst negative slack (max_path violation) in each
path group.

The log written by compile shows the different phases of optimization. In addition to the Resource Allocation and Mapping phases,
there are four more phases. The first of these is the Delay Optimization phase, which fixes max_path violations. In the Phase 1
Design Rule Fixing phase, design-rule violations are fixed without creating any new max_path delay violations. In the Phase 2
Design Rule Fixing phase, max_path delay constraints might be impacted while fixing design-rule violations. Finally, there is an
Area Recovery phase that attempts to reduce the area of the design while keeping other constraints intact. The Area Recovery
phase always does some minimal cleanup, but it performs more CPU-intensive area recovery only if max_area constraints have
been set on the design. If the -only_design_rule option is used, the Delay Optimization phase and Area Recovery phase are
skipped. If the -no_design_rule option is used, both Phase 1 Design Rule Fixing and Phase 2 Design Rule Fixing are skipped. If
the set_cost_priority command with the -delay option has been used before using the compile command, Phase 2 Design Rule
Fixing is skipped.

The set_local_link_library command sets the local_link_library attribute on a design. The local_link_library attribute contains a
list of design and library files that are searched before the files are specified with the link_library variable whenever a link operation
is performed. The target_library variable specifies a technology library or a list of technology libraries containing the components
(usually from a specific ASIC supplier) to use during optimization. The compile command sets the local_link_library attribute of

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the top-level design to the value of the target_library variable.

If compile is interrupted by an interrupt signal during an interactive process, it displays the following menu:

Please type in one of the following options:

1 to Write out the current state of the design
2 to Abort optimization
3 to Kill the process
4 to Continue optimization
Please enter a number:

If you select option 1, the design is written out and the menu reappears.

If the process is running in the background, you cannot use the menu. The number of interrupt signals determines what action is
performed. The sequence is as follows:

^C Information: Preparing to interrupt optimization... (INT-5)

^C Information: Aborting Optimization... (INT-6)
^C Information: Process terminated by interrupt. (INT-4)

The interrupt signal can be different from one machine to another.

EXAMPLES
The following examples apply to all modes.

The following command specifies that the current design be optimized without mapping the logic:

prompt> compile -no_map

The following command optimizes the design TEST twice; once for speed and once for area:

prompt> current_design TEST

prompt> set_max_delay 2.0 -to [all_outputs]

prompt> compile

prompt> set_max_area 250

prompt> compile

The following example specifies that the command perform restricted optimizations across hierarchical boundaries:

prompt> compile -boundary_optimization

The following example demonstrates a simple optimization strategy. The commands in the example first define the current design.
Design attributes and constraints are set. Optimization phases for compile are defined. The compile command is executed with the
specified options.

prompt> current_design TRIAL

prompt> set_wire_load_model "10x10"
prompt> set_operating_conditions "WCCOM"
prompt> create_clock -period 12 \
-waveform {0 6} CLK
prompt> set_input_delay 2 [all_inputs]
prompt> set_output_delay 3 [all_outputs]
prompt> set_max_area 580
prompt> set_structure -boolean false
prompt> set_flatten -phase true -effort medium
prompt> compile -incremental_mapping \
-no_design_rule

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prompt> report_constraint

SEE ALSO
alib_analyze_libs(2)
check_design(2)
create_clock(2)
insert_dft(2)
report_compile_options(2)
reset_design(2)
set_boundary_optimization(2)
set_cost_priority(2)
set_critical_range(2)
set_dont_touch(2)
set_dont_touch_network(2)
set_dont_use(2)
set_drive(2)
set_equal(2)
set_fix_hold(2)
set_fix_multiple_port_nets(2)
set_flatten(2)
set_fsm_encoding(2)
set_fsm_encoding_style(2)
set_fsm_order(2)
set_fsm_state_vector(2)
set_input_delay(2)
set_load(2)
set_local_link_library(2)
set_logic_dc(2)
set_logic_one(2)
set_logic_zero(2)
set_max_area(2)
set_max_capacitance(2)
set_max_delay(2)
set_max_fanout(2)
set_max_transition(2)
set_min_delay(2)
set_operating_conditions(2)
set_opposite(2)
set_output_delay(2)
set_prefer(2)
set_register_type(2)
set_structure(2)
set_timing_ranges(2)
set_unconnected(2)
set_wire_load_mode(2)
set_wire_load_model(2)
set_wire_load_min_block_size(2)
set_wire_load_selection_group(2)
ungroup(2)
uniquify(2)
alib_library_analysis_path(3)
compile_auto_ungroup_area_num_cells(3)
compile_auto_ungroup_count_leaf_cells(3)
compile_auto_ungroup_override_wlm(3)
compile_log_format(3)
compile_top_all_paths(3)
ungroup_keep_original_design(3)

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compile_exploration
Performs a fast mapping of gates with limited timing and area optimization.

SYNTAX
status compile_exploration
[-check_only]
[-exact_map]
[-gate_clock]
[-no_autoungroup]
[-no_boundary_optimization]
[-no_seq_output_inversion]
[-scan]

ARGUMENTS
-check_only

Checks whether the design and libraries have all the data that the compile_exploration command requires to run.

-exact_map

Specifies that sequential cells are mapped exactly as indicated in the HDL code. Specifying this option does not mean that QN pins
are not to be used in the mapped sequential element. Specifying the -exact_map option disables sequential output inversion. For
more information, see the compile_seqmap_enable_output_inversion variable.

-gate_clock

Enables clock-gating optimization, which automatically removes or inserts clock gates. When this option is used with the -
exact_map option, the command might not honor the -exact_map option for those registers that are involved with clock-gating
optimization.

A clock-gating cell is not modified or removed if the cell or its parent hierarchical cell is marked with the dont_touch attribute by the
the set_dont_touch command.

-no_autoungroup

Specifies to disable automatic ungrouping completely. All hierarchies are preserved unless otherwise specified.

-no_boundary_optimization

Specifies not to perform any hierarchical boundary optimization. By default, boundary optimization is turned on during the
compile_exploration step.

-no_seq_output_inversion

Disables sequential output inversion. The sequential phase of all sequential elements is the same as in the RTL. When this option
is not specified, the compile_exploration command can invert sequential elements during mapping and optimization.

-scan

Enables the examination of the impact of scan insertion on mission-mode constraints during optimization as in a normal compile.

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Use this option to replace all sequential elements during optimization. Some scan-replaced sequential cells might be converted to
nonscan cells later in the test synthesis process because of test design rule violations or explicit specifications.

DESCRIPTION
The compile_exploration command performs a fast mapping of gates with limited timing and area optimization. It typically runs much
faster than the compile or compile_ultra command. Like the compile command, the optimization is controlled by constraints that you
specify for the design. The compile_exploration command is targeted for high-performance designs with very tight timing constraints.
It provides you with a simple approach to achieve critical delay optimization.

When used with the set_host_options command, the compile_exploration command uses up to the specified number of CPU cores
on the same computer for parallel execution. For more details, see the description of the -max_cores option of the set_host_options
man page.

This command can be used in the same manner as the compile command.

By default, the compile_exploration command incorporates two ungrouping phases for design hierarchies. The first phase occurs
before the mapping step of first pass and attempts to ungroup small design hierarchies. The second ungrouping phase occurs during
the mapping optimization step and applies a delay-based ungrouping strategy for design hierarchies. If you need to preserve all design
hierarchies, specify the -no_autoungroup option.

By default, if dw_foundation.sldb is not specified in the list of the synthetic_library variable and the DesignWare license is checked
out successfully, dw_foundation.sldb is automatically added to the synthetic library to improve the QoR by using the licensed
DesignWare architectures. This behavior occurs in the current command only, and it does not affect the user-specified synthetic library
and link library lists.

By default, the compile_exploration command performs hierarchical boundary optimization, which can change the function of the
design. Therefore, hierarchical boundary optimization can only operate in its current environment. If input or output ports are
complemented as a result of this optimization, port names are changed according to the setting of the
port_complement_naming_style variable. To disable hierarchical boundary optimization, specify the -no_boundary_optimization
option.

SEE ALSO
compile(2)
compile_ultra(2)

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compile_prefer_runtime
Overrides runtime-intensive user settings with settings designed to improve runtime. The compile_prefer_runtime command settings
take effect when you run the compile_ultra, compile_ultra -incremental, or the optimize_netlist -area command.

SYNTAX
status compile_prefer_runtime

ARGUMENTS
This command has no arguments.

DESCRIPTION
The compile_prefer_runtime command overrides runtime-intensive user settings with settings designed to improve runtime. The
user-specified settings are reverted back to their original settings at the end of the optimization flow. The command also sets some
internal variables to reduce runtime. The command overrides the user settings before optimization starts during compile_ultra and
optimize_netlist and before report_congestion. The command is supported only in topographical mode.

Use the compile_prefer_runtime command only if runtime is a concern. The command disables runtime-intense optimizations, and
therefore it might impact QOR. The effect of the setting changes depends on the design. You might not see runtime improvements on
all designs.

For detailed information about the values that are changed when you use the compile_prefer_runtime command, see the "Using
Topographical Technology" chapter in the Design Compiler User Guide.

EXAMPLES
The following example enables runtime mode settings during compile:

prompt> compile_prefer_runtime
prompt> compile_ultra

SEE ALSO

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compile_ultra(2)
optimize_netlist(2)
report_congestion(2)

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compile_ultra
Performs a high-effort compile on the current design for better quality of results (QoR).

SYNTAX
status compile_ultra
[-incremental]
[-scan]
[-exact_map]
[-no_autoungroup]
[-no_seq_output_inversion]
[-no_boundary_optimization]
[-no_design_rule | -only_design_rule]
[-timing_high_effort_script
| -area_high_effort_script]
[-top]
[-retime]
[-gate_clock]
[-self_gating]
[-check_only]
[-congestion]
[-spg]
[-no_auto_layer_optimization]

ARGUMENTS
-incremental

Runs compile_ultra in incremental mode. In the incremental mode, the tool does not run the mapping or implementation selection
stages.

-scan

Enables the examination of the impact of scan insertion on mission-mode constraints during optimization, as in a normal compile.
Use this option to replace all sequential elements during optimization. Some scan-replaced sequential cells can be converted to
nonscan cells later in the test synthesis process because of test design rule violations or explicit specifications.

-exact_map

Specifies that sequential cells are mapped exactly as indicated in the HDL code. Use of the -exact_map option does not mean the
QN pin won't be used in the mapped sequential element. Use of the -exact_map option would disable sequential output inversion.
For more information, see compile_seqmap_enable_output_inversion.

-no_autoungroup

Specifies that automatic ungrouping is completely disabled. All hierarchies are preserved unless otherwise specified.

-no_seq_output_inversion

Disables sequential output inversion. The phase sequential of all sequential elements is the same as in the RTL. Without this
option, compile_ultra is free to invert sequential elements during mapping and optimization. For more information, see the man

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page for the compile_seqmap_enable_output_inversion variable.

-no_boundary_optimization

Specifies that no hierarchical boundary optimization is to be performed. By default, boundary optimization is turned on during
compile_ultra activity.

Specifies that no hierarchical boundary optimization is to be performed. By default, the -no_boundary_optimization option does
not disable constant propagation across design hierarchies. To disable constant propagation with the -no_boundary_optimization
option, set the compile_enable_constant_propagation_with_no_boundary_opt variable to false.

This option sets the compile_preserve_subdesign_interfaces variable to true.

-no_design_rule

Determines whether the command fixes design rule violations before exiting. The -no_design_rule option specifies for the
command to exit before fixing design rule violations, thus allowing you to check the results in a constraint report before fixing the
violations. The default is to perform both design rule fixing and mapping optimizations before exiting.

The -no_design_rule and -only_design_rule options are mutually exclusive. Use only one option.

-only_design_rule

Determines whether the command fixes design rule violations before exiting. The -only_design_rule option specifies for the
command to perform only design rule fixing; that is, mapping optimizations are not performed. The default is to perform both design
rule fixing and mapping optimizations before exiting.

The -no_design_rule and -only_design_rule options are mutually exclusive. Use only one option. The -only_design_rule option
can be used only with the -incremental option.

-timing_high_effort_script

This option is available in the tool to support backward compatibility with existing scripts and is ignored for optimization purposes.

-area_high_effort_script

This option is available in the tool to support backward compatibility with existing scripts and is ignored for optimization purposes.

-top

Fixes design rule and top-level timing violations in a design. By default, this option fixes all design rule violations, but only those
timing violations whose paths cross top-level hierarchical boundaries. If you want this option to fix timing violations for all paths, set
the compile_top_all_paths variable to true.

-retime

Uses the adaptive retiming algorithm during optimization to improve delay. This option is ignored if the -only_design_rule option or
the -top option is chosen at the same time.

-gate_clock

Enables clock gating optimization: clock gates are automatically inserted or removed. The -gate_clock option cannot be used in
combination with the -only_design_rule option. When used with the -exact_map option, it might not be possible to honor the -
exact_map option for those registers that are involved with clock gating optimization.

A clock gating cell is not modified or removed if it or its parent hierarchical cell is marked dont_touch with the set_dont_touch
command.

-self_gating

Enables the execution of self-gating insertion.

Self-gating is an clock gating technique that optimizes dynamic power by gating the clock signal in those cycles in which the data
saved in a register remains unchanged. An enable condition is computed by comparing the stored data with the new data arriving at
the data pin, and that signal is used to drive the inserted self-gating cell.

A self-gating cell can be shared across several registers by creating a combined enable condition so that the area and power
overhead due to the inserted cells is minimized.

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The selection of registers to be gated and the grouping of them to form the self-gating banks are driven by the switching activity at
the registers' data pins, the timing slack available, and the physical proximity between the registers to be grouped.

This option is only supported in Design Compiler topographical mode.

The -self_gating option cannot be used in combination with the -only_design_rule option.

-check_only

Checks whether the design and libraries have all the data that compile_ultra requires to run successfully. This option is available
only in Design Compiler topographical mode.

-congestion

This option will be obsolete in a future release. See the -spg option for information about congestion optimization.

-spg

This option is available only in Design Compiler topographical mode. Enables physical guidance, congestion optimization, and
automatic layer optimization. Congestion optimization reduces routing-related congestion. Physical guidance enables Design
Compiler Graphical to save coarse placement information and pass this coarse placement information to IC Compiler. With this
coarse placement, IC Compiler can begin the implementation flow with the place_opt command.

IC Compiler no longer needs to re-create the coarse placement by running commands such as create_placement,
remove_buffer_tree, or psynopt. By using the Design Compiler coarse placement as a starting point for placement, runtime and
area correlation with IC Compiler are improved.

Design Compiler Graphical automatically performs layer-aware optimization when you use the -spg option, modeling parasitic
variation across metal layers in a way that benefits optimization. This optimization helps remove excess pessimism, leading to
better area and power.

In addition to the default layer-aware optimization, you can also specify net constraints for layer optimization by setting specific
constraints using the set_net_routing_layer_constraints command or by creating a net-search pattern.

In the net-search pattern approach, you define a net-search pattern by using the create_net_search_pattern command and then
define associated minimum and maximum routing layer constraints for the search pattern by using the
set_net_search_pattern_delay_estimation_options command. Design Compiler invokes net-pattern identification after the high-
fanout synthesis step in compile_ultra and assigns the minimum and maximum constraints to the matching nets. The subsequent
optimizations consider the effects of the constraints (for example, the unit resistance and capacitance values of matching nets will
change) during buffering and buffer removal. You can define as many net-search patterns and associated layer constraints as
needed. In general, however, it is recommended to start with very long nets (for example, 500 um) with top routing layers (for
example, M7 and M8). You should consider this approach when your design shows significant unit resistance variation (see RCEX-
011 resistance values) across all available routing layers.

Note that the user-constraints and net-pattern layer optimization methods might affect runtime.

-no_auto_layer_optimization

The -no_auto_layer_optimization option is obsolete. Running the option has no effect on layer optimization.

DESCRIPTION
The compile_ultra command performs a high-effort compile on the current design for better quality of results (QoR). As with the
compile command, optimization is controlled by constraints that you specify on the design. This command is targeted toward high-
performance designs with very tight timing constraints. It provides you with a simple approach to achieve critical delay optimization.
The compile_ultra command packages all the DC Ultra features and enables them by default. It requires a DC Ultra license plus a
DesignWare Foundation license. This command provides the best strategy for optimum overall QoR and performance.

When used in conjunction with the set_host_options command, compile_ultra uses up to the user-specified number of CPU cores
on the same computer for parallel execution. See the description of the -max_cores option in the set_host_options man page for
more information.

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This command can be used in the same manner as the compile command.

By default, compile_ultra incorporates two ungrouping phases for design hierarchies. The first phase is performed before "Pass1
Mapping" and attempts to ungroup small design hierarchies. This first ungrouping phase can be turned off using the following
command:

set compile_ultra_ungroup_small_hierarchies false

The second ungrouping phase is performed during "Mapping Optimization" and applies a delay-based ungrouping strategy for design
hierarchies. If you need to preserve all design hierarchies, use the -no_autoungroup option. If you want to preserve the hierarchies
for a specific block, use the set_ungroup command.

By default, if dw_foundation.sldb is not in the synthetic_library list, and the DesignWare license is successfully checked out,
dw_foundation.sldb is automatically added to the synthetic_library to use the QoR benefit provided by the licensed DesignWare
architectures. This behavior occurs in the current command only, and it does not affect the user-specified synthetic_library and
link_library list.

By default, all DesignWare hierarchies are unconditionally ungrouped in the second pass of compile. You can set the
compile_ultra_ungroup_dw variable to control the ungrouping process of DesignWare components.

By default, hierarchical boundary optimization is performed on the design. This can change the function of the design so that it can
operate only in its current environment. If input or output ports are complemented as a result of this optimization, port names are
changed according to the port_complement_naming_style variable. Use the -no_boundary_optimization option to turn off the
boundary optimization feature.

By default, the tool applies a compile strategy intended to improve the resulting area of the design, possibly at the cost of additional
runtime. The strategy can make changes to variables or constraints that modify compile_ultra behavior and perform additional passes
to achieve better area.

EXAMPLES
The following example turns off boundary optimization for cell U1:

prompt> set_boundary_optimization [get_cells U1] false

prompt> compile_ultra

SEE ALSO
compile(2)
set_host_options(2)
create_net_search_pattern(2)
set_net_search_pattern_delay_estimation_options(2)

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compute_polygons
Returns a list or collection of polygons that exactly cover the region computed by performing a Boolean operation on the input
polygons.

SYNTAX
list compute_polygons
-boolean and | or | not | xor
poly_list1
poly_list2

Data Types
poly_list1 list or collection
poly_list2 list or collection

ARGUMENTS
-boolean and | or | not | xor

Specifies the Boolean operation to perform on the two input polygon lists or collections to produce the output polygon list or
collection.

"and" finds the area occupied by both the first and second input polygon list or collection.

"or" finds the area occupied by either the first or second input polygon list or collection, or occupied by both.

"not" finds the area occupied by the first input polygon list or collection and not occupied by the second polygon list or collection.

"xor" finds the area occupied by either the first or second input polygon list or collection, but not both.

poly_list1

Specifies the first list or collection of input polygons. You can specify a single polygon or multiple polygons, representing the first
argument for the geometric Boolean operation.

To specify a polygon as a list, enter a sequence of X-Y coordinate pairs that represent the successive vertices of the polygon, using
the following format:

{{x1 y1} {x2 y2} ... {xN yN} {x1 y1}}

The coordinate unit size is specified in the technology file; typically it is microns.

Polygons must be rectilinear, so the X coordinate of each data point must match the X coordinate of a neighboring data point, and
the Y coordinate must match the Y coordinate of the other neighboring data point. The last point in the list must be the same as the
first.

Instead of specifying lists of coordinates, you can specify a polygon collection. In that case, the output of the command is also a
collection.

poly_list2

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Specifies the second list or collection of input polygons. The command performs a Boolean operation between the first and the
second list or collection of polygons.

DESCRIPTION
This command performs a Boolean operation (OR, AND, NOT, or XOR) between two polygons or between two sets of polygons,
specified as lists of vertices or as polygon collections. It returns the result in the same form as the input polygons, either a list or a
polygon collection. The result can be a single polygon or a set of multiple, disjoint polygons.

Before using this command, the Milkyway design library containing the input polygons must be open. The input polygons must be
rectilinear, consisting of only vertical and horizontal line segments that meet at right angles.

You can directly pass the output of this command as a parameter directly to another compute_polygons command, but not to the
other polygon commands, convert_from_polygon, resize_polygon, or get_polygon_area. This is because the other polygon
commands can only take a single polygon as input. Instead, you must use a Tcl list command such as the foreach or lindex
command to extract each polygon from the returned list, and then pass each polygon to the other polygon command.

To view the coordinates of a polygon collection stored in a variable, use the following command:

prompt> get_attribute $variable_name coordinate

EXAMPLES
Assume that you have two polygons, A-B-C-D-A and A1-B1-C1-D1-A1, as shown in the following figure:

A B
+---------------------+
| |
| |
| A1 |E B1
| +--------------+------+
| | | |
| | | |
| | | |
+------+--------------+ |
D F| C |
| |
| |
+---------------------+
D1 C1

The following example performs the Boolean OR operation on these input polygons. The result is the B-E-B1-C1-D1-F-D-A-B polygon.

prompt> compute_polygons -boolean or \

{{0 30} {30 30} {30 10} {0 10} {0 30}} \
{{10 20} {40 20} {40 0} {10 0} {10 20}}
{{30.000 30.000} {30.000 20.000} {40.000 20.000} {40.000 0.000} {10.000 0.000}
{10.000 10.000} {0.000 10.000} {0.000 30.000} {30.000 30.000}}

The following figure shows the resulting polygon.

A B
+---------------------+
| |
| |
| |E B1

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| +------+
| |
| |
| |
+------+ |
D F| |
| |
| |
+---------------------+
D1 C1

The following example performs the Boolean AND operation on the same input polygons. The result is the A1-E-C-F-A1 polygon.

prompt> compute_polygons -boolean and \

{{0 30} {30 30} {30 10} {0 10} {0 30}} \
{{10 20} {40 20} {40 0} {10 0} {10 20}}
{{10.000 20.000} {30.000 20.000} {30.000 10.000}
{10.000 10.000} {10.000 20.000}}

The following figure shows the resulting polygon.

A1 E
+--------------+
| |
| |
| |
+--------------+
F C

The following example performs the Boolean NOT operation on these input polygons. The result is the B-E-A1-F-D-A-B polygon,
which is the region covered by the first polygon, A-B-C-D-A, but not covered by the second polygon, A1-B1-C1-D1-A1.

prompt> compute_polygons -boolean not \

{{0 30} {30 30} {30 10} {0 10} {0 30}} \
{{10 20} {40 20} {40 0} {10 0} {10 20}}
{{30.000 30.000} {30.000 20.000} {10.000 20.000} {10.000 10.000}
{0.000 10.000} {0.000 30.000} {30.000 30.000}}

The following figure shows the resulting polygon.

A B
+---------------------+
| |
| |
| A1 |
| +--------------+
| | E
| |
| |
+------+
D F

The following example performs the Boolean XOR operation on these input polygons. The result is two polygons, B-E-A1-F-D-A-B and
B1-C1-D1-F-C-E-B1, which are the areas covered by either input polygon, but not both.

prompt> compute_polygons -boolean xor \

{{0 30} {30 30} {30 10} {0 10} {0 30}} \
{{10 20} {40 20} {40 0} {10 0} {10 20}}
{{30.000 30.000} {30.000 20.000} {10.000 20.000} {10.000 10.000} {0.000 10.000}
{0.000 30.000} {30.000 30.000}} {{40.000 20.000} {40.000 0.000} {10.000 0.000}
{10.000 10.000} {30.000 10.000} {30.000 20.000} {40.000 20.000}}

The following figure shows the resulting polygons, moved apart slightly to clearly show the disjoint regions.

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A B
+---------------------+
| |
| |
| A1 | E B1
| +--------------+ +------+
| | E | |
| | | |
| | F | |
+------+ +-------------+ |
D F | C |
| |
| |
+--------------------+
D1 C1

The following example shows how compute_polygons can accept list of polygons as input.

prompt> compute_polygons -boolean or {{{0 0} {10 0} {10 10} \

{0 10} {0 0}} {{20 0} {30 0} {30 10} {20 10} {20 0}}} \
{{10 0} {20 0} {20 10} {10 10} {10 0}}
{{0.000 10.000} {30.000 10.000} {30.000 0.000} {0.000 0.000} {0.000 10.000}}

SEE ALSO
convert_from_polygon(2)
resize_polygon(2)

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connect_logic_net
Connects a logic net to logic ports in a UPF description.

SYNTAX
status connect_logic_net
net_name
-ports port_list
[-reconnect]

Data Types
net_name string
port_list list

ARGUMENTS
net_name

Specifies the net name. You must use a simple name.

-ports port_list

Specifies the ports connected to the net. The ports must be on the interface of the active UPF scope or on the design elements that
are located in the active scope and its descendants.

-reconnect reconnect

Allows a port that is already connected to a net to be disconnected from the existing net and connected to the newly specified net.

DESCRIPTION
This command connects a logic net to the specified ports. The net is propagated through implicitly created ports and nets throughout
the logic hierarchy in the descendant tree of the active UPF scope. The connection from the specified net in the active UPF scope to
any element in the port list cannot cross any power-domain boundaries. The -reconnect option disconnects any existing net from the
specified port and connects the newly specified net to all the ports present in the port_list.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

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SEE ALSO
create_logic_port(2)
create_logic_net(2)

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connect_net
Connects the specified net to the specified pins or ports.

SYNTAX
status connect_net
net
object_list

Data Types
net string
object_list list

ARGUMENTS
net

Specifies the net to connect. The net must be a scalar (single bit) net, and must exist in the current design.

object_list

Specifies a list of pins and ports to which the net is to be connected. Pins and ports must be at the same hierarchical level as the
specified net, and must exist in the current design. If a specified pin or port is already connected, the tool issues an error message.

DESCRIPTION
This command connects a net to the specified pins or ports at the same hierarchical level. The net can be at any level of hierarchy but
the pins or ports must be at the same level. A net can be connected to many pins or ports; however, you cannot connect a pin or port
to more than one net.

To disconnect objects on a net, use the disconnect_net command.

To display pins and ports on a net, use either the all_connected or get_nets -of $net command.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES

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The following example uses connect_net to connect net NET0 to ports A1 and A2 and pin U1/A. The all_connected command
returns the objects connected to net NET0.

prompt> connect_net NET0 [get_ports {A1 A2}]

prompt> connect_net NET0 [get_pins U1/A]

prompt> all_connected NET0

{A1 A2 U1/A}

The following example shows the error message generated when you attempt to connect a pin or port to more than one net:

prompt> connect_net MY_NET_1 PORT1

Connecting net 'MY_NET_1' to port 'PORT1'.

prompt> connect_net MY_NET_2 PORT1

Error: Object 'PORT1' is already connected to net 'MY_NET_1'.

The following example shows how connect_net is used to connect the U1/MY_NET net to the U1/MY_PORT port:

prompt> connect_net U1/MY_NET U1/MY_PORT

SEE ALSO
all_connected(2)
create_net(2)
current_design(2)
disconnect_net(2)
remove_net(2)

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connect_pin
Connects pins or ports at any level of hierarchy.

SYNTAX
status connect_pin
-from from_object
-to to_list
[-port_name port_name]
[-verbose]

Data Types
from_object collection
to_list collection
port_name string

ARGUMENTS
-from from_object

Specifies the pin or port from which to make the connection. The direction of the pin or port cannot be inout.

-to to_list

Specifies the pins and ports to which to make the connection. The pins and ports can be at any level of the hierarchy. The direction
of the pins or ports cannot be inout.

-port_name port_name

Specifies the base name to use as the names of ports that are created on subdesigns to make the connection.

-verbose

Specifies that the tool displays individual netlist operations while making the global connections.

DESCRIPTION
This command performs global connections between the source object specified in the -from option and the objects specified in the -
to option. The specified pins and ports can be at any level of hierarchy. The parent design of the pins and ports must be unique.

While making the global connections, ports and nets are created in the subdesigns, if needed. Ports in the subdesigns are reused
regardless of their names, when the from pin is already connected to a net. Also, a port in a subdesign is reused if it is unconnected
and the name is as specified by the -port_name option.

Wherever applicable, the name of the net that is created is the name of the connecting port, as long as there is no net with the same

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name in that design. If there is an existing net with the name, the name of the net is generated.

The connect_pin command ensures that multiply-driven nets are not created. The command does not allow a connection from an
output pin to an output pin.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example uses the connect_pin command to connect the U1/Z output pin to the mid1/bot1/U3/A input pin.

Use the report_net -connections or report_cell -connections command to view the connections.

prompt> connect_pin -from [get_pins U1/Z] \

-to [get_pins mid1/bot1/U3/A]

prompt> report_net -connections [get_net -of [get_pins U1/Z]]

SEE ALSO
all_connected(2)
connect_net(2)
create_port(2)
report_cell(2)
report_net(2)

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connect_supply_net
Connects the supply net to specified supply ports and pins.

SYNTAX
status connect_supply_net
supply_net_name
-ports list
[-vct vct_name]

Data Types
supply_net_name string
list list
vct_name string

ARGUMENTS
supply_net_name

Specifies the name of the supply net to be connected, which must be an existing simple (nonhierarchical) supply net name.

-ports list

Specifies the supply ports or pins that are to be connected with the supply net. Each item in the list is the hierarchical name of a
supply port or pin.

-vct vct_name

Specifies the value conversion table (VCT) to be used in this connection.

The tool supports only the following 14 predefined VCT names: UPF2VHDL_SL ; UPF_GNDZERO2VHDL_SL ; UPF2SV_LOGIC ;
UPF_GNDZERO2SV_LOGIC ; VHDL_TIED_HI ; SV_TIED_HI ; VHDL_TIED_LO ; SV_TIED_LO ; VHDL_SL2UPF ;
VHDL_SL2UPF_GNDZERO ; SV_LOGIC2UPF ; SV_LOGIC2UPF_GNDZERO ; SV_LOGIC2UPF_MD ;
SV_LOGIC2UPF_GNDZERO_MD.

DESCRIPTION
The connect_supply_net command makes an explicit connection of a supply net to specified supply ports or pins. It overrides (has
higher precedence than) the automatic connection semantics that might otherwise apply.

If a design element is not connected explicitly to any supply net using the connect_supply_net command, it shares the primary power
or ground supply net with the power domain to which it belongs.

Before they can be connected, the supply net must be created in the same power domain as the supply port. The instance that
contains the pin must also be in the extent of the same power domain.

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The command can be used to connect a supply net to bias pins. Bias pins that meet following conditions are supported:

The bias pin is from a macro cell

The bias pin direction is "input" or "inout"

The bias pin physical_connection is "routing_pin"

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example connects a supply net named VSS with the supply port VSS:

prompt> create_power_domain PD1 -elements INST_1

PD1
prompt> create_supply_net VSS -domain PD1
VSS
prompt> create_supply_port VSS -domain PD1
VSS
prompt> connect_supply_net VSS -ports VSS
1

The following example shows how to connect a supply set with a supply port:

prompt> connect_supply_net sset.power -ports VDD

1
prompt> connect_supply_net sset.ground -ports VSS
1

SEE ALSO
create_supply_net(2)
report_supply_net(2)

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continue
Begins the next loop iteration.

SYNTAX
int continue

ARGUMENTS
None

DESCRIPTION
This command begins the next iteration of the innermost loop. To immediately reevaluate the condition of a while loop, use the
continue command, rather than executing the remaining statements to the end.

The continue command always returns the integer 1, indicating successful operation. A syntax error is reported if the continue
command is used outside a loop structure.

EXAMPLES
The following example plots the first 10 sheets of the current design, except for sheet 5:

set p 0
while {$p <= 10} {
if {$p % 2} {
incr p
continue
}
echo "$p squared is: [expr $p * $p]"; incr p

SEE ALSO
break(2)
while(2)

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convert_from_polygon
Converts each polygon into a list or collection of mutually exclusive rectangles.

SYNTAX
list convert_from_polygon
polygons
[-format polygon | rectangle]

Data Types
polygons polygon list or collection

ARGUMENTS
polygons

Specifies the list or collection of input polygons to be decomposed into rectangles. You can specify a single polygon or multiple
polygons.

To specify a polygon as a list, enter a sequence of X-Y coordinate pairs that represent the successive vertices of the polygon, using
the following format:

{{x1 y1} {x2 y2} ... {xN yN} {x1 y1}}

The coordinate unit size is specified in the technology file; typically it is microns.

Polygons must be rectilinear, so the X coordinate of each data point must match the X coordinate of a neighboring data point, and
the Y coordinate must match the Y coordinate of the other neighboring data point. The last point in the list must be the same as the
first.

Instead of specifying lists of coordinates, you can specify a polygon collection. In that case, the output of the command is also a
collection.

-format polygon | rectangle

Specifies the output format of the resulting rectangles.

By default, each resulting rectangle is represented as two data points at opposite corners of the rectangle:

{x1 y1} {x2 y2}

If you specify -format polygon, each resulting rectangle is represented in polygon format, using five data points for the round trip
around the perimeter of the rectangle:

{{x1 y1} {x2 y1} {x2 y2} {x1 y2} {x1 y1}}

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DESCRIPTION
This command converts a polygon into a list of mutually exclusive rectangles. The returned rectangles are represented as a list of
coordinates or a collection. Before using this command, the Milkyway design library must be open.

Note that this command might return a list of disjoint polygons. Because the polygon commands take a single polygon as input, you
cannot directly pass the result as a parameter to another polygon command. Instead, you must use a Tcl list command, such as the
foreach or lindex command, to extract each polygon from the returned list, and then pass each polygon to the polygon command.

EXAMPLES
The following example converts the A-B-C-D-E-F-G-H-A polygon to three rectangles, K-F-G-H, E-I-C-D, and A-B-I-K.

A B
+---------------------+
| |
| |
| |
K+- - - +-------+ - - -+I
| |F E| |
| | | |
| | | |
+------+ +------+
H G D C

prompt> convert_from_polygon {{0 20} {30 20} {30 0} \

{20 0} {20 10} {10 10} {10 0} {0 0} {0 20}}
{{0.000 0.000} {10.000 10.000}} {{20.000 0.000}
{30.000 10.000}} {{0.000 10.000} {30.000 20.000}}

SEE ALSO
convert_to_polygon(2)
compute_polygons(2)
resize_polygon(2)

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convert_pg
Converts RTL PG information extracted from RTL into UPF. This command is supported only in UPF mode.

SYNTAX
status convert_pg
[-net_creation_style style]

Data Types
style string

ARGUMENTS
-net_creation_style style

Optional argument which tells convert_pg the style of supply net to be created in case a matching supply net is not found in the
UPF. Valid values for style are domain_dependent and domain_independent.

DESCRIPTION
The convert_pg command converts the PG network information extracted from RTL during the link command into UPF constraints.
For the link command to extract the PG network from RTL, the dc_allow_rtl_pg Tcl Boolean variable must be set before reading in
the RTL.

The PG network is converted into a set of domain-dependent UPF constraints or domain-independent UPF constraints depending on
the style specified to the -net_creation_style option.

The convert_pg command requires some basic UPF constraints to have been loaded and at least a top level power domain defined
already. It then tries to match each RTL PG net with an existing supply net, if any. If there is no match, then either a domain-
dependent supply net or a domain-independent supply net is created for the RTL PG net, based on the value specified to the -
net_creation_style option. In addition, supply ports are also created as required. If a supply net cannot be created because of the lack
of knowledge of a target power domain, then errors are reported.

The RTL net connections to PG pins are converted to connect_supply_net commands. If your UPF connects a different supply net to
the same PG pins, then an error is reported.

If convert_pg command can successfully convert all of the PG network to UPF, then it returns a status of 1. Otherwise, a status of 0 is
returned.

After the convert_pg command converts the PG network to UPF successfully, subsequent calls to the convert_pg command yield
nothing.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

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EXAMPLES
The following examples show different usages of the convert_pg command and its outcome.

The following shows the behavior when the convert_pg command is called without any RTL PG information.

prompt> convert_pg
Information: The design does not contain any RTL-derived PG nets. (UPF-439)

The following shows the behavior when the convert_pg command is called without loading any UPF constraints.

prompt> convert_pg
Error: No top level power domain found.

The following shows the behavior when the convert_pg command is called again after a successful call.

prompt> convert_pg
Information: The design does not contain any RTL-derived PG nets. (UPF-439)

The following shows the behavior when the convert_pg command successfully converts the PG network into domain-dependent UPF.

prompt> convert_pg -net_creation_style domain_dependent

Generating UPF for PG netlist derived from RTL:

create_supply_net {vdd} -domain {TOP}

create_supply_port {vdd} -direction {in}
connect_supply_net {vdd} -port {vdd}
connect_supply_net {vdd} -port {mid1/U1/VDD mid1/bot1/U1/VDD}
1

SEE ALSO
dc_allow_rtl_pg(3)

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convert_to_polygon
Returns a polygon list for the specified objects.

SYNTAX
list convert_to_polygon
[-quiet]
[-collection]
object_spec

Data Types
object_spec object collection

ARGUMENTS
-quiet

Suppresses the reporting of error and warning messages.

-collection

This option is not supported in Design Compiler.

object_spec

Specifies the input object collection. The object class must be fixed cells, fixed physical-only cells, a placement blockage, or a move
bound.

DESCRIPTION
This command returns polygons calculated from the input objects. The returned polygon is represented as a list of polygon vertex
coordinates.

EXAMPLES
The following example returns a polygon list from the MB#123 move bound.

prompt> convert_to_polygon [get_bounds MB#123]

{{99.490 111.340} {117.590 111.340} {117.590 112.620} {99.490 112.62}
{99.490 111.340}}

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SEE ALSO
convert_from_polygon(2)
compute_polygons(2)
resize_polygon(2)

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copy_collection
Duplicates the contents of a collection, resulting in a new collection. The base collection remains unchanged.

SYNTAX
collection copy_collection
collection1

Data Types
collection1 collection

ARGUMENTS
collection1

Specifies the collection to be copied. If an empty string is used for the collection1 argument, the command returns the empty string
(a copy of the empty collection is an empty collection).

DESCRIPTION
This command is no longer needed and is provided only to make old scripts work without modification.

EXAMPLES
The following example from PrimeTime shows the result of copying a collection. Functionally, it is not much different that having
multiple references to the same collection, except it is slower.

prompt> set c1 [get_cells "U1*"]

{U1 U10 U11 U12}
prompt> set c2 [copy_collection $c1]
{U1 U10 U11 U12}
prompt> unset c1
prompt> query_objects $c2
{U1 U10 U11 U12}

SEE ALSO

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collections(2)

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copy_design
Copies a design to a new design, or copies a list of designs to a new file in dc_shell memory.

SYNTAX
string copy_design
design_list
target_name

Data Types
design_list string
target_name string

ARGUMENTS
design_list

Specifies a lists of designs to copy. If a design is specified, the target_name must be a file name. All of the listed designs are copied
to the the specified file with their base design names.

target_name

Specifies the name of the new design to create or the name of the file to which multiple designs are copied.

DESCRIPTION
The copy_design command copies a list of designs either to a target file or to a newly created design.

In the first form, the copy_design command copies the contents of design_name to target_name. The attributes and constraints of
design_name are copied with the design. A design cannot be copied over another design that already exists in dc_shell.

In the second form, copy_design copies the designs listed in design_name to the file specified by target_name.

To write these files to disk, use the write command.

EXAMPLES
This example copies the design named TEST to the design named BILL:

prompt> copy_design TEST BILL

Information: Copying design /usr/example/TEST.DB:TEST to /usr/example/TEST.db:BILL.

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(UIMG-45)

prompt> list_designs
BILL TEST.db (*)

This example copies design TEST to the new file my_test.db:

prompt> copy_design TEST /usr/example/my_test.db:TEST

Information: Copying design /usr/example/TEST.db:TEST to /usr/example/my_test.db:TEST.
(UIMG-45)

prompt> list_designs -show_file

/usr/example/TEST.db
TEST (*)

/usr/example/my_test.db
TEST

In this example, the get_designs command is used with copy_design to copy all of the designs currently read into dc_shell to a
single file:

prompt> list_designs -show_file

/usr/example/TEST.db
TEST (*)

/usr/example/ADDER.db
ADDER

prompt> copy_design [get_designs *] /usr/dc/project/all.db

Information: Copying design /usr/example/TEST.db:TEST to /usr/dc/project/all.db:TEST.
(UIMG-45)
Information: Copying design ADDER.db:ADDER to /usr/dc/project/all.db:ADDER.
(UIMG-45)

prompt> list_designs -show_file

/usr/example/TEST.db
TEST (*)

/usr/example/ADDER.db
ADDER

/usr/dc/project/all.db
ADDER TEST

If you attempt to copy multiple designs without specifying a target file name as the second argument of the copy_design command,
an error is generated, as shown below:

prompt> copy_design {A, B, C} all.db:TEST3

Error: Cannot copy multiple designs to a single design
(UIMG-4)

SEE ALSO
current_design(2)
get_designs(2)
remove_design(2)
rename_design(2)
write(2)

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copy_lib
Copies one or more design libraries from one location to another.

SYNTAX
status copy_lib
[-force]
[-merge | -no_designs]
[-from_lib source_name]
-to_lib destination_name

Data Types
source_name string
destination_name string

ARGUMENTS
-force

Overwrites the destination library when the library is modified but not yet saved. If this option is not specified, the command stops
and issues an error message if the library is modified but not yet saved.

-merge

Merges the source library into the destination library. This option is used for incremental update. Normally, the destination library is
(re)initialized before the copy begins. This option can be used only if both the source and destination libraries are design libraries.
Note that lib-cell libraries cannot be merged, and library attributes, technology, and parasitic_tech data are not merged. If the
destination library does not already contain technology or parasitic_tech data, the command copies the technology or tech_parasitic
data from the source library to the destination library. Only libraries with compatible technology can be merged, and the command
performs a technology compatibility test if both the source and destination libraries contain technology sections. The -merge option
fails if the source and destination technologies are incompatible.

-no_designs

Copies the source library to the destination library, without copying the designs in the source library. This option is mutually
exclusive with the -merge option. The command copies the library attributes, ref_lib list, view_switch list, technology, and
parasitic_tech from the source library without copying any of the designs. This option is useful when splitting a source library that
contains subblocks into a separate destination libraries that each contain a subblock.

-from_lib source_name

Specifies the name of source NDM library. If you specify a list of NDM library names, the designs in each library are copied to the
destination library. If there are duplicate designs in the source libraries, the design from the first library in the list that contains the
duplicate is copied to the destination library. If the -no_designs option is used, the -from_lib option must contain a single library. If
this option is not specified, the command uses the current library. Use the current_lib command to determine the current library.

-to_lib destination_name

Specifies the destination library name. This can be a simple, relative, or absolute path. If it is a relative or absolute path, the trailing
portion of the path after he last '/' becomes the name of the library. It will be an error if the a library, file, or directory of the same

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name already exists on disk.

DESCRIPTION
This command copies one or more source libraries into a destination library. If technology data and a ref_lib list exists, they are copied
as well. Note that the command fails if there are conflicts in technology data among the source libraries or between the source and
destination libraries when the -merge option is used. When there are conflicts in design data, the data from the first library in the
source list is used (or from the destination library if the -merge option is used and a conflict exists). Note that conflicts are resolved on
the design level, not down to the view level. For example, if a source library has topLib1:Mid.timing and another source library has
topLib2:Mid.design, only the first design is copied. The destination target is reinitialized (deleted) before the copy unless the -merge
option is used. When the source and destination libraries contain a reference library list, the source reference list is appended to the
target library and the duplicate entries are removed.

The command returns 1 if successful, or 0 otherwise. If an illegal name is given, a Tcl error is raised.

Note that when overriding an existing library (without the -merge option), there is no automatic rebinding to the new design or
technology data in the library. All original designs in the library are removed, and designs from other libraries that used to bind to those
removed designs become unbound. Any other libraries or designs that used to bind to the technology data of the overridden library are
also be unbound and are saved without a technology section.

It is also an error to copy (or merge) from (or into) lib-cell library. It is also an error to copy over a library that is opened for read-only, or
to copy over a library that has unsaved and modified data without using the -force option.

This command is supported in Design Compiler NXT topographical mode.

EXAMPLES
The following example copies library lib1 into the library design_lib.

prompt> copy_lib -from_lib "lib1" -to_lib design_lib

1

The following example copies the designs from lib1 and lib2 into the library top_lib.

prompt> copy_lib -from_lib "lib1 lib2" -to_lib top_lib

1

The following example merges the designs from lib1 and lib2 into the library mid_lib, without reinitializing mid_lib

prompt> copy_lib -merge -from_lib "lib1 lib2" -to_lib mid_lib

1

The following example copies the technology and ref_lib list from lib1 to lib2 without copying the designs.

prompt> copy_lib -no_designs -from_lib "lib1" -to_lib lib2

1

SEE ALSO
close_lib(2)
create_lib(2)
current_lib(2)
get_libs(2)

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move_lib(2)
open_lib(2)
save_lib(2)
search_path(3)
set_ref_libs(2)
shell_is_in_ndm_mode(2)

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copy_mw_lib
Copies a Milkyway library to another location.

SYNTAX
status copy_mw_lib
[-from mw_lib]
-to lib_name

Data Types
mw_lib string
lib_name string

ARGUMENTS
-from mw_lib

Specifies the name of the source Milkyway library to be copied. The mw_lib value can be a library name or a collection of libraries.
By default, the command uses the current Milkyway library.

-to lib_name

Specifies the destination Milkyway library name.

DESCRIPTION
The copy_mw_lib command copies a Milkyway library to another location. It returns a status indicating success or failure.

Multicorner-Multimode Support

This command has no dependency on scenario-specific information.

EXAMPLES
The following example copies a Milkyway library design to another location:

prompt> copy_mw_lib -from design -to design.bak

1

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SEE ALSO
rename_mw_lib(2)

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cputime
Reports the CPU time in seconds.

SYNTAX
status cputime
[-all]
[-verbose]

ARGUMENTS
-all

Reports the total CPU time of the main process and its child processes. This is the default; this option is kept for backward
compatibility.

-verbose

Reports in detail the CPU time and elapsed (wall-clock) time of the main process and each child process, including placement,
extraction, and routing.

DESCRIPTION
The cputime command reports the CPU time in seconds. If you specify -verbose, it reports the CPU time and elapsed (wall-clock)
time for the main process and each child process. The runtime numbers are collected from the operating system.

When you use the set_host_options command, the tool runs multiple threads. Currently the operating system measures the CPU
time by adding the usage for all threads. It does not take into account parallelization of the threads. This means that the report might
show a larger CPU time than elapsed time when you use set_host_options. The elapsed time (wall-clock time) is more appropriate
for measuring multicore runtime.

The elapsed time depends on many external factors and can vary for every session. It depends on factors such as the I/O traffic, the
network traffic, RAM and swap usage, and the other processes running on the same machine. When the elapsed time is much longer
than the CPU time, it might point out an inefficiency of the computing environment, such as insufficient memory, too many processes
running on the same machine, or a slow network. The only way to make the elapsed time close to the CPU time is to run only one
session on a machine with enough RAM and using the local disk.

EXAMPLES
The following example shows the default command output:

prompt> cputime

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1202

The following example shows the output when using the -verbose option:

prompt> cputime -verbose

Main process CPU: 1202 s (0.33 hr) Elapse: 1800 s (0.50 hr)
Child "placement" called 3 times, total CPU: 200 s (0.06 hr)
Elapse: 250 s (0.07 hr)
Child "extraction" called 2 times, total CPU: 100 s (0.03 hr)
Elapse: 150 s (0.04 hr)
Total CPU: 1502 s ( 0.42 hr) Elapse: 1800 s ( 0.50 hr)

1523

SEE ALSO
mem(2)
set_host_options(2)

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create_auto_path_groups
Creates path groups for the current design.

SYNTAX
string create_auto_path_groups
-mode rtl | mapped
[-exclude IO | macro | ICG]
[-slack slack]
[-max max]
[-min_regs_per_hierarchy min_regs]
[-prefix prefix]
[-file file_name]
[-verbose]
[-user_path_groups_file user_file_name]
[-skip]

Data Types
slack double
max int
min_regs int
prefix string
file_name string
user_file_name string

ARGUMENTS
-mode rtl | mapped

Specifies if paths groups should be created for all hierarchies before optimization (-mode rtl) or only for hierarchies that fail timing
after optimization (-mode mapped).

-exclude IO | macro | ICG

Prevents the generation of specific path groups. Supported values are macro, IO, and ICG. You can specify any combination of
values. By default, the command creates path groups for I/Os, macros, and integrated clock-gating cells.

-slack slack

Specifies the slack value used to create group paths in mapped mode. The default is 0.0.

-max max

Specifies the maximum number of path groups in mapped mode. The default is 0, which means unlimited.

-min_regs_per_hierarchy min_regs

Specifies the minimum number of registers per hierarchy to be considered for path groups in rtl mode. The default is 10.

-prefix prefix

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Specifies the prefix of the path groups names. The default is synopsys_pg_.

-file file_name

Writes group_path commands to the specified file.

-verbose

Activates the verbose mode.

-user_path_groups_file user_file_name

Specifies the file to which user path groups are saved. The default is auto_path_groups.user_path_groups.tcl.

DESCRIPTION
Creates path groups automatically for the current design. You can create path groups either after elaboration or after the initial
compile.

To create path groups after the design has been elaborated, run the create_auto_path_groups command with the -mode rtl option.
This creates one path group per hierarchy within the design. If there are multiple levels of hierarchy, the tool creates path groups for
each level. The advantage of creating path groups at this stage is that the tool can perform all optimizations during the initial compile.
However, the number of hierarchical levels within the design can be large, leading to a large number of path groups and causing
excessive the runtime. Modules that have the optimize_registers attribute set on them are excluded to avoid the possibility of
optimize_registers not working on the modules that have a path group set on them.

To create path groups after the design has successfully completed the initial compile, run the create_auto_path_groups command
with the -mode mapped option. This creates one path group per hierarchy only for those hierarchies within the design that are not
meeting timing. If there are multiple levels of hierarchy that are not meeting timing, the tool creates path groups for each of those
levels. Fewer path groups are created when you use the -mode mapped option compared to the -mode rtl option because, in most
cases, not all hierarchical blocks violate timing. Only those that fail to meet timing are assigned a separate path group, and therefore
the runtime impact is reduced. In most cases, use this flow.

When you use the -mode mapped option, you can provide a slack value by specifying the-slack option or provide the maximum
number of paths by specifying the -max option. The default slack value is zero, which means that the command creates path groups
for all violating paths. The default maximum number of paths value is zero, which means that the number of path groups is unlimited.
When you set the -max option to a value other than zero, path groups are created only for hierarchies with the maximum worst
violations.

You can control path groups names by using the -prefix option. By default, the prefix is synopsys_pg_. For example, path group
names by default would be synopsys_pg_0, synopsys_pg_1, and so on.

The generated group_path commands are listed in the output file specified by the-file option. You can edit the output file and add
weight or critical_range options on particular path groups.

You can remove path groups generated by the create_auto_path_groups command by using the remove_auto_path_groups
command.

Notes
If the design has inserted clock gates at the GTECH stage, you should run the create_auto_path_groups command only after the
initial compile (with the -mode mapped option). This would lead to the creation of fewer path groups than running the
create_auto_path_groups command before optimization (with the -mode rtl option), resulting in better runtime.

Multicorner-Multimode Support
This command uses information from the current scenario only.

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EXAMPLES
The following example creates path groups after design elaboration and removes them after compile. First, read the RTL, perform
analyze and elaborate, and read the SDC constraints.

prompt> create_auto_path_groups -mode rtl # creates path groups at pre-compile stage

prompt> compile_ultra
prompt> report_qor # reports both user and script-created path groups
prompt> remove_auto_path_groups # removes only the script-created path groups
prompt> report_qor # reports only the user-created path groups

The following example creates path groups after compile and removes them after incremental compile. First, read the RTL, perform
analyze and elaborate, and read the SDC constraints.

prompt> compile_ultra
prompt> create_auto_path_groups -mode mapped # creates path groups at post-compile stage
prompt> compile_ultra -incremental
prompt> report_qor # reports both user and script-created path groups
prompt> remove_auto_path_groups # removes only the script-created path groups
prompt> report_qor # reports only the user-created path groups

Consider an example with the following design hierarchy:

+---------------------------------------------+
|top |
| +--------+ +----------------+ |
| |m1 | |m2 | |
| +--------+ | +--------+ | |
| | |m3 | | |
| | +--------+ | |
| | | |
| +----------------+ |
| |
+---------------------------------------------+

If paths groups are created after elaboration:

prompt> create_auto_path_groups -mode rtl -exclude {IO macro ICG}

INFO: Collecting hierarchies without optimize_registers...
INFO: Creating path groups for hierarchies without optimize_registers...
INFO: group_path -name synopsys_pg_0 -to [get_cells m1/*
-filter "is_hierarchical==false && is_sequential==true"] -priority 1
INFO: group_path -name synopsys_pg_1 -to [get_cells m2/*
-filter "is_hierarchical==false && is_sequential==true"] -priority 1
INFO: group_path -name synopsys_pg_2 -to [get_cells m2/m3/*
-filter "is_hierarchical==false && is_sequential==true"] -priority 1

If paths groups are removed after compile:

prompt> remove_auto_path_groups
INFO: remove_path_group synopsys_pg_2
INFO: remove_path_group synopsys_pg_1
INFO: remove_path_group synopsys_pg_0

If set_optimize_registers is set on m2 and paths groups are created after elaboration:

prompt> set_optimize_registers [get_designs [get_attribute [get_cells m2] ref_name]] true

prompt> create_auto_path_groups -mode rtl -exclude {IO macro ICG}
INFO: Collecting hierarchies without optimize_registers...
INFO: Creating path groups for hierarchies without optimize_registers...
INFO: group_path -name synopsys_pg_0 -to [get_cells m1/* -filter "is_hierarchical==false &&
is_sequential==true"] -priority 1

If paths groups are removed after compile:

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prompt> remove_auto_path_groups
INFO: remove_path_group synopsys_pg_0

SEE ALSO
remove_auto_path_groups(2)

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create_block_abstraction
Generates a block abstraction for the current design. The command identifies the interface logic of the current design and annotates
the design in memory with the interface logic.

SYNTAX
status create_block_abstraction
[-include objects]

Data Types
objects collection

ARGUMENTS
-include objects

Specifies the additional leaf cells and nets that are to be included in the block abstraction.

Logical hierarchical cells and pins are ignored.

If either one of the following conditions exist, the entire block is included in the block abstraction:

The number of leaf cells included exceeds 95 percent of the total leaf cells in the block.

The number of nets included exceeds 95 percent of the total nets in the block.

DESCRIPTION
This command creates a block abstraction of the current design and annotates the design in memory with the interface logic.

To save the block abstraction, you must use the write_file command immediately after creating the block abstraction. The write_file
command writes the complete design, including the block abstraction information, into a single .ddc file.

Creating a block abstraction by using the create_block_abstraction command allows you to perform transparent interface
optimization on the block in the top-level flow.

You can create block abstractions in either Design Compiler or Design Compiler in topographical mode. However, you must use
topographical mode to optimize block abstractions with transparent interface optimization, and only block abstractions created in
topographical mode are optimized.

At the top level, use the set_top_implementation_options command to specify which blocks should be integrated with the top-level
design as block abstractions.

The create_block_abstraction command first determines the interface logic.

The following netlist objects are part of the interface logic:

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All cells, pins, and nets in timing paths from input ports to registers or output ports.

All cells, pins, and nets in timing paths to output ports from registers or input ports.

The following clock-gating circuitry:

Any logic in the connection from the master clock to the generated clocks.

The clock trees that drive interface registers, including any logic in the clock tree.

The longest and shortest clock paths from the clock ports.

The side-load cells of all nonideal and non-DRC disabled nets.

By default, the create_block_abstraction command ignores an input or inout port during interface logic identification, if the
percentage of the total registers in the transitive fanout of the port is greater than or equal to the threshold percentage specified in the
abstraction_ignore_percentage variable. (The default is 25.) The ports that are ignored are then connected to already-identified
interface logic. Also, minimum and maximum critical timing paths are retained for these ignored ports.

This default helps to identify the test enable and reset ports of your design. Examine the current value of the
abstraction_ignore_percentage variable and change it, if needed. The default might potentially ignore ports you do not want to
ignore or fail to ignore ports that you do want to ignore. Carefully read the messages that the create_block_abstraction command
issues when you use the default to see which ports have been ignored and to what percentage of registers they fanned out.

The create_block_abstraction command implicitly performs an update_timing on the design, if required.

The create_block_abstraction command ignores case analysis settings, if any, during interface logic identification. You must specify
the appropriate case analysis settings at the top level. This is done to make the block abstraction more context independent.

The create_block_abstraction command assumes all latches found in the interface logic are potential borrowers; thus, all logic from
I/O ports to flip-flops or output ports are identified as belonging to the interface logic.

Multicorner-Multimode Support

This command uses information from all scenarios.

For a multicorner-multimode design,

The create_block_abstraction command automatically detects the presence of multiple scenarios (multiple modes or
corners) and determines the interface logic for each scenario. The interface logic identified for each scenario is retained as the
interface logic of the block abstraction. If an interface timing path is disabled in one scenario but enabled in another, the path
is included in the interface logic.

Net capacitance, resistance, and annotated delays are stored as part of abstraction information for each specified TLUPlus
file and temperature.

Power consumption of the design is calculated for each scenario. The calculated power data is stored in attributes in the
design and can be used by the report_power command during the final assembly step of the entire chip.

EXAMPLES
The following example shows how to create and save a block abstraction:

prompt> read_ddc MY_DES.compiled.ddc

prompt> create_block_abstraction
prompt> write_file -hierarchy -format ddc -output MY_DES.abstract.ddc

SEE ALSO

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abstraction_ignore_percentage(3)
check_block_abstraction(2)
report_block_abstraction(2)
set_top_implementation_options(2)

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create_bounds
Creates a fixed move bound or floating group bound in the design.

SYNTAX
status create_bounds
[-name bound_name]
[-coordinate {llx1 lly1 urx1 ury1 ...}]
[-dimension bound_dimension]
[-diamond central_object]
[-effort low | medium | high | ultra]
[-type soft | hard]
[-exclusive]
[-color color]
[-cycle_color]
[-repelling diamond | rect]
[-groups list]
object_list

Data Types
bound_name string
llx1 float
lly1 float
urx1 float
ury1 float
bound_dimension list
central_object object
color integer or string
list object_list
object_list list

ARGUMENTS
-name bound_name

Specifies the name of the bound.

-coordinate {llx1 lly1 urx1 ury1 ...}

Specifies rectangular move bounds by specifying the coordinates of the lower-left and upper-right corners for each rectangle. The
coordinates are in microns relative to the chip origin.

Each combination of {llx lly urx ury} defines a target placement area for the objects. The coarse placement engine can place cells in
any of the rectangles. These placeable areas can overlap or be disjoint.

You can specify rectilinear move bounds by dividing the rectilinear region into individual rectangular bounds and specifying the
rectangles in the coordinate list.

-dimension bound_dimension

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Specifies the dimension of a group bound or diamond bound in microns. The dimension of a group bound is specified as {width
height}, while the dimension of a diamond bound is specified as extent.

-diamond central_object

Creates a diamond bound centered on the specified object, which can be a port, cell, or pin.

The objects in the bound are constrained to lie within the distance specified by the -dimension option (measured as a Manhattan
distance) of the specified object. A diamond bound is always a soft bound.

If you specify this option, you must also specify the -dimension option.

-effort low | medium | high | ultra

Specifies the effort to bring cells closer inside a group bound.

The default is medium.

This option is mutually exclusive with the -coordinate and -dimension options.

-type soft | hard

Specifies the type of the bound to be either hard or soft.

To use this option, you must also specify either the -coordinate or -dimension option. The bound type cannot be set for
automatically generated group bounds or diamond bounds.

The default is soft.

-exclusive

Creates an exclusive move bound.

Exclusive move bounds require all of their cells to be placed inside them and prohibit the placement of other cells in the same area.
Exclusive move bounds are respected by both coarse placement and legalization.

-color color

Specifies the move bound color. You can specify the color either by specifying an integer value between 0 and 63 or by specifying
one of the following keywords: black, blue, green, cyan, brown, purple, red, magenta, salmon, orange, yellow, or white.

The default is no_color, meaning that no color is specified.

-cycle_color

Allows the tool to automatically assign a move bound color.

By default, this option is off.

-repelling diamond | rect

Specifies a bound to be repelling rather than attractive. A repelling bound specifies a floating area between a pair of objects to keep
them apart in the bound. You can specify either a diamond-shaped bound (diamond) or a rectangle-shaped bound (rect) for
specifying the shape of the repelling bound.

-groups list

Specifies a list of groups containing modules and leaf cells which will obey the repelling bound distance constraint in dual core lock
step (DCLS) designs. No ports are allowed in the groups, and an object may not appear in two different groups.

object_list

Specifies a list of cells, ports, and pins to be included in the bound.

If a cell is a hierarchical cell, the bound applies to all cells

in the subdesign.

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If a port is a hierarchical port, the corresponding port is attached to the bound instead.
If a pin is a leaf pin, the lower-left point of the first geometry of the pin is marked on the cell of the pin, and the cell is added to
the bound.
If a pin is a hierarchical pin, it is ignored.

A cell can be assigned to only one move bound; an error occurs if a specified cell already belongs to another move bound.

This argument is optional; you can create an empty move bound and later associate cells with it by using the update_bounds command.

DESCRIPTION
The create_bounds command allows you to define region-based placement constraints for coarse placement.

There are three types of bounds: move bounds, group bounds, and diamond bounds.

Move bounds restrict the placement of cells to a specific region of the core area.

To create a move bound, use the -coordinate option.

Group bounds are floating region constraints. Cells in the same group bound are placed within a specified bound, but the
absolute coordinates are not fixed. Instead, they are optimized by the placer.

To create a group bound, use the -dimension option.

Diamond bounds are region constraints centered on a specific object, which can be fixed or floating. Other objects in the same
diamond bound are placed within the specified Manhattan distance from the central object but their absolute coordinates are not
fixed. Instead, they are optimized by the placer.

To create a diamond bound, use the -diamond option together with the -dimension option.

If you do not use any of these options, the tool creates a group bound with a bounding box computed internally by the tool. In this
case, you can use the -effort option to specify the effort level used to bring the cells closer. All automatically generated bounds are
soft bounds; you cannot use the -type option to change the bound type for these group bounds.

Generally, there is no guarantee that cells are placed completely within the bounds. For instance, coarse placement can violate the
bounds if the quality of its primary placement objectives would otherwise be destroyed.

In these situations, you should revisit the bounds and floorplan to ensure that the design is not overconstrained. Alternatively, you can
use the -type hard option to specify the bound type to be hard. The default is soft. The coarse placer tries to honor the hard bound as
hard constraints while sacrificing other objectives, such as timing and routability. You should not use many hard bounds because this
can lead to inferior placement solutions.

The bounds created by the create_bounds command are persistent and do not need to be re-created when the design is reloaded.

Multicorner-Multimode Support
This command has no dependency on scenario-specific information.

EXAMPLES
The following example constrains the placement of the INST_1 instance to lie within the rectangle with its lower-left corner at (100,
100) and its upper-right corner at (200, 200):

prompt> create_bounds -name "temp" -coordinate {100 100 200 200} INST_1

The following example creates a hard rectilinear move bound on a hierarchical instance named INST2. The rectilinear move bound is
created as a set of two rectangles: one with its lower-left corner at (10, 10) and its upper-right corner at (30, 20), and one with its lower-
left corner at (20, 20) and its upper-right corner at (30, 30).

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prompt> create_bounds -name "temp2" \

-coordinate {10 10 30 20 20 20 30 30} \
-type hard INST_2

The following example creates a diamond bound centered on the pin MOD/U1/A. The cells MOD/INST1 and MOD/INST2 are
constrained to lie at most 64 microns of Manhattan distance away from MOD/U1/A.

prompt> create_bounds -name "temp3" \

-dimension 64 \
-diamond MOD/U1/A \
{MOD/INST1 MOD/INST2}

SEE ALSO
remove_bounds(2)
report_bounds(2)
set_cell_location(2)
update_bounds(2)

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create_bsd_patterns
Generates a set of functional patterns for a boundary-scan design.

SYNTAX
status create_bsd_patterns
-output test_program_name
[-effort low | medium | high]
[-type pattern_type]
[-setup_instructions instruction_list]
[-bsd_test_setup enable | disable]
[-jtag_reset enable | disable]

Data Types

test_program_name string
pattern_type string
instruction_list list

ARGUMENTS
-output test_program_name

Specifies the name of the output test program. On completion, create_bsd_patterns writes out the Synopsys pattern database
(test_program_name.vdb) file that contains the generated patterns and the fault status information. By default, the
test_program_name is design_name and the file is named design_name.vdb. This file is placed in the current working directory.

-effort low | medium | high

Controls the effort used to search for implemented instructions if the boundary-scan database has not been previously built by the
check_bsd, insert_dft, or read_bsdl command and the tool must infer the implemented instructions. For more information, see the
man page for the check_bsd command.

-type pattern_type

Generates vectors to test the various aspects of the boundary scan of the design.

This option allows you to generate vectors to test bsr, tap, tdr, and reset mechanisms of the boundary scan of the design
separately. This option allows generation of leakage vectors and all functional vectors (bsr, tap, tdr, and reset vectors). The option
also allows generation of vectors to test AC receivers and transmitters.

You must specify one of the following values:

all generates everything (the default).

functional generates {tap_controller, reset, bsr, tdr, ac_input_pulse, ac_input_train, ac_output_pulse, ac_output_train}.

dc_parametric generates vectors to {bsr, leakage}. Can also be used to measure voltage and current levels for I/O.

tap_controller generates vectors to test the tap finite state machine function.

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reset generates vectors to test the asynchronous and synchronous reset mechanism.

tdr generates vectors to test that each instruction implemented selects the corresponding test data register.

bsr generates vectors to test the function of the boundary scan register.

leakage generates vectors to test I/O leakage.

ac_input_pulse generates vectors for AC input tests with EXTEST_PULSE instruction. These vectors test the
preset/transition/single ended/dc behaviors of AC receivers and the DC behavior of the AC instruction.

ac_input_train generates vectors for AC input tests with EXTEST_TRAIN instruction. These vectors test the
preset/transition/single ended/dc behaviors of AC receivers and the DC behavior of the AC instruction.

ac_output_pulse generates vectors for AC output tests with EXTEST_PULSE instruction. These vectors test the transition
behavior of AC drivers with the AC instruction. The vectors also test AC/DC selection cells.

ac_output_train generates vectors for AC output tests with EXTEST_TRAIN instruction. These vectors test the transition
behavior of AC drivers with the AC instruction. The vectors also test AC/DC selection cells.

The default behavior is to generate both functional and DC parametric vectors. This is the same as running the command with the -
type all option.

-setup_instructions instruction_list

Specifies one or more user-defined instructions whose associated test data registers are to be initialized at the beginning of the test
program.

This method creates a test_setup procedure for the test program that initializates the user-defined test data registers (UTDRs)
associated with the specified instructions. The initialization data is be specified with the -bsd_init_data option of the
set_bsd_instruction command.

By default, no test_setup procedure is created. This option is mutually exclusive with the -bsd_test_setup option.

-bsd_test_setup enable | disable

Specifies that a custom test_setup procedure to be used for the test patterns.

This method inserts the test_setup section from the provided STIL protocol file into the created patterns. The setup protocol must
be read using the read_test_protocol -section test_setup command prior to pattern creation.

By default, no test_setup procedure is created. This option is mutually exclusive with the -setup_instructions option.

-jtag_reset enable | disable

Specifies whether to enable JTAG reset operations during the test program.

If you are using the -setup_instructions or -bsd_test_setup option to initialize configuration registers at the beginning of the test
program, and the configuration registers are affected by the JTAG reset signal, you can use the -jtag_reset disable option to
suppress JTAG resets during the test program.

When the -setup_instructions option is used, BSD Compiler creates a test_setup procedure that asserts the JTAG reset signal
before loading the specified configuration registers, but it suppresses all subsequent JTAG reset signals in the test program.

When the -bsd_test_setup option is used, you supply a custom test_setup procedure that is responsible for asserting JTAG reset
and initializing the configuration registers. BSD Compiler suppresses all subsequent JTAG reset signals in the test program.

If the tap_controller or reset type is specified with the -type option, the -jtag_reset disable option is ignored because the JTAG
reset signal must be asserted during these tests. If the all type is specified, the tap_controller and reset tests are omitted from the
test program.

This option can only be specified together with the -setup_instructions or -bsd_test_setup option.

By default, JTAG resets are enabled.

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DESCRIPTION
The create_bsd_patterns command generates functional test patterns for a boundary-scan design. If the boundary-scan database
was not previously built by the check_bsd, insert_dft, or read_bsdl command, the command performs an implicit compliance check
before proceeding. If a boundary-scan design is non-compliant, the create_bsd_patterns command does not generate any functional
vectors. If a boundary-scan design is compliant, the create_bsd_patterns command generates functional test patterns to test the
synchronous and asynchronous TAP reset, the TAP controller finite state machine, the implemented boundary-scan instructions and
associated test data registers, and the boundary-scan register.

If the design contains IEEE 1149.6 logic, the generated functional vectors also include tests for AC receivers and transmitters. Note
that these vectors are not generated if compliance checker is run prior to pattern generation.

The test patterns are stored in the Core Test Language (CTL) model for the design, which can be converted to different formats using
the write_test command.

EXAMPLES
The following example performs functional testbench generation on the current design and writes out the bscan.vdb Synopsys pattern
database:

prompt> create_bsd_patterns -out bscan

Loading db file '/u/root_dir/libraries/my_class.db'

Loading design 'M1'
...Starting IEEE 1149.1 Compliance Checking.
...Inferring the boundary scan protocol for the design 'M1'.
...Generating the BSD test patterns for the design 'M1'.
.....Generating vectors to test the asynchronous test logic reset.
.....Generating vectors to test the synchronizing sequence of 5 1's on tms.
.....Generating vectors to test the TAP FSM.
.....Generating vectors to test boundary scan instructions.
.......Generating vectors to test the 'BYPASS' instruction.
.......Generating vectors to test the 'EXTEST' instruction.
.......Generating vectors to test the 'SAMPLE' instruction.
.......Generating vectors to test the 'CLAMP' instruction.
.......Generating vectors to test the 'HIGHZ' instruction.
.......Generating vectors to test the 'IDCODE' instruction.
.....Generating vectors to test the boundary scan register.
...Writing test program bscan to file /tmp/bsdvec/bscan.vdb.

BSD test patterns are generated successfully.

SEE ALSO
check_bsd(2)
set_bsd_instruction(2)
write(2)
write_test(2)

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create_buffer_tree
Creates a buffer tree for the specified driver pins and nets.

SYNTAX
status create_buffer_tree
[-from pin_net_list]
[-incremental]
[-no_legalize]
[-on_route [-skip_detail_route]]
[-align_hierarchy_for_long_nets]

Data Types

pin_net_list collection

ARGUMENTS
-from pin_net_list

Specifies the driver pins and nets for which the tool creates buffer trees. When the -from option is not specified, the
create_buffer_tree command works on all drivers with a transitive fanout of 5 or more.

-incremental

Sets the scope of creating the buffer tree for the specified nets rather than the entire buffer tree driven by the specified nets. When
this option is specified, the create_buffer_tree command constructs a buffer tree, if needed, on each net specified by the -from
option to reduce the high fanout of each net, but it does not remove any existing buffers or inverters. So, the scope of creating buffer
trees is a single specified net.

-no_legalize

Disables placement legalization at the end of buffering. By default Design Compiler does not do placement legalization so the option
doesn't have any effect.

-on_route

Perform the postroute optimization flow, where it fixes DRC violations by using the route_opt command and then the focal_opt
command. It focuses mainly on fixing maximum net length, so you need to specify the max_net_length constraint by using the
set_max_net_length command, before using this option. The final database is a detail routed database.

It is recommended to use the -align_hierarchy_for_long_nets option with the -on_route option to ensure that optimization occurs
for long nets crossing logical hierarchies.

You can use the -from option with this option to fix DRC violations for the concentrated nets. However, if you use the -from option,
the design must be detail routed and you cannot use the -skip_detail_route or -align_hierarchy_for_long_nets options.

This option is not supported in Design Compiler topographical mode and will be ignored.

-skip_detail_route

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Skips detail routing when used with the -on_route option. By default the -on_route option triggers full detail routing after topology-
based DRC optimization. This option can reduce runtime of the on_route option by skipping the final detail route.

This option can only be used with the -on_route option. This option cannot be combined with the -from option.

This option is not supported in Design Compiler topographical mode and will be ignored.

-align_hierarchy_for_long_nets

Enables additional optimizations and port punching for long nets that crosses multiple hierarchies. Long nets are those nets that
violate the maximum net length constraint for the design. You can specify max_net_length constraint via command
set_max_net_length before using this option. If you use this option and the design does not have a maximum net length constraint,
the command fails with an error message.

When you use this option, the tool first performs high-fanout net fixing and also fixing DRC violations, such as maximum transition
and capacitance, for low fanout nets. It then performs preroute topology-based buffering and port punching for the nets that violate
the maximum net length constraint and crosses multiple hierarchies. If both of these conditions are not met, this additional
optimization is not performed.

This option does not fix all maximum net length constraint. You have to rely on the -on_route option to fix the remaining violations.

This option can be used alone or with the -on_route option, but it cannot be used with the -from options.

This option is not supported in Design Compiler topographical mode and will be ignored.

DESCRIPTION
The create_buffer_tree command creates a buffer tree for each specified driver pin and for the driver pin of each specified net.

The create_buffer_tree command generates a hierarchical buffer tree, and buffers are inserted across hierarchical boundaries. The
command is location-based. Therefore, the specified driver pin should not be a hierarchical pin because a hierarchical pin does not
have a location.

Use this command on a placed design only. The command requires the following libraries and information:

The physical libraries that correspond to the specified logic libraries.

The capacitance and resistance per unit length derived from the physical library or user-specified.

Multicorner-Multimode Support
This command uses information from all active scenarios.

EXAMPLES
The following example creates a buffer tree that is implemented at driver a/O:

prompt> create_buffer_tree -from [get_pins a/O]

The following example creates buffer trees for driver a/O and net n1:

prompt> create_buffer_tree -from {[get_pins a/O] [get_nets n1]}

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SEE ALSO
remove_buffer_tree(2)
report_buffer_tree(2)
report_ahfs_options(2)
report_net_fanout(2)
set_ahfs_options(2)

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create_bus
Creates a port bus or a net bus.

SYNTAX
status create_bus
object_list
bus_name
[-type type_name]
[-sort]
[-no_sort]
[-start start_bit]
[-end end_bit]

Data Types
object_list list
bus_name string
type_name string
start_bit integer
end_bit integer

ARGUMENTS
object_list

Specifies a list of ports or nets to be put into a bus. If both ports and nets have the same names, the ports are put into the bus.

This option is required.

bus_name

Specifies the name of the bus. This name cannot be the same as any other bus or object of the same type. Port bus names must
be different from the names of ports, and net bus names must be different from the names of nets.

This option is required.

-type type_name

Assigns the specified type_name to the bused port. Valid types are port or net. This name appears in port declarations when a
design with the bused ports is written to a file in the VHDL format. All buses that are assigned the same type name must be the
same width (contain the same number of members).

-sort

Sorts the bits of the bus specified in object_list in alphanumeric order. By default, bits sort in reverse alphanumeric order.

-no_sort

Specifies that the order of the bits in the bus should be the same as specified on the command line. By default, bits sort in reverse
alphanumeric order.

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-start start_bit

Specifies the start bit for the bus.

-end end_bit

Specifies the end bit for the bus.

DESCRIPTION
The create_bus command creates a bus object of the type port or net. The number of objects in the list determines the bus width.
Buses appear as multibit ports on a design or as multiwire nets in a design. This command groups any number of ports or any number
of nets into a bus object. Unless the -sort or -no_sort option is selected, the specified objects are sorted by reverse alphanumeric
order of names before the bus is created.

When using Design Vision to create a design schematic, bused nets are inferred from bused ports or pins in the design. Bused nets
only appear as nets in a schematic if they are connected to a bused port.

If the start bit and end bit for the bus are specified with the -start and -end options, the bus is created with these start and end indices.
If only the start bit is specified, an upward-going bus starting at that start bit is built. If only the end bit is specified, an upward-going bus
ending at that end bit is built.

EXAMPLES
This example groups the A1, A2, and A3 ports into a bus named A. The ports must already exist. The order in which the ports appear
in the bus is A3, A2, A1.

prompt> create_bus {A1 A2 A3} A

This example groups the B1, B2, and B3 nets into a bus named B. The nets must already exist and there must not be any ports with
the same names. The order in which the nets appear in the bus is B3, B2, B1.

prompt> create_bus {B1 B2 B3} B

This example groups the C1, C2, and C3 nets into a bus named C. The nets must already exist and because the object net is defined
in the get_nets command, it does not matter if there are ports with the same name. The order in which the nets appear in the bus is
C3, C2, C1.

prompt> create_bus [get_nets C1 C2 C3] C

This example groups the existing D1, D2, and D3 ports into a bus named D and assigns the 3-bit type to the bus:

prompt> create_bus {D1 D2 D3} D -type "3-bit"

This example groups the existing D1, D2, and D3 ports into a bus named D and assigns it the index range 6-to-4. Port D1 is assigned
index 6, port D2 to index 5, and port D3 to index 4.

prompt> create_bus {D1 D2 D3} D -start 6 -end 4

This example groups the E1, E2, and GH ports into a bus named E. The ports must already exist. Because the -sort option is used,
the first bit is port E1, the second bit is port E2, and the third bit is port GH.

prompt> create_bus {E2 GH E1} E -sort

This example groups the R1, R2, and GH ports into a bus named R. The ports must already exist. Because the -no_sort option is
used, the first bit is port R1, the second bit is port R2, and the third bit is port GH.

prompt> create_bus {R1 R2 GH} R -no_sort

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This example groups the ports in the MID subdesign into a bus named NEW. U1 is a unique instantiation of MID.

prompt> create_bus {U1/R1 U1/R2 U1/GH} NEW -no_sort

This example groups the nets in the MID subdesign into a bus named NET_BUS. U1 is a unique instantiation of MID.

prompt> create_bus [get_nets U1/R1 U1/R2 U1/GH] NET_BUS -no_sort

SEE ALSO
get_nets(2)
remove_bus(2)
report_bus(2)

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create_cell
Creates leaf or hierarchical cells in the current design or its subdesigns.

SYNTAX
status create_cell
cell_list
[reference_name]
[-hierarchical]
[-logic 0 | 1]
[-only_physical]

Data Types

cell_list list
reference_name string

ARGUMENTS
cell_list

Specifies the names of cells created in the current design. Each cell name must be unique within the current design.

reference_name

Specifies the design or library cell that new cells reference. You must specify the reference_name unless you use the -logic option.
Ports on the reference determine the name, number, and direction of pins on the new cell.

-hierarchical

Creates hierarchical cell instances and designs with the name given by cell_list if the reference_name is not specified.

If you specify the reference_name, the cell_list must have a single element. The command creates the hierarchical cell instance
with the name given by the single cell_list and also creates the design with the name given by reference_name.

-logic 0 | 1

Specifies that the new cell generates a logic 0 or logic 1 value. The logic value must be either 0 or 1. By using this option, the cell
contains a single output pin. By default, this option is off.

-only_physical

Creates a new physical or physical-only cell using a reference from the physical library. The -only_physical option sets the
is_physical_only attribute on the created physical-only cell. After you create a physical-only cell, you must assign a location to that
cell. Unlike physical cells with logic functions, the tool does not assign a location to a physical-only cell during synthesis. To assign
a location, use the set_cell_location command, Tcl commands, or a DEF file. By default, this option is off.

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DESCRIPTION
This command creates new leaf or hierarchical cells in the current design or its subdesigns based on the cell_list argument. New leaf
cells are the instantiation of an existing design or library cell. New hierarchical cells are the instantiation of a new design. New cells are
the instantiation of an existing design, a library cell, a logic 0 generator, or a logic 1 generator.

The created cells are unplaced. To be viewed properly in the GUI, the cells must be placed either manually by using the
set_cell_location command or automatically by using placement commands.

To remove cells from the current design, use the remove_cell command.

Although the reference_name argument accepts names in the format library/library_cell, the command might not instantiate the actual
library cell from the specified library. The actual library cell to be used is determined by the current link library settings.

EXAMPLES
The following example creates a cell named cell1 under the subdesign corresponding to the mid1 cell:

prompt> create_cell {mid1/cell1} my_lib/AND2

Creating cell 'cell1' in design 'mid'.

The following example creates a cell named cell2 in the design corresponding to the m1/U1 and m2/U1 instances. The cell names
cell2 is a logic 0 generator. The design corresponding to m1/U1 and m2/U1 must be unique.

prompt> create_cell {m1/U1/cell2 m2/U1/cell2} -logic 0

The following example creates cells using existing designs as references:

prompt> create_design ALPHA

prompt> current_design ALPHA

prompt> create_cell U1 ADDER

prompt> create_cell U2 SUBTRACTOR

The following example creates logic 1 and logic 0 cells:

prompt> create_cell LOGIC_ONE -logic 1

prompt> create_cell LOGIC_ZERO -logic 0

The following example creates leaf cells using library cells as references.

prompt> create_cell {U3 U4} my_lib/NAND2

prompt> create_cell "U5" my_lib/NOR2

The following example creates hierarchical cell H1 with the new design name DESIGN1, and creates leaf cell U2 under the new
hierarchical cell using library cells as references:

prompt> create_cell -hierarchical H1 DESIGN1

prompt> create_cell H1/U2 my_lib/NAND2

The following example creates hierarchical cells H2 and H3 with the design name H2 and H3 separately. Also, it creates leaf cell U3
under the new hierarchical cell H2 using library cells as references.

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prompt> create_cell -hierarchical {H2 H3}

prompt> create_cell H2/U3 my_lib/NAND2

The following example creates physical cells using physical library cells as references:

prompt> create_cell -only_physical {U3 U4} lib.pdb:my_lib/pad0

prompt> create_cell -only_physical phys_inst1 test_lib.pdb:mylib/PAD0

SEE ALSO
current_design(2)
remove_cell(2)
report_cell(2)
set_cell_location(2)

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create_clock
Creates a clock object and defines its waveform in the current design.

SYNTAX
status create_clock
[-name clock_name]
[-add]
[source_objects]
[-period period_value]
[-waveform edge_list]
[-comment comment_string]

Data Types

clock_name string
source_objects list
period_value float
edge_list list
comment_string string

ARGUMENTS
-name clock_name

Specifies the name of the clock being created. If you do not use this option, the clock is given the same name as the first clock
source specified in source_objects. If you do not use source_objects, you must use this option, which creates a virtual clock not
associated with a port or pin. Use this option along with source_objects to give the clock a more descriptive name than that of the
pin or port where it is applied.

If you specify the -add option, you must use the -name option and the clocks with the same source must have different names.

-add

Specifies whether to add this clock to the existing clock or to overwrite the existing clock. Use this option to capture the case where
multiple clocks must be specified on the same source for simultaneous analysis with different clock waveforms. When you specify
this option, you must also use the -name option. Defining multiple clocks on the same source pin or port causes longer runtime and
higher memory usage than a single clock, because the synthesis timing engine must explore all possible combinations of launch
and capture clocks. Use the set_false_path command to disable unwanted clock combinations. This option is ignored (the default),
unless multiple clocks analysis is enabled by setting the timing_enable_multiple_clocks_per_reg variable to true.

source_objects

Specifies a list of pins or ports on which to apply this clock. If you do not use this option, you must use -name clock_name, which
creates a virtual clock not associated with a port or pin. If you specify a clock on a pin that already has a clock, the new clock
replaces the old clock unless you use the -add option.

-period period_value

Specifies the period of the clock waveform in library time units.

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-waveform edge_list

Specifies the rise and fall edge times, in library time units, of the clock over an entire clock period. The first time in the list is a rising
transition, typically the first rising transition after time zero. There must be an even number of increasing times, and they are
assumed to be alternating rise and fall times. The numbers must represent one full clock period. If -waveform edge_list is not
specified, but -period period_value is, a default waveform with a rise edge of 0.0 and a fall edge of period_value/2 is assumed.

-comment comment_string

Allows the command to accept a comment string. The tool honors the annotation and preserves it with the SDC object so that the
exact string is written out when the constraint is written out when you use the write_sdc or write_script command. The comment
remains intact through the synthesis, place-and-route, and timing-analysis flows.

DESCRIPTION
The create_clock command creates a clock object in the current design. The command defines the specified source_objects as clock
sources in the current design. A pin or port can be a source for a single clock. If source_objects is not specified, but a clock_name is
given, a virtual clock is created. A virtual clock can be created to represent an off-chip clock for input or output delay specification. For
more information about input and output delay, refer to the set_input_delay and set_output_delay command man pages.

Clock objects hold attributes that affect the clock network, such as dont_touch_network, fix_hold, and propagated_clock. Using
create_clock on an existing clock object overwrites the attributes previously set on the clock object. The create_clock command also
defines the waveform for the clock. The clock can have multiple pulses per period