Computer Architecture (BCAC201) -

Detailed Notes
Unit 1: Data Representation

Number Systems
 Decimal (Base-10): The standard system for denoting integer and non-integer numbers.
Uses digits from 0 to 9.
 Binary (Base-2): Used internally by almost all modern computers and computer-based
devices. Consists of only two digits: 0 and 1.
 Octal (Base-8): Uses digits from 0 to 7. Each octal digit corresponds to exactly three
binary digits.
 Hexadecimal (Base-16): Uses digits 0 to 9 and letters A to F. Each hex digit represents
four binary digits.
 Alphanumeric Representation: Includes letters and numbers. Used for data such as
ASCII (American Standard Code for Information Interchange).

Complements
 1’s Complement: Invert all the bits of a binary number.
 2’s Complement: Add 1 to the 1’s complement of a binary number. Used for
representing negative numbers in binary.
 9’s Complement: Subtract each digit of a number from 9. Used in decimal subtraction.
 10’s Complement: Add 1 to the 9’s complement.
 [r-1]’s and r’s Complement: Generalized form used for numbers in base-r.

Fixed Point Representation

 Represents real numbers with a fixed number of digits after (or before) the decimal
point.
 Used for integers or real numbers with a fixed fractional part.
 Includes representation of positive and negative numbers and handling overflow.

Floating Point Representation

 Used for very large or small real numbers. Represented using a sign bit, exponent, and
mantissa.
 Example: 1.5 = 1.1 × 2^0 in binary floating point.

IEEE 754 Floating Point Representation

 Single Precision (32-bit): 1 bit for sign, 8 bits for exponent, 23 bits for fraction.
 Double Precision (64-bit): 1 bit for sign, 11 bits for exponent, 52 bits for fraction.
 Includes special cases like 0, infinity, NaN (Not a Number).
Unit 2: Computer Arithmetic

Arithmetic Operations
 Addition/Subtraction of Sign Magnitude Numbers: The sign bits are compared first. If
same, magnitudes are added; if different, smaller magnitude is subtracted from larger.
 2's Complement Addition: Add the numbers including sign bits. Discard final carry.
 2's Complement Subtraction: Convert subtrahend to its 2’s complement and add to
minuend.

Multiplication Algorithms
 Binary Multiplication: Repeated addition of multiplicand and shifting.
 Booth’s Algorithm: Handles signed multiplication efficiently by encoding runs of 1s in
the multiplier.

Division Algorithms
 Restoring Division: Subtract divisor, check sign, restore if needed.
 Non-Restoring Division: Avoids the restoring step, slightly faster in some cases.

Overflow Detection
 Occurs when the result exceeds the range representable with given bits.
 For 2’s complement: If adding two positives yields a negative or two negatives yield a
positive.

Unit 3: Register Transfer and Micro-Operations

Register Transfer Language (RTL)

 Used to specify micro-operations in symbolic form.
 Example: T1: MAR <- PC

Bus System for Registers

 Common bus connects multiple components. Reduces number of pathways needed.

Memory Transfers
 Memory Read: Data from memory copied to register.
 Memory Write: Data from register stored into memory.

Micro-Operations
 Arithmetic: ADD, SUB, INC, DEC.
 Logic: AND, OR, XOR, NOT.
 Shift: Logical, Arithmetic, Circular.
 Register Transfer: Moving data between registers.
Other Circuits
 Binary Adder/Subtractor: Performs addition or subtraction based on control input.
 Incrementer: Adds 1 to binary number.
 Masking: Used to clear or set specific bits.
 Selective Set/Clear: Operates on selected bits.

Unit 4: Basic Computer Organization and Design

Instruction Codes
 Binary codes that represent operations to be performed by the CPU.
 Each instruction has an operation code (opcode) and operands.

Basic Registers
 AC (Accumulator), DR (Data Register), AR (Address Register), PC (Program Counter), IR
(Instruction Register).

Addressing Modes
 Direct Addressing: Address of operand is given directly.
 Indirect Addressing: Address field points to a location holding the actual address.
 Effective Address: Final memory address computed.

Instruction Types
 Memory Reference Instructions: Involve memory operations.
 Register Reference Instructions: Operate on data in registers.
 I/O Instructions: Used for input/output operations.

Instruction Cycle
 Fetch: Get instruction from memory.
 Decode: Identify operation.
 Execute: Perform the instruction.
 Store: Save result.

Unit 5: Microprogrammed Control

Control Memory
 Stores the microprograms that define the control signals for instruction execution.
 Each location in control memory contains a microinstruction.

Microinstructions and Microprograms

 Microinstruction: A set of control signals represented in binary.
 Microprogram: Sequence of microinstructions that implement the machine instruction.
Address Sequencing
 Determines the next microinstruction address.
 Can be determined by incrementing, branching, or conditional branching.

Advantages of Microprogrammed Control

 Easier to modify and debug.
 Simplifies control unit design for complex instructions.

Unit 6: Central Processing Unit

General Register Organization

 CPU contains multiple general-purpose registers for temporary data storage.
 ALU operations performed using registers and controlled by control unit.

Stack Organization
 Memory organized as a stack; LIFO (Last In First Out) structure.
 Operations include PUSH (insert) and POP (remove).

Instruction Formats
 Define how instruction is encoded.
 Include opcode field, operand fields, and mode fields.

Types of CPU Organizations

 Single Accumulator: All operations done using a single register.
 General Register: Uses multiple registers.
 Stack Organization: Operands are implicitly on the top of the stack.

Instruction Types
 Three-address, Two-address, One-address, and Zero-address instructions vary in
number of operands.

Instruction Classification
 Data Transfer: MOV, LOAD, STORE.
 Data Manipulation: ADD, SUB, AND.
 Program Control: JUMP, CALL, RETURN.

Interrupts
 External: Triggered by external devices.
 Internal: Caused by CPU operations (e.g., overflow).
 Software: Triggered by software instruction.

RISC vs CISC
 RISC: Reduced Instruction Set Computer, simple instructions, faster execution.
 CISC: Complex Instruction Set Computer, more powerful instructions, fewer lines of
code.

Unit 7: Pipeline and Vector Processing

Flynn’s Classification
 SISD: Single Instruction, Single Data.
 SIMD: Single Instruction, Multiple Data.
 MISD: Multiple Instruction, Single Data.
 MIMD: Multiple Instruction, Multiple Data.

Pipelining
 Technique where multiple instructions are overlapped in execution.
 Stages: Fetch, Decode, Execute, Memory Access, Write Back.

Space-Time Diagram
 Graphical representation showing execution stages across time.

Speedup
 Speedup = Time without pipeline / Time with pipeline.
 Ideal speedup equals the number of pipeline stages.

Arithmetic Pipeline
 Breaks down complex arithmetic operations into stages for faster execution.
 Used in floating point operations.

Unit 8: Input – Output Organization

Peripheral Devices
 Devices like keyboard, mouse, monitor, printer, etc.

Input – Output Interfaces

 Connect I/O devices to CPU and memory.
 Handles communication and data transfer.

I/O Techniques
 Isolated I/O: Separate address space for I/O.
 Memory Mapped I/O: I/O devices share memory address space.

Asynchronous Data Transfer

 Strobe Method: Uses single control line.
 Handshaking Method: Uses request and acknowledge lines for safe transfer.
I/O Modes
 Programmed I/O: CPU actively waits and checks I/O status.
 Interrupt I/O: Device interrupts CPU when ready.
 DMA (Direct Memory Access): Transfers data directly without CPU involvement.

Unit 9: Memory Organization

Memory Hierarchy
 Registers → Cache → Main Memory → Secondary Storage.
 Trade-off between speed, cost, and size.

Main Memory
 RAM: Volatile memory, fast access. Types: SRAM (faster), DRAM (cheaper).
 ROM: Non-volatile memory used to store firmware.

Cache Memory
 Stores frequently accessed data for faster CPU access.
 Mapping Techniques: Direct Mapping, Associative Mapping, Set-Associative Mapping.

CAM (Content Addressable Memory)

 Data is accessed based on content rather than address.
 Used in associative memory and TLB.

Virtual Memory
 Extends RAM using disk storage.
 Uses paging and segmentation. Handles page faults using TLB.

Auxiliary Memory
 Non-volatile memory like hard disks, optical drives, magnetic tapes.

Timing Terminologies
 Seek Time: Time to move to correct track.
 Rotational Delay: Wait for correct sector to rotate.
 Access Time = Seek Time + Rotational Delay.
 Transfer Time: Time to move data.
 Latency: Overall delay.