MCS-012 Solved Assignment 2024-25 | learningscience.co.

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Course Code : MCS-012

Course Title : Computer Organisation and Assembly Language Programming

Assignment Number : BCA(II)/012/Assignment/2024-25

Maximum Marks : 100

Weightage : 25%

Last Dates for Submission : 31st October, 2024 (For July Session) 30th April, 2025 (For
January Session)

Note:

There are four questions in this assignment, which carries 80 marks. Rest 20 marks are for
viva voce. You may use illustrations and diagrams to enhance the explanations. Please go
through the guidelines regarding assignments given in the Programme Guide for the format
of the presentation. The answer to each part of the question should be confined to about
300 words. Make suitable assumptions, if any.

Question 1:

(a) Please refer to Figure 4 of Unit 1 of Block 1 on page 11 of the Instruction execution
example. Assuming a similar machine is to be used for the execution of the following three
consecutive instructions:

LOAD A ; Load the content of Memory location A into the Accumulator Register.

ADD B ; Add the content of memory location B to Accumulator Register.

STOR C ; Stores the content of the Accumulator register to memory location C.

However, this machine is different from the example in Figure 4 in the following ways:

 Each memory word of this new machine is of 32 bits length.

 Each instruction is of length 32 bits with 12 bits for operation code (opcode) and 20
bits for specifying one direct operand. The size of operand is 32 bits.
 The Main Memory of the machine is of size 220 words.
 The three consecutive instructions are placed starting from memory location
(11FFE)h ; operand A is at location (2FFFF)h and contains a value (111AB4C1)h,
Operand B is at location (30000)h and contains a value (AAA1A1FE)h and operand C
is at location (30001)h and contains a value (00000000)h.
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 2

 The AC, IR, MAR and MBR registers are of size 32 bits, whereas PC register is of size
20 bits. The initial content of the PC register is (11FFE)h.

(i) Draw a diagram showing the Initial State of the machine with the addresses and content
of memory locations in hexadecimal. Show only those address locations of the memory that
store the instruction and data. Also, show the content of all the stated registers. (2 Marks)

(ii) Draw three more diagrams, each showing the state of the machine after execution of
every instruction viz. LOAD, ADD and STOR. Show the changes in the values of Registers and
memory locations, if any, due to the execution of the instruction. Show all the addresses and
values in hexadecimal notations. (3 Marks)

Solution:

Machine Specifications Recap:

 Memory word size: 32 bits

 Instruction size: 32 bits (12 bits for opcode, 20 bits for operand)
 Main memory size: 2^20 words
 Starting memory location of instructions: 11FFEh
 Memory locations and data:
o Operand A at location 2FFFFh contains 111AB4C1h
o Operand B at location 30000h contains AAA1A1FEh
o Operand C at location 30001h contains 00000000h
 Register sizes: AC, IR, MAR, MBR are 32 bits; PC is 20 bits.
 Initial PC: 11FFEh

(i) Initial State of the Machine:

Memory:

 Instruction at 11FFEh: LOAD A (opcode for LOAD and operand pointing to A at

2FFFFh)
 Instruction at 11FFFh: ADD B (opcode for ADD and operand pointing to B at
30000h)
 Instruction at 12000h: STOR C (opcode for STOR and operand pointing to C at
30001h)
 Memory location 2FFFFh: 111AB4C1h (data for operand A)
 Memory location 30000h: AAA1A1FEh (data for operand B)
 Memory location 30001h: 00000000h (initial data for operand C)

Registers:

 PC: 11FFEh (pointing to the first instruction)

 AC: Empty (not yet loaded with data)
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 3

 IR: Empty (not yet loaded with instruction)

 MAR: Empty (not yet pointing to any memory address)
 MBR: Empty (not yet containing memory data)

Diagram 1: Initial State (Before Execution)

(ii) After Executing Each Instruction:

1. Instruction 1: LOAD A

 PC increments to 11FFFh (next instruction).

 IR is loaded with the contents at 11FFEh (LOAD A).
 MAR is set to 2FFFFh (operand A’s address).
 MBR is loaded with the value from 2FFFFh, i.e., 111AB4C1h.
 AC is updated with the value from MBR, i.e., 111AB4C1h.

Diagram 2: After LOAD A

 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 4

2. Instruction 2: ADD B

 PC increments to 12000h (next instruction).

 IR is loaded with the contents at 11FFFh (ADD B).
 MAR is set to 30000h (operand B’s address).
 MBR is loaded with the value from 30000h, i.e., AAA1A1FEh.
 AC is updated with the sum of AC and MBR, i.e., 111AB4C1h + AAA1A1FEh =
BBCC566Fh.

Diagram 3: After ADD B

 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 5

3. Instruction 3: STOR C

 PC increments to 12001h (next instruction, although no more instructions are

given).
 IR is loaded with the contents at 12000h (STOR C).
 MAR is set to 30001h (operand C’s address).
 MBR is loaded with the current value of AC, i.e., BBCC566Fh.
 The value from MBR is stored at memory location 30001h.

Diagram 4: After STOR C

 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 6

Q1 (b) Perform the following conversion of numbers: (2 Marks)

i) Decimal (345789531)10 to binary and hexadecimal.

ii) Hexadecimal (ABC023DEF)h into Octal.

iii) String “MCS-12 Price in $” into UTF 8. iv) Octal (12076543)O into Decimal.

Solution:

Step 1: Convert Decimal to Binary

To convert 345789531₁₀ into binary, I repeatedly divide the number by 2 and record the
remainders:

 345789531 ÷ 2 = 172894765 remainder 1

 172894765 ÷ 2 = 86447382 remainder 1
 86447382 ÷ 2 = 43223691 remainder 0
 43223691 ÷ 2 = 21611845 remainder 1
 21611845 ÷ 2 = 10805922 remainder 1
 10805922 ÷ 2 = 5402961 remainder 0
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 7

 5402961 ÷ 2 = 2701480 remainder 1

 2701480 ÷ 2 = 1350740 remainder 0
 1350740 ÷ 2 = 675370 remainder 0
 675370 ÷ 2 = 337685 remainder 0
 337685 ÷ 2 = 168842 remainder 1
 168842 ÷ 2 = 84421 remainder 0
 84421 ÷ 2 = 42210 remainder 1
 42210 ÷ 2 = 21105 remainder 0
 21105 ÷ 2 = 10552 remainder 1
 10552 ÷ 2 = 5276 remainder 0
 5276 ÷ 2 = 2638 remainder 0
 2638 ÷ 2 = 1319 remainder 0
 1319 ÷ 2 = 659 remainder 1
 659 ÷ 2 = 329 remainder 1
 329 ÷ 2 = 164 remainder 1
 164 ÷ 2 = 82 remainder 0
 82 ÷ 2 = 41 remainder 0
 41 ÷ 2 = 20 remainder 1
 20 ÷ 2 = 10 remainder 0
 10 ÷ 2 = 5 remainder 0
 5 ÷ 2 = 2 remainder 1
 2 ÷ 2 = 1 remainder 0
 1 ÷ 2 = 0 remainder 1

Reading the remainders from bottom to top, 345789531₁₀ in binary is:

10100100100111111011011000011₂

Step 2: Convert Decimal to Hexadecimal

To convert 345789531₁₀ into hexadecimal, I repeatedly divide the number by 16 and

record the remainders:

 345789531 ÷ 16 = 21611845 remainder 11 (B)

 21611845 ÷ 16 = 1350740 remainder 5
 1350740 ÷ 16 = 84308 remainder 4
 84308 ÷ 16 = 5269 remainder 4
 5269 ÷ 16 = 329 remainder 5
 329 ÷ 16 = 20 remainder 9
 20 ÷ 16 = 1 remainder 4
 1 ÷ 16 = 0 remainder 1

Reading the remainders from bottom to top, 345789531₁₀ in hexadecimal is:

149454B₁₆
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 8

Q1 (b) ii) Convert Hexadecimal (ABC023DEF)₁₆ to Octal:

To convert the hexadecimal number ABC023DEF₁₆ into octal, I first convert it into binary,
then group the bits in sets of three (since octal is base 8).

Step 1: Convert Hexadecimal to Binary

Each hexadecimal digit is represented by 4 binary digits:

 A = 1010
 B = 1011
 C = 1100
 0 = 0000
 2 = 0010
 3 = 0011
 D = 1101
 E = 1110
 F = 1111

So, ABC023DEF₁₆ in binary is:

101010111100000000100011110111101111₂

Step 2: Convert Binary to Octal

Now, group the binary digits in sets of three starting from the right:

 101010111100000000100011110111101111 = 010 101 011 110 000 000 010 001

111 011 110 111

Converting each group to octal:

 010 = 2
 101 = 5
 011 = 3
 110 = 6
 000 = 0
 000 = 0
 010 = 2
 001 = 1
 111 = 7
 011 = 3
 110 = 6
 111 = 7
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 9

Thus, ABC023DEF₁₆ in octal is:

253600217367₈

Q1 (b) iii) Convert the string "MCS-12 Price in $" into UTF-8:

In UTF-8 encoding, each character is represented by a series of bytes. Here's the

breakdown for the string "MCS-12 Price in $":

So, the string "MCS-12 Price in $" in UTF-8 is:

4D 43 53 2D 31 32 20 50 72 69 63 65 20 69 6E 20 24
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 10

Q1 (b) iv) Convert Octal (12076543)₈ to Decimal:

To convert the octal number 12076543₈ into decimal, I use the expansion method, where
each digit is multiplied by 8 raised to the power of its position (starting from 0 on the
right).

12076543₈ = 1×8⁷ + 2×8⁶ + 0×8⁵ + 7×8⁴ + 6×8³ + 5×8² + 4×8¹ + 3×8:

= 1×2097152 + 2×262144 + 0×32768 + 7×4096 + 6×512 + 5×64 + 4×8 + 3×1

= 2097152 + 524288 + 0 + 28672 + 3072 + 320 + 32 + 3

= 2629539

Thus, 12076543₈ in decimal is:

2629539₁₀

Q1 (c) Simplify the following function using K-map: F(A, B, C, D) = Σ (0, 1, 2, 4, 8, 9, 10, 13)
Draw the circuit for the resultant function using NAND gates. (2 Marks)

Solution:

Create the K-map

The function involves 4 variables: A, B, C, and D. This means we will need a 4-variable K-
map, which has 16 cells (2⁴ = 16 cells). I will label the cells based on the binary
combinations of the variables (AB for rows, CD for columns).

The minterms given are: 0, 1, 2, 4, 8, 9, 10, 13

AB\CD 00 01 11 10
00 1 1 - 1
01 1 - 1 -
11 - - - -
10 1 1 - -

Group the 1's on the K-map

I can simplify the function by grouping adjacent 1's into the largest possible groups of 2ⁿ
cells. Here are the groups:
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 11

 Group 1 (top-left corner 4 cells): This group covers minterms 0, 1, 8, and 9. The
simplified expression for this group is A'C'.
 Group 2 (middle top 2 cells): This group covers minterms 2 and 10. The simplified
expression for this group is A'B'C.
 Group 3 (bottom-left 2 cells): This group covers minterms 4 and 5. The simplified
expression for this group is B'D'.

Write the simplified function

The simplified Boolean expression for the function F(A, B, C, D) is:

F(A, B, C, D) = A'C' + A'B'C + B'D'

Circuit Diagram using NAND Gate:

Q1 (d) Consider the Adder-Subtractor circuit as shown in Figure 3.15 page 76 of Block 1.
What would be the values of various inputs and outputs; viz. Cin input to each full adder, A0,
B0, A1, B1, A2, B2, A3, B3, S0, S1, S2, S3, Carry out bit, and overflow condition; if this circuit
performs subtraction (A-B), when the value of A is 1010 and B is 1011. (1 Mark)

Solution:

Inputs:
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 12

 A = 1010 (binary for decimal 10)

 B = 1011 (binary for decimal 11)

Since the operation is subtraction, the circuit will compute A - B, which is 10102−101121010_2 -
1011_210102−10112.

Step-by-Step Analysis:

1. Two's Complement of B:
o First, we calculate the two's complement of B=1011B = 1011B=1011.
 Invert the bits of B: 010001000100
 Add 1 to the result: 0100+1=01010100 + 1 = 01010100+1=0101 (This is
the two's complement of BBB).
2. Subtraction Using Full Adders:
o We now add A=1010A = 1010A=1010 and the two's complement of B=0101B =
0101B=0101.

Full Adder Inputs and Outputs:

Bit A B Two's Complement of B Cin (Carry Sum Cout (Carry

Position (Input) (Input) (Input) In) (S) Out)
0 0 1 0 1 1 0
1 1 1 0 0 1 1
2 0 0 1 1 0 0
3 1 1 0 0 0 1

Final Results:

 S0 = 1
 S1 = 1
 S2 = 0
 S3 = 0
 Carry Out = 1

Overflow Condition:

 The overflow condition occurs when there is a carry into the most significant bit but no
carry out, or vice versa. In this case, both the carry into and carry out of the most significant
bit (bit 3) are 0, so overflow does not occur.

Q1 (e) Explain the functioning of a 2 × 4 decoder with the help of a logic diagram and an
example input. (2 Marks)

Solution:
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 13

A 2×4 decoder is a digital circuit that converts 2 input lines into 4 output lines, where each
output represents one of the possible combinations of the inputs. The inputs are typically
labeled A and B, and the outputs are Y0, Y1, Y2, and Y3. The truth table of a 2×4 decoder is
as follows:

 For input A=0, B=0 → Y0=1

 For input A=0, B=1 → Y1=1
 For input A=1, B=0 → Y2=1
 For input A=1, B=1 → Y3=1

Only one output is active at a time, depending on the combination of inputs. The logic
diagram typically includes two NOT gates and four AND gates. The outputs are formed by
AND gates based on combinations of inputs and their complements.

For example, for input A=1 and B=0, Y2 will be activated, meaning the corresponding AND
gate produces an output of 1, while all other outputs remain 0

Q1 (f) Assume that a source data value 1111 was received at a destination as 1011. Show
how Hamming's Error-Correcting code bits will be appended to source data to identify and
correct the error of one bit at the destination. You may assume that transmission error
occurs only in the source data and not the source parity bits. (2 Marks)
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 14

Solution:

Given that the original source data was 1111 and was received as 1011, the error occurred
in one of the bits.

Hamming Code works by adding redundancy bits (parity bits) at specific positions to the
source data. These parity bits help detect and correct errors. The number of parity bits
needed for error detection and correction is given by the formula:

2r ≥ m + r + 1

Where:

 r is the number of parity bits

 m is the number of data bits (4 in this case)

For a 4-bit data, at least 3 parity bits are needed since 23 = 8 ≥ 4 + 3 + 1

Position the Parity Bits

I insert the parity bits at positions that are powers of 2 (i.e., positions 1, 2, and 4 in the 7-bit
sequence):

 P1 at position 1
 P2 at position 2
 P4 at position 4

The data bits (D) are placed in the remaining positions:

 D3 at position 3
 D5 at position 5
 D6 at position 6
 D7 at position 7

So, the structure becomes: P1 P2 D3 P4 D5 D6 D7.

Calculate Parity Bits for the Source Data

Using the source data 1111, I place the bits in the data positions:

Position 1 2 3 4 5 6 7
Value P1 P2 1 P4 1 1 1

I now calculate the values for P1, P2, and P4 by ensuring each parity bit covers the
appropriate set of bits:
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 15

 P1 covers positions 1, 3, 5, 7:

P1 = 1 ⊕ 1 ⊕ 1 = 1

 P2 covers positions 2, 3, 6, 7:

P2 = 1 ⊕ 1 ⊕ 1 = 1

 P4 covers positions 4, 5, 6, 7:

P4 = 1 ⊕ 1 ⊕ 1 = 1

Thus, the final 7-bit transmitted code is 1111111.

Received Data and Error Detection

The received data is 1011111. To detect the error, I calculate the parity bits at the
destination and compare them with the parity bits in the received data.

1. P1 covers positions 1, 3, 5, 7:

P1′ = 1 ⊕ 1 ⊕ 1 = 1

No error detected by P1.

2. P2 covers positions 2, 3, 6, 7:

P2′ = 0 ⊕ 1 ⊕ 1 = 0

Error detected by P2.

3. P4 covers positions 4, 5, 6, 7:

P4′ = 1 ⊕ 1 ⊕ 1 = 1

No error detected by P4.

Identify and Correct the Error

The error syndrome is formed by combining the results from the parity checks:

Syndrome = P4′ P2′ P1′ = 010

This points to position 2 (binary 010), indicating that the second bit is in error. I flip the
second bit of the received data 1011111, correcting it to 1111111, which matches the
original transmitted data.
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 16

Q1 (g) Explain the functioning of the RS flip flop with the help of a logic diagram and
characteristic table. Also, explain the excitation table of this flip-flop. (2 Marks)

Solution:

The RS (Reset-Set) flip-flop is a fundamental memory element used in digital electronics,

and it can be constructed using NAND or NOR gates. Here's a brief explanation:

1. Functioning:
o In the SET state (S = 1, R = 0), the output Q is 1, and the flip-flop stores a "1."
o In the RESET state (S = 0, R = 1), the output Q is 0, and it stores a "0."
o When both S and R are 0, it leads to an invalid or undefined state in the RS
flip-flop using NOR gates, while using NAND gates, both outputs remain "1."

2. Characteristic Table: This table defines the next state of the output based on the
current inputs (S, R) and the current state (Q). For example:
o S=0, R=0: No change.
o S=0, R=1: Reset.
o S=1, R=0: Set.
o S=1, R=1: Invalid state (for NOR gates).
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 17

3. Excitation Table: This table provides the necessary inputs (S, R) to transition from
the current state to the next state, helping in the design of sequential circuits.

Q1 (h) Explain the functioning of the master-slave flip-flop with the help of a diagram. (2
Marks)

Solution:

Whenever the CLK pulse goes to high which means 1, then the slave can be separated; the
inputs like J & K may change the condition of the system.
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 18

The slave FF can be is detached until the CLK pulse goes to low which means to 0.
Whenever the CLK pulse goes back to low-state, then the data can be transmitted from the
master FF to the slave FF and finally, the o/p can be obtained.

At first, the master FF will be triggered at a positive level whereas the slave FF will be
triggered at a negative level. Due to this reason, the master FF responds first.

If J=0 & K=1, then the output of the master FF ‘Q’ goes to the input K of the slave FF & the
CLK forces the slave FF to RST (reset), therefore the slave FF copies the master FF.

If J=1 & K=0, then the of the master FF ‘Q’ goes to the input J of the slave FF & the CLK’s
negative transition sets the slave FF, and copies the master.

If J=1 & K=1, then it toggles over the CLK’s positive transition & therefore the slave toggles
over the CLK’s negative transition.

If both the J & K are 0, then the FF can be immobilized & Q remains unmovable.
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 19

Q1 (i) Represent (129. 5)10 and (-1.125)10 in IEEE 754 single-precision and double-
precision formats. (2 Marks)

Solution:

1. (129.5)10

 Single-Precision:
o Convert to binary: 12910 = 11001012 and 0.510 = 0.12
o Combine: 1100101.12
o Normalize: 1.1001011 × 26
o Sign: 0 (positive)
o Exponent: 6 + 127 = 13310 = 100001012
o Mantissa: 1001011 (1.1001011 × 26 - 1) = 01001011000000000000000 2
o Binary Representation: 0 10000101 01001011000000000000000
o Hexadecimal Representation: 40 4B 00 00
 Double-Precision:
o Convert to binary: 12910 = 11001012 and 0.510 = 0.12
o Combine: 1100101.12
o Normalize: 1.1001011 × 26
o Sign: 0 (positive)
o Exponent: 6 + 1023 = 102910 = 100000000112
o Mantissa: 1001011 (1.1001011 × 26 - 1) =
01001011000000000000000000000000 2
o Binary Representation: 0 10000000011
01001011000000000000000000000000 2
o Hexadecimal Representation: 40 08 4B 00 00 00 00 00

2. (-1.125)10:

 Single-Precision:
o Convert to binary: -1.12510 = -1.0012
o Sign: 1 (negative)
o Exponent: 0 + 127 = 12710 = 011111112
o Mantissa: 001 (1.0012 - 1) = 00100000000000000000000 2
o Binary Representation: 1 01111111 00100000000000000000000
o Hexadecimal Representation: C0 40 00 00
 Double-Precision:
o Convert to binary: -1.12510 = -1.0012
o Sign: 1 (negative)
o Exponent: 0 + 1023 = 102310 = 011111111112
o Mantissa: 001 (1.0012 - 1) = 001000000000000000000000000000002
o Binary Representation: 1 01111111111
0010000000000000000000000000000000 2
o Hexadecimal Representation: C0 00 00 00 00 00 00 40
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 20

Question 2:

Q2 (a) Refer to the Figure 2(b) on page 8 in Unit 1 of Block 2. Draw the Internal organisation
of a 16×2 RAM. Explain all the Input and Output of this organisation. Also, answer the
following:

(i) How many data input and data output lines does this RAM need? Explain your answer.

(ii)How many address lines are needed for this RAM? Give reasons in support of your
answer. (2 Marks)

Solution:

1. Decoder:

The RAM has 16 memory locations (24 = 16), which means I need a 4-to-16 decoder to select any
one of the 16 locations. The decoder will have 4 address lines (A0, A1, A2, A3) as inputs and 16
output lines to select the specific memory location in the RAM.

2. Data Inputs (I1, I0):

Since each word in the RAM is 2 bits wide, I will need 2 data input lines (I1 and I0) to provide data
for writing into the RAM.
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 21

3. Data Outputs (O1, O0):

Similarly, I need 2 data output lines (O1 and O0) to read the data from the RAM when it is in "read"
mode.

4. Control Signals:

 R/W (Read/Write): This signal determines whether the operation is a read or write. If the
signal is 0, the RAM performs a write operation, and if it is 1, it performs a read operation.
 Chip Select (CS): This enables the RAM chip. When CS = 0, the chip is active, meaning it can
perform either a read or a write operation depending on the R/W signal. If CS = 1, the chip
is disabled.

(i) Data Input and Output Lines

This RAM has 2 data input lines and 2 data output lines, as the data width is 2 bits. Each word stored
in the RAM has 2 bits, so I need two separate lines to input and output data.

(ii) Address Lines

I need 4 address lines for this RAM because I need to address 16 different memory locations. Since
24 = 16, four address lines (A0, A1, A2, A3) are required to uniquely select any of the 16 locations in
the RAM.

Q2 (b) A computer has 4 K Word RAM with each memory word of 8 bits. It has cache
memory, having 16 blocks, having a size of 16 bits (2 memory words). Show how the main
memory address (3AC)h will be mapped to the cache address, if

(i) Direct cache mapping is used

(ii) Associative cache mapping is used

(iii)Two-way set associative cache mapping is used. You should show the size of the tag,
index, main memory block address and offset in your answer. (3 Marks)

Solution:

Cache Mapping

Main Memory Address: 3ACh

RAM: 4K words, 8 bits/word

Cache: 16 blocks, 16 bits/block (2 memory words)

 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 22

(i) Direct Cache Mapping

 Address: 15 bits (4K words 8 bits/word)

 Offset: 8 bits (2 words 8 bits/word)
 Index: 4 bits (16 blocks)
 Tag: 3 bits (15 - 8 - 4 = 3)
 3ACh (0011 1010 11002):
o Tag: 0011
o Index: 1010
o Offset: 1100
o Cache Address: 1010

(ii) Associative Cache Mapping

 Address: 15 bits (4K words 8 bits/word)

 Offset: 8 bits (2 words 8 bits/word)
 Tag: 7 bits (15 - 8 = 7)
 3ACh (0011 1010 11002):
o Tag: 0011 1010
o Offset: 1100
o Cache Address: 0011 1010

(iii) Two-way set associative cache mapping

 Address: 15 bits (4K words 8 bits/word)

 Offset: 8 bits (2 words 8 bits/word)
 Set Index: 3 bits (16 blocks / 2 blocks/set = 8 sets)
 Tag: 4 bits (15 - 8 - 3 = 4)
 3ACh (0011 1010 11002):
o Tag: 0011
o Set Index: 101
o Offset: 1100
o Cache Address: 510

2 (c) What are the different kinds of interrupts? Explain the process of handling an interrupt
with the help of a diagram. . (3 Marks)

Solution:

There are several kinds of interrupts, each serving a different purpose.

1. Hardware Interrupts: These are triggered by external devices or internal events within
the computer system. Examples include:
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 23

I/O Interrupts: When an I/O device (like a keyboard, mouse, or printer) completes an
operation or encounters an error.
Timer Interrupts: Generated by a timer within the CPU, used for timekeeping and
scheduling.
Memory Interrupts: Occur when the CPU attempts to access a memory location that is not
valid, such as trying to read from a non-existent location.
Hardware Errors: Occur due to malfunctions in the computer system, like power failure or
memory parity errors.

2. Software Interrupts: These are caused by the execution of specific instructions within the
program. Examples include:
System Calls: Requests made by a program to the operating system for services, such as file
operations, memory allocation, or process management.
Trap Interrupts: Occur when the CPU encounters an error or exception, such as a divide-
by-zero error or an invalid instruction.

Interrupt Handling Process:

 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 24

Explanation:

1. Interrupt Triggered: An interrupt occurs, interrupting the normal program

execution.
2. Interrupt Vector: The CPU saves the current state of the program (the program
counter, registers, etc.) and accesses the interrupt vector table. This table contains
the addresses of the interrupt handlers for different interrupt sources.
3. Interrupt Handler: The CPU jumps to the address in the interrupt vector table
corresponding to the type of interrupt that occurred.
4. Interrupt Handling: The interrupt handler performs the necessary actions to resolve
the interrupt. This might involve:
o Processing data from the device that caused the interrupt.
o Responding to the error that caused the interrupt.
o Performing any necessary actions to restore the system to a stable state.
5. Return from Interrupt: The interrupt handler completes its work, and the CPU
retrieves the saved state of the program and resumes execution from the point
where it was interrupted.

In essence, the interrupt handling process involves a transfer of control from the current
program to a dedicated interrupt handler, which processes the interrupt and restores the
system to a normal state.

Q2 (d) What is a DMA? What are the advantages of using DMA? Explain the functions of a
DMA interface with the help of a block diagram. (2 Marks)

Solution:

DMA stands for Direct Memory Access. It is a technique that allows devices to transfer data
directly to and from memory without the intervention of the CPU. This means the CPU does
not need to be involved in every data transfer, freeing it up to perform other tasks.

Advantages of using DMA:

 Increased Efficiency: DMA allows for faster data transfer rates, as it eliminates the
overhead of the CPU constantly handling data transfers. This can significantly
improve the performance of the system.
 Reduced CPU Overhead: By offloading data transfer tasks to DMA, the CPU can focus
on other critical functions, leading to a more efficient and responsive system.
 Improved System Throughput: DMA can handle multiple data transfers
simultaneously, leading to a higher overall throughput in the system.
 Simplified Program Design: With DMA, programmers do not need to write complex
code to manage data transfers, simplifying their program design.
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 25

Functions of a DMA Interface:

A DMA interface acts as a bridge between the device and the memory. It manages the data
transfer process, allowing the device to access memory directly. Here's a block diagram
illustrating its functions:

Explanation:

 Device: This is the device that needs to transfer data to/from memory.
 DMA Controller: This is the central component of the DMA interface. It handles the
data transfer process. It has:
o Address Register: Stores the memory address to which data needs to be
transferred.
o Control Logic: Controls the timing and flow of data transfers.
o Data Register: Stores the data to be transferred to/from memory.
o Status Register: Indicates the status of the DMA transfer (e.g., busy,
completed).
 Memory: This is the memory location where data is stored or retrieved.

How DMA Works:

1. Device Request: The device sends a request to the DMA controller, indicating that it
needs to transfer data.
2. DMA Controller Activation: The DMA controller initiates the data transfer process.
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 26

3. Address and Data Transfer: The DMA controller uses the address register to access
the memory and transfer data to/from the device using the data register.
4. Completion: When the data transfer is complete, the DMA controller signals the
device and the CPU.

Q2 (e) Assume that a disk has 128 tracks, with each track having 64 sectors and each sector
is of size 1 M Bytes. The cluster size in this system can be assumed to be 2 sectors. A file
having the name assignmentmcs012.txt is of size 16 MB. Assume that it is a new disk, and the
first 16 clusters are occupied by the Operating System. Rest all the clusters are free. How can
this file be allotted space on this disk? Also, show the content of FAT after the space
allocation to this file. You may make suitable assumptions. (4 Marks)

Solution:

To allocate space for the file "assignmentmcs012.txt" on the disk, I will need to consider the
file size, the cluster size, and the available space on the disk.

1. Calculate the total number of clusters needed:

 File size: 16 MB = 16,777,216 bytes

 Sector size: 1 MB = 1,048,576 bytes
 Number of sectors per cluster: 2
 Total sectors in the file: 16,777,216 bytes / 1,048,576 bytes/sector = 16 sectors
 Total clusters needed: 16 sectors / 2 sectors/cluster = 8 clusters

2. Allocate space:

 Since the first 16 clusters are occupied by the OS, the file needs to be placed starting
from cluster 17.
 The file requires 8 clusters, so the file will occupy clusters 17 to 24.

3. FAT (File Allocation Table) Update:

 The FAT is a table that stores information about the file allocation on the disk. Each
entry in the FAT corresponds to a cluster, and it contains the address of the next
cluster in the file's allocation chain.
 Since the file is a new file, its FAT entries will be updated to reflect the allocation of
clusters to it.
 Assumptions:
o The FAT has the same number of entries as the number of clusters on the
disk.
o The first 16 entries are occupied by the OS.
o The remaining entries are free.
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 27

o The FAT uses a linked-list structure to store the file's clusters.

 FAT Content: The FAT content would look like this:

Cluster # FAT Entry

1 - 16 OS
17 18
18 19
19 20
20 21
21 22
22 23
23 24
24 0
25 - 127 Free

 Explanation:
o Clusters 17-24: These clusters are allocated to the file
"assignmentmcs012.txt". The FAT entries indicate the next cluster in the
file's allocation chain.
o Cluster 24: Since the file ends at cluster 24, the FAT entry for 24 is set to 0,
indicating the end of the file.
o Free Clusters: The remaining clusters (25-127) are free and can be allocated
to other files.

4. File Allocation Chain:

The file "assignmentmcs012.txt" will have the following allocation chain:

17 → 18 → 19 → 20 → 21 → 22 → 23 → 24 → 0

Q2 (f) Explain the following, giving their uses and advantages/disadvantages, if needed.
(Word limit for the answer of each part is 50 words ONLY) (6 Marks)

(i) Access time of disks

(ii) CD-ROM

(iii) Classification of Printers

(iv) Scanner
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 28

(v) Refresh rates of monitors

(vi) Devices for data backup

Solution:

(i) Access time of disks: The time it takes to locate and retrieve data from a disk. Uses:
Accessing data from a hard drive, reading files from a floppy disk. Advantages: Fast data
access, large storage capacity. Disadvantages: Slower than RAM access.

(ii) CD-ROM: A type of optical disc that stores data in a digital format. Uses: Storing and
distributing software, music, and data. Advantages: Cheap, durable, and capable of storing
large amounts of data. Disadvantages: Read-only, slow data access compared to hard drives.

(iii) Classification of Printers: Printers are categorized by technology, print quality, speed,
and type of paper they can use. Uses: Printing documents, photos, and labels. Advantages:
Variety of options for different needs. Disadvantages: Different printers have different
capabilities and costs.

(iv) Scanner: A device that converts printed documents into digital images. Uses: Digitizing
documents, photos, and artwork for storage or editing. Advantages: Saves paper, allows for
easy sharing of documents. Disadvantages: Can be slow for large documents, may not
always accurately capture images.

(v) Refresh rates of monitors: The frequency at which the monitor redraws the screen.
Uses: Ensuring smooth and flicker-free display of images. Advantages: Improved image
quality and viewing comfort. Disadvantages: Higher refresh rates can increase power
consumption.

(vi) Devices for data backup: Devices used to create copies of data for protection against
data loss. Uses: Protecting critical data from accidental deletion, corruption, or hardware
failure. Advantages: Ensures data recovery, protects against data loss. Disadvantages:
Requires time and resources to perform backups.

Question 3:

Q3 (a) A single-core uniprocessor system has 16 General purpose registers. The machine has
RAM of size 1 M memory words. The size of every general-purpose register and memory
word is 32 bits. The computer uses fixed-length instructions of size 32 bits each. An
instruction of the machine can have two operands. One of these operands is a direct memory
operand and the other is a register operand. An instruction of a machine consists of bits for
operation code, bits for memory operand and bits of register operand. The machine has
about 64 different operation codes. The machine also has special purpose registers, which
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 29

are other than general purpose registers. These special purpose registers are – Program
Counter (PC), Memory Address Register (MAR), Data Register (DR) and Flag registers (FR).
The first register among the general-purpose registers can be used as Accumulator Register.
The size of Integer operands on the machine may be assumed to be equal to the size of the
accumulator register. To execute instructions, the machine has another special purpose
register called Instruction Register (IR) of size 32 bits, as each instruction is of this size.
Perform the following tasks for the machine. (Make and state suitable assumptions, if any.)

(i) Design suitable instruction formats for the machine. Specify the size of different fields that
are needed in the instruction format. Also, indicate how many bits of the instructions are
unused for this machine. Explain your design of the instruction format. What would be the
size of each register? (3 Marks)

(ii) Illustrate two valid instructions of the machine by drawing a diagram that shows
instructions and related data in registers and memory. (2 Marks)

(iii) Assuming that an instruction is first fetched to the Instruction Register (IR), its memory
operand is brought to the DR register and the result of an operation is stored in the
Accumulator register, write and explain the sequence of micro-operations to fetch and
execute an addition instruction that adds the contents of a memory operand with the
contents of a register operand. The result is stored in the accumulator register. Make and
state suitable assumptions, if any. (5 Marks)

Solution:

(i) Design suitable instruction formats for the machine

Assumptions:

 The machine uses 32-bit instructions.

 There are 64 different operation codes, meaning 6 bits are needed for the operation
code (since 26 = 64).
 There are 16 general-purpose registers, so 4 bits are required to specify a register
(since 24 = 16).
 The system has 1 M memory words, which requires 20 bits for addressing (since 220
= 1,048,576 memory locations).
 The instruction contains both a register operand and a memory operand.

Instruction Format Design:

A suitable instruction format needs the following fields:

1. Operation Code (Opcode):

o 6 bits to represent 64 different instructions.
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 30

2. Memory Operand:
o 20 bits to address one of the 1 M memory words.
3. Register Operand:
o 4 bits to specify one of the 16 general-purpose registers.
4. Unused Bits:
o 32 - (6 + 20 + 4) = 2 unused bits.

Thus, the instruction format will be:

Field Bits
Operation Code 6
Memory Operand 20
Register Operand 4
Unused 2

Explanation of Instruction Format:

 Operation Code: This field specifies the operation to be performed (e.g., ADD, SUB,
etc.). With 6 bits, 64 different instructions can be represented.
 Memory Operand: This field contains the address of the memory location that holds
one of the operands.
 Register Operand: This field specifies which of the 16 general-purpose registers is
being used for the second operand.
 Unused Bits: There are 2 unused bits, as 32 bits are available but only 30 are needed
for the operation code, register, and memory operands.

Size of Each Register:

 The general-purpose registers, special-purpose registers, and accumulator are all 32

bits in size. This is consistent with the size of memory words and the size of integer
operands.

(ii) Illustrate Two Valid Instructions of the Machine

Let's illustrate two sample instructions: ADD and SUB.

Instruction 1: ADD R1, [100000h]

This instruction adds the contents of memory location 100000h to the value in register R1
and stores the result in the accumulator (R0).

Field Bits Value Explanation

 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 31

Field Bits Value Explanation

Operation Code 6 000001 (ADD) Operation to perform (ADD).
Memory Operand 20 100000h (1,048,576) Memory address of the operand.
Register Operand 4 0001 (R1) Register R1.
Unused 2 00 Unused bits.

 Memory Address: The memory operand points to the data located at 100000h.
 Register: The register operand refers to R1.

Instruction 2: SUB R2, [0A0000h]

This instruction subtracts the contents of memory location 0A0000h from the value in
register R2 and stores the result in the accumulator (R0).

Field Bits Value Explanation

Operation Code 6 000010 (SUB) Operation to perform (SUB).
Memory Operand 20 0A0000h (655,360) Memory address of the operand.
Register Operand 4 0010 (R2) Register R2.
Unused 2 00 Unused bits.

 Memory Address: The memory operand points to the data located at 0A0000h.
 Register: The register operand refers to R2.

(iii) Sequence of Micro-operations for Fetching and Executing an Addition Instruction

Assumption:

The instruction is ADD R1, [100000h]. The instruction adds the contents of memory
address 100000h to the contents of R1, and the result is stored in the accumulator register
R0.

The steps involved in fetching and executing this instruction are:

1. Fetch the instruction to the Instruction Register (IR):

o The instruction at the memory location specified by the Program Counter
(PC) is fetched.
o Micro-operation:

MAR←PC
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 32

PC←PC+1

IR←Memory[MAR]

2. Decode the instruction:

o The instruction in the IR is decoded, and the operation code and operands
are identified.
o No specific micro-operation is performed here, as the control unit decodes
the instruction.
3. Fetch the memory operand into Data Register (DR):
o The memory operand is fetched from the specified address (100000h) into
the Data Register (DR).
o Micro-operation:

MAR←IR[Memory Operand]

DR←Memory[MAR]

4. Perform the addition:

o The contents of register R1 and the memory operand (now in DR) are added.
o The result is stored in the Accumulator Register (R0).
o Micro-operation: R0←R1+DR

5. Store the result in the Accumulator Register (R0):

o The result of the addition is stored in R0.
o This step is already included in the previous micro-operation.

Final Micro-operation Sequence:

Step Micro-operation
1. Fetch Instruction MAR ← PC, PC ← PC + 1, IR ← Memory[MAR]
2. Decode Instruction Control unit decodes the instruction in IR
3. Fetch Memory Operand MAR ← IR[Memory Operand], DR ← Memory[MAR]
4. Perform Addition R0 ← R1 + DR
5. Store Result (Result already stored in R0)

Q3 (b) Assume that you have a machine, as shown in section 3.2.2 of Block 3 having the set of
microoperations as given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both
are 8-bit registers and contain 01111110 and 11010101 respectively. What will be the
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 33

values of select inputs, carry-in input, and the result of the operation (including carry-out
bit) if the following micro-operations are performed on these registers? (For each micro-
operation you may assume the initial value of R1 and R2 as given above) (2 Marks)

(i) Increment R2

(ii) Subtract R2 from R1

(iii) AND of R1 with R2

(iv) Shift left R1

Solution:

Select
Micro- Initial Operation Carry-in Carry-
Inputs (S₃ Result
operation Values Description (Cᵢ) out
S₂ S₁ S₀)
R1 =
11010110
Increment 01111110 Increment the value
0001 0 (214 in 0
R2 R2 = in R2 by 1
decimal)
11010101
R1 =
Subtract R2 from R1 10101001
Subtract R2 01111110
using two's 0011 1 (−87 in 1
from R1 R2 =
complement decimal)
11010101
R1 =
Perform a bitwise 01010100
AND of R1 01111110
AND operation 0100 0 (84 in 0
with R2 R2 =
between R1 and R2 decimal)
11010101
R1 =
Shift all bits in R1 to 11111100
01111110 Not
Shift left R1 the left by one 1000 (252 in 0
R2 = applicable
position decimal)
11010101

Q3 (c) Consider that an instruction pipeline has four stages namely instruction fetch (INFE),
Instruction decode and Operand Fetch (IDOF), Instruction Execute (INEX) and store results
(STRE). Draw an instruction pipeline diagram showing the execution of five sequential
instructions using this pipeline. Explain, what problem may occur, if the 2nd instruction is a
conditional jump instruction? (3 Marks)

Solution:
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 34

Instruction Pipeline Diagram and Conditional Jump Problem

Instruction Pipeline Diagram

Explanation of the Diagram:

 INFE (Instruction Fetch): Fetches the next instruction from memory.

 IDOF (Instruction Decode/Operand Fetch): Decodes the instruction and fetches the
operands (if any).
 INEX (Instruction Execute): Performs the operation specified by the instruction.
 STRE (Store Results): Stores the result of the instruction.

Instruction Sequence:

Let's assume the following 5 sequential instructions:

1. ADD R1, R2, R3

2. SUB R4, R5, R6
3. MOV R7, R8
4. CMP R9, R10
5. JMP label (Conditional Jump)

Execution:
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 35

Stage Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5

INFE ADD R1, R2, R3 SUB R4, R5, R6 MOV R7, R8 CMP R9, R10 JMP label
IDOF
INEX
STRE

Conditional Jump Problem

If the 2nd instruction (SUB R4, R5, R6) is a conditional jump instruction, the pipeline can
stall. This is because:

 Branch Prediction: The pipeline relies on branch prediction to continue execution. If

the jump is taken, the pipeline needs to discard the following instructions and start
fetching from the new location.
 Stalls: A conditional jump introduces uncertainty, and the pipeline may stall waiting
for the result of the conditional jump. This leads to a performance penalty.

Q3 (d) Explain the structure and operation of the micro-programmed control unit with the
help of a diagram. (2 Marks)

Solution:

Microprogrammed Control Unit in Short:

A microprogrammed control unit uses a ROM to store a sequence of microinstructions that

control the processor's operations. These microinstructions are fetched, decoded, and
executed sequentially.

Key Components:

 Microinstruction Memory: Stores microinstructions.

 Microprogram Counter (MPC): Tracks the current microinstruction.
 Instruction Decoder: Decodes the microinstruction to generate control signals.
 Control Signals: Control the processor's components (ALU, registers, memory).

Operation:

1. Fetch: MPC fetches the next microinstruction.

2. Decode: Decoder translates the microinstruction into control signals.
3. Execute: Control signals control processor components.
4. Increment: MPC moves to the next microinstruction.
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 36

Diagram (Simplified):

Q3 (e) Explain the use of large register file in RISC. Also, explain the optimisation of RISC
pipelining. (3 Marks)

Solution:

RISC: Large Register File and Pipelining Optimization

Large Register File in RISC

In a RISC processor, a large register file is crucial for efficient execution. This register file is
a collection of general-purpose registers that store data. The large size of this register file
allows the processor to hold more data, minimizing the need to load and store data from
memory. This helps to reduce the number of instructions needed to complete a task,
leading to faster execution.

Here's why a large register file is beneficial:

 Reduced Memory Access: Since most instructions operate on data stored in registers,
fewer memory accesses are required. This reduces the time taken to fetch
instructions and data, leading to a significant performance boost.
 Increased Instruction Level Parallelism (ILP): With a large register file, more
instructions can be executed concurrently, as there's sufficient space to hold the
intermediate results. This leads to higher instruction-level parallelism, which
further accelerates the execution of programs.
 Simplifies Instruction Set: A large register file simplifies the instruction set, as fewer
instructions are needed to perform operations. This makes the processor design
simpler and more efficient.

RISC Pipelining Optimization

 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 37

RISC architectures leverage pipelining to improve performance. This involves breaking

down the instruction execution process into smaller stages, allowing multiple instructions
to be processed concurrently. However, there are several optimizations that can be applied
to improve the efficiency of RISC pipelining:

 Instruction Scheduling: Optimizing the order of instructions in a program can help

avoid stalls in the pipeline. For instance, if an instruction depends on the result of a
previous instruction, the compiler can rearrange the code to ensure the dependent
instructions are executed in the correct order.
 Data Dependency: This refers to the relationship between instructions where one
instruction depends on the output of another. By identifying and managing data
dependencies, the compiler can minimize pipeline stalls. For example, if an
instruction needs the result of a previous instruction, the compiler can ensure that
the previous instruction is executed before the current one.
 Branch Prediction: Branches (jumps) can disrupt the pipeline. The compiler or
processor can predict the branch direction and execute instructions based on the
prediction. If the prediction is correct, the pipeline continues smoothly. If the
prediction is wrong, a branch misprediction penalty is incurred.
 Register Allocation: Efficient register allocation can prevent the need for
unnecessary loads and stores from memory. By carefully assigning variables to
registers, the processor can minimize the number of memory accesses, thus
improving performance.

Question 4:

Q4 (a) Write a program using 8086 assembly Language (with proper comments) that
accepts two different digits as input from the keyboard. Each digit is converted to its binary
equivalent value. These converted digits are stored in registers BL and CL. The program then
stores the smaller of these two values in AL register. The program also checks if the present
AL value is larger than all the values contained in a byte array of size 6, which is stored in the
memory. If so, then a value 1 is moved to DL register, else a value 0 is moved to DL register.
You may assume the byte array has the values 02h, 03h, 05h, 01h, 02h, 03h. Make suitable
assumptions, if any. (7 Marks)

Solution:

.MODEL SMALL

.STACK 100H

.DATA

MSG1 DB 'Enter first digit: $'

 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 38

MSG2 DB 'Enter second digit: $'

ARRAY DB 02H, 03H, 05H, 01H, 02H, 03H ; Byte array of size 6

NEWLINE DB 0DH, 0AH, '$' ; Newline for output formatting

.CODE

.STARTUP

; Display message to enter first digit

MOV AH, 09H

LEA DX, MSG1

INT 21H

; Read first digit from keyboard (ASCII)

MOV AH, 01H

INT 21H

SUB AL, 30H ; Convert ASCII to digit

MOV BL, AL ; Store first digit in BL

; Display message to enter second digit

MOV AH, 09H

LEA DX, MSG2

INT 21H

; Read second digit from keyboard (ASCII)

MOV AH, 01H

INT 21H
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 39

SUB AL, 30H ; Convert ASCII to digit

MOV CL, AL ; Store second digit in CL

; Compare digits and store the smaller one in AL

CMP BL, CL

JBE LESS_OR_EQUAL

MOV AL, CL ; If CL is smaller, move CL to AL

JMP CHECK_ARRAY

LESS_OR_EQUAL:

MOV AL, BL ; If BL is smaller or equal, move BL to AL

CHECK_ARRAY:

; Check if AL is larger than all values in the byte array

LEA SI, ARRAY ; Load address of array into SI

MOV CX, 06 ; Set counter for 6 elements

MOV DL, 01H ; Assume AL is larger, set DL to 1

COMPARE_LOOP:

CMP AL, [SI] ; Compare AL with each byte in the array

JBE NOT_LARGER ; If AL is less than or equal to any byte, set DL to 0

INC SI ; Move to the next byte in array

LOOP COMPARE_LOOP

JMP DONE ; If the loop finishes, AL is larger than all elements

 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 40

NOT_LARGER:

MOV DL, 00H ; AL is not larger than all values in array

DONE:

; Exit the program

MOV AH, 4CH

INT 21H

Screenshots of Output:
MCS-012 Solved Assignment 2024-25 | learningscience.co.in 41
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 42

Q4 (b) Differentiate between the FAR and NEAR procedure calls in 8086 micro-processor.
Assuming that a stack is used for implementing procedure calls, explain how call and return
statements of 8086 microprocessor would use stack for NEAR and FAR procedure calls and
return from a call. Also, assuming that two parameters are to be passed to a procedure using
stack, explain how they will be passed to the procedure and accessed in the procedure. You
need not write the assembly code but draw necessary diagrams to illustrate the concept. (7
Marks)

Solution:

In the 8086 microprocessor, FAR and NEAR procedure calls refer to how the processor
handles the memory addresses during procedure calls and returns. I will explain the
differences between them, describe how the stack is used in both cases, and how
parameters are passed and accessed via the stack.

Differentiation Between FAR and NEAR Procedure Calls:

 NEAR Procedure Call:

o A NEAR procedure call is made within the same code segment. Only the offset
address (IP - Instruction Pointer) is pushed onto the stack during the call.
o The return address contains the offset within the current code segment, and
the return instruction only restores this offset.
o Uses fewer resources as it operates within a single code segment.
 FAR Procedure Call:
o A FAR procedure call is made between different code segments. Both the
segment address (CS - Code Segment) and the offset address (IP) are pushed
onto the stack during the call.
o The return address restores both the segment and the offset, allowing the
processor to return to a different segment.
 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 43

o This method uses more memory but allows the program to call procedures
outside the current code segment.

How the Stack is Used in NEAR and FAR Calls:

NEAR Procedure Call and Return:

1. CALL Instruction (NEAR):

o When a NEAR procedure is called, the offset (IP) of the next instruction (after
the CALL) is pushed onto the stack.
o The processor then jumps to the called procedure, within the same segment,
using the IP provided in the CALL instruction.

Diagram for NEAR CALL (Stack Before and After):

Figure 1: Before Near Call

Figure 2: After Near Call

2. RET Instruction (NEAR):

 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 44

o When the NEAR procedure finishes, the RET instruction pops the IP from the
stack and continues execution from the saved address in the same segment.

Diagram for NEAR RET (Stack Before and After):

FAR Procedure Call and Return:

1. CALL Instruction (FAR):

o In a FAR procedure call, both the CS (Segment) and IP (Offset) of the next
instruction are pushed onto the stack.
o The processor then jumps to the new segment and the offset specified in the
CALL instruction.

Diagram for FAR CALL (Stack Before and After):

2. RET Instruction (FAR):

o When the FAR procedure finishes, the RET instruction pops the IP and CS
from the stack, allowing the processor to return to the correct segment and
offset.

Diagram for FAR RET (Stack Before and After):

 MCS-012 Solved Assignment 2024-25 | learningscience.co.in 45

How Parameters are Passed Using the Stack:

In 8086 assembly language, parameters can be passed to procedures via the stack. To
explain how this works, I will illustrate how two parameters are pushed onto the stack,
accessed within the procedure, and the process of returning.

1. Pushing Parameters Onto the Stack:

o Before calling the procedure, the caller pushes the parameters onto the stack
in reverse order. For example, if we need to pass two parameters (Param1
and Param2), the stack would look like this:

Diagram for Pushing Parameters:

2. CALL Instruction:
o After pushing the parameters, the CALL instruction pushes the return
address (IP or CS depending on NEAR or FAR) onto the stack, as shown in the
previous diagrams.
3. Accessing Parameters in the Procedure:
o Inside the procedure, the BP (Base Pointer) register is typically used to
access the stack. After the procedure starts, BP is set to SP (Stack Pointer) to
point to the base of the stack frame. Parameters can then be accessed as
offsets from BP:
 [BP + 4]: Points to Param1.
 [BP + 6]: Points to Param2.

Diagram for Accessing Parameters:

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4. RET Instruction:
o After accessing and using the parameters, the RET instruction is executed to
pop the return address off the stack and continue execution from the point
where the procedure was called.

Q4 (c) Explain the following in the context of 8086 Microprocessor with the help of an
example or a diagram: (6 Marks)

(i) Explain the use of Segment Registers in 8086 microprocessor

(ii) Explain the use of the flags - CF, ZF, OF, DF

(iii) Explain the Instructions – XLAT, MUL, SAR, RCL

Solution:

(i) Segment Registers in 8086 Microprocessor

The 8086 microprocessor uses segment registers to address a large memory space. These
registers, which include CS (Code Segment), DS (Data Segment), SS (Stack Segment), and
ES (Extra Segment), allow the CPU to access different parts of memory. Imagine a book
with many pages. Each segment register acts like a bookmark, pointing to a specific page or
section of the book (memory).

For instance, the CS register points to the location of the program code. The DS register
points to the location of data. When the CPU wants to access a specific instruction or data, it
combines the segment register value with an offset address (a number within the segment)
to calculate the actual memory address. This allows the 8086 to address up to 1 MB of
memory.

Example:
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Let's say we have a program that stores a number in memory. The program code might be
located in memory starting at address 0x10000. The data is stored starting at address
0x20000. The code segment register (CS) would point to 0x10000, and the data segment
register (DS) would point to 0x20000.

(ii) Flags: CF, ZF, OF, DF

The 8086 microprocessor has a set of flags that provide information about the result of an
arithmetic or logical operation. These flags are used by the CPU to make decisions and
control program flow.

 CF (Carry Flag): Indicates if a carry occurred during an arithmetic operation. For

example, in an addition, if the result overflows the maximum value, a carry is
generated and the CF flag is set.
 ZF (Zero Flag): Set when the result of an operation is zero. It helps the CPU to check
if a variable is zero.
 OF (Overflow Flag): Indicates if an arithmetic overflow occurred during an
operation, either positive or negative. This flag is essential for ensuring the accuracy
of calculations, especially with signed numbers.
 DF (Direction Flag): Determines the direction of string operations (like moving data
in memory). When set (DF=1), the string is processed from right to left; when
cleared (DF=0), the string is processed from left to right.

(iii) Instructions: XLAT, MUL, SAR, RCL

 XLAT (Translate): This instruction is used for translating a character code. It looks
up a value in a table and returns the corresponding value based on the current value
of the AL register. It's often used to convert character codes to their corresponding
ASCII values.

Example:

mov al, 'A' ; Load the character 'A' into AL

xlat ; Translate the character code in AL
; The value corresponding to 'A' is now in AL

 MUL (Multiply): This instruction multiplies two operands. The result is stored in the
AX register. For example, MUL BX will multiply the value in AL with the value in BX,
and the result will be stored in AX.

Example:

mov al, 5 ; Load the value 5 into AL

mov bl, 3 ; Load the value 3 into BL
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mul bl ; Multiply AL (5) with BL (3)

; The result (15) will be stored in AX

 SAR (Shift Arithmetic Right): This instruction shifts the bits of a number to the right.
For example, SAR AX, 1 will shift the bits in AX one position to the right. This
instruction is often used for division and bit manipulation.

Example:

mov ax, 10 ; Load the value 10 into AX (1010 in binary)

sar ax, 1 ; Shift the bits of AX to the right by 1 position
; AX now contains 5 (0101 in binary)

 RCL (Rotate Carry Left): This instruction rotates the bits of a number left, including
the carry flag. The carry flag is included in the rotation.

Example:

mov al, 10 ; Load the value 10 into AL (1010 in binary)

rcl al, 1 ; Rotate the bits of AL to the left by 1 position
; AL now contains 20 (10100 in binary)