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TLM Assignment

The document outlines two cases of component interactions in a UVM (Universal Verification Methodology) environment, focusing on the roles of generators and drivers as initiators and targets. Case 1 describes a scenario where the generator acts as an initiator and the driver as a target, detailing the connection phases and component classes involved. Case 2 presents a situation where both the generator and driver function as initiators, including their respective ports and exports for data transfer.

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93 views4 pages

TLM Assignment

The document outlines two cases of component interactions in a UVM (Universal Verification Methodology) environment, focusing on the roles of generators and drivers as initiators and targets. Case 1 describes a scenario where the generator acts as an initiator and the driver as a target, detailing the connection phases and component classes involved. Case 2 presents a situation where both the generator and driver function as initiators, including their respective ports and exports for data transfer.

Uploaded by

20501a0404
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

ASSIGNMENT

1.

a) case 1.

Generator as initiator and Driver as Target

C1

C2 C3

C4 C5

GENERATOR DRIVER
AS AS
INITIATOR TARGET

---- put_port

----put_export

-----put_imp
class generator extends uvm_component; class driver extends uvm_component;
uvm_blocking_put_port #(trans) put_port; uvm_blocking_put_imp #(trans,driver) put_imp;
..... .....
virtual task run_phase(uvm_phase phase); virtual task put(trans trans_h);
..... .....
put_port.put(trans); … endtask
endtask endclass
endclass

class C4 extends uvm_component; class C5 extends uvm_component;


uvm_blocking _put_port #(trans) put_port; uvm_put_export #(trans) put_export;
generator gen_h; driver drv_h;
function void connect_phase (uvm_phase function void connect_phase (uvm_phase
phase); phase);
gen_h.put_port.connect(this.put_port); this.put_export.connect(drv_h.put_imp);
endfunction endfunction
endclass endclass

class C2 extends uvm_component; class C3 extends uvm_component;


uvm_blocking _put_port #(trans) put_port; uvm_put_export #(trans) put_export;
C4 c4_h; C5 c5_h;
function void connect_phase (uvm_phase function void connect_phase (uvm_phase
phase); phase);
c4_h.put_port.connect(this.put_port); this.put_export.connect(c5_h.put_export);
endfunction endfunction
endclass endclass

class C1 extends uvm_component;


C2 c2_h;
C3 c3_h;
function void connect_phase (uvm_phase phase);
c2_h.put_port.connect(c3_h.put_export);
endfunction
endclass
b) Case 2

Generator as initiator and Driver as initiator

C1

C2 C3

C4 C5
T
L
M
GENERATOR _ DRIVER
AS F AS
INITIATOR I INITIATOR
F
O

------ put_port

------put_export

-----get_export

-----get_port
class generator extends uvm_component; class driver extends uvm_component;
uvm_blocking_put_port #(trans) put_port; uvm_blocking_get_port#(trans) get_port;
……. …..
virtual task run_phase(uvm_phase phase); virtual task run_phase(uvm_phase phase);
.... …
put_port.put(trans); get_port.get(trans)
endtask endtask
endclass endclass

class C4 extends uvm_component; class C5 extends uvm_component;


uvm_blocking _put_port #(trans) put_port; uvm_blocking_get_port #(trans) get_port;
generator gen_h; driver drv_h;
function void connect_phase (uvm_phase function void connect_phase (uvm_phase
phase); phase);
gen_h.put_port.connect(this.put_port); drv_h.get_port.connect(this.get_port);
endfunction endfunction
endclass endclass

class C2 extends uvm_component; class C3 extends uvm_component;


uvm_blocking _put_port #(trans) put_port; uvm_blocking_get_port #(trans) get_port;
C4 c4_h; C5 c5_h;
function void connect_phase (uvm_phase function void connect_phase (uvm_phase
phase); phase);
c4_h.put_port.connect(this.put_port); c5_h.get_port.connect(c3_h.get_port);
endfunction endfunction
endclass endclass

class C1 extends uvm_component;


C2 c2_h;
C3 c3_h;
uvm_tlm_fifo#(trans) fifo_h;
function void connect_phase (uvm_phase phase);
c2_h.put_port.connect(fifo_h.put_export);
c3_h.get_port.connect(fifo_h.get_export);
endfunction
endclass

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