ROBERTO RANGEL DA SILVA

BLUETOOTH LOW ENERGY RF FRONT-END

FOR LOW-VOLTAGE APPLICATIONS IN CMOS
TECHNOLOGY

São Paulo
2019
 ROBERTO RANGEL DA SILVA

BLUETOOTH LOW ENERGY RF FRONT-END

FOR LOW-VOLTAGE APPLICATIONS IN CMOS
TECHNOLOGY

Dissertation presented to the Polytechnic

School of Engineering of the University
of São Paulo in partial fulfillment of the
requirements for the degree of Master of
Science.

São Paulo
2019
 ROBERTO RANGEL DA SILVA

BLUETOOTH LOW ENERGY RF FRONT-END

FOR LOW-VOLTAGE APPLICATIONS IN CMOS
TECHNOLOGY

Dissertation presented to the Polytechnic

School of Engineering of the University
of São Paulo in partial fulfillment of the
requirements for the degree of Master of
Science.

Concentration Area:
Microelectronics

Supervisor:
Prof. Dr. Wilhelmus Adrianus
Maria Van Noije

São Paulo
2019
 ROBERTO RANGEL DA SILVA

BLUETOOTH LOW ENERGY RF FRONT-END

FOR LOW-VOLTAGE APPLICATIONS IN CMOS
TECHNOLOGY

Dissertação de mestrado apresentada à

Escola Politécnica da Universidade de
São Paulo como requisito parcial para a
obtenção do tı́tulo de Mestre em Ciências.

Área de Concentração:
Microeletrônica

Orientador:
Prof. Dr. Wilhelmus Adrianus
Maria Van Noije

São Paulo
2019
This work is dedicated to my par-
ents Roberto and Jaqueline, my
sister Vitória, and all that gave
support in this journey.
 ACKNOWLEDGMENTS

First I would like to thank God for the health, inspiration and perseverance given
through this work development. Thank my family who give me support throughout all
this work.
I would like to thank Professor Wilhelmus Adrianus Maria Van Noije for the oppor-
tunity in work as a [Link]. candidate at the Polytechnic School of the University of São
Paulo, all the supervising experience and challenges imposed to me that have collaborated
significantly in the improvements of my professional abilities.
I would also like to thank to professors João A. Martino, Paula G. Der Agopian and
all CI Brasil CT-SP group for all the help, support and friendship.
To the IMEC Free-mini@asic and to the MOSIS Educational programs for the free
integrated circuit fabrications and to professors João N. Soares Júnior and Julio Saldana
for all the suggestions gave me at the qualification exam. A special thank to Lucas Severo
for all the meaningful conversations, inspiration and technical knowledge. Thank to Hugo
Hernandez and Armando Pabon for the kindness, inspiration and knowledge shared.
I would like to thank all the friends I had the great opportunity of meeting at the CI
Brasil program, Fellipe Sola, Edelson Venuto, Walter Aranda, Ruy Costa, Isaias Junior,
Sergio Santos, Marcio Oliveira, Alejandra Gonzales, Mauricio Camilo, Guilherme Araújo,
Alison Venancio, Pedro Bispo, Vitor Przedzmirski, Catherine Pancotto, Phillipe Menezes,
Pedro Ferreira, Fabio Kelm, Rafael Alves, Mateus Castro, Diego Lima, Vitor Gomes,
Estevão Magro, Lucas Martins, Brunno Brendon, Leonardo Leopoldo.
A special thank to Daniele Santana, whose constant love, care and support made
possible this work development.
I would like to thank all the friends that supported this work development, especially
Thamyris Santos, for all the support and for reserving time to be present in the final
moments of this work development.
I would like to thank all the members of the DMPSV department of the LSI at USP,
especially to Silvana, for all the conversations at the coffee time, help and kindness. For
Jair and Professor Fatima at LME for the help and support during the experimental phase
of this work.
Thanks to professor Frederico Pontes, who first inspired my to pursue the Electronics
Engineering major and first showed me the possibilities in integrated circuit design, and
to professor Manoel Perez, for believing and inspiring me from my very beginning in the
microelectronics.
Finally, to all that shared part of this time of my life, supporting and giving strength
to go forward.
 RESUMO

Este trabalho apresenta a análise, métodos de projeto e implementação de circuitos

eletrônicos em tecnologia Metal Óxido Silı́cio Complementar (CMOS) para operação em
rádio frequências na banda industrial, cientı́fica e médica, seguindo o protocolo de comu-
nicação Bluetooth Low Energy, para a banda de frequência de 2,4 GHz a 2,4835 GHz.
São apresentadas as motivações atuais para o trabalho com o padrão Bluetooth Low
Energy, assim como os parâmetros de performance necessários para o projeto. Este proto-
colo oferece um conjunto de especificações mais flexı́veis, ajudando na redução da tensão
de alimentação e do consumo de potência.
Estão incluı́das considerações sobre o trabalho com transistores de efeito de campo
em Metal Óxido Silı́cio em baixas tensões, incluindo sua operação na região de inversão
fraca.
Três implementações são apresentadas, com resultados ,para blocos de Amplificador de
Baixo Ruı́do e bloco conjunto Amplificador de Baixo Ruı́do e Misturador de Frequências.
O sinal convertido a frequência intermediária é analisado, assim como a operação do
Amplificador de Baixo Ruı́do.
Todos os projetos apresentados mostraram um consumo de potência abaixo de 1 mW,
para tensão de alimentação 0,5 V e linearidade compatı́vel com potências de entrada até
-20 dBm.
Palavras-Chave – Microeletrônica, CMOS, Rádio Frequência, Bluetooth Low En-
ergy.
 ABSTRACT

This work presents the analysis, design methodology and implementation of CMOS
electronic circuits for operation in RF frequency, in the Industrial, Scientifical and Med-
ical (ISM) band, following the Bluetooth Low Energy communication protocol, for the
frequency band of 2.4 GHz to 2.4835 GHz.
The contemporary motivation for working with Bluetooth, as well as the necessary
performance parameters to be followed by the design is presented. Bluetooth Low Energy
present a more flexible specification set, which helps with the reduction of supply voltage
and power consumption.
The considerations on how to work with MOSFETs with low voltage are presented,
including the operation with inversion levels next to weak inversion region.
Three implementations are presented, with results for LNA blocks and Front-End,
which present a system with LNA and Mixer. The signal converted to an intermediate
frequency is analyzed, as well as the LNA operation.
All the presented design showed power consumption below 1 mW, for 0.5 V supply
and linearity compatible with input power up to -20 dBm.
Keywords – Microelectronics, CMOS, Radio-Frequency, Bluetooth Low Energy.
 LIST OF FIGURES

1 Receiver system considered for this work, with RF Front-End implementing

a Low-IF quadrature downconversion. . . . . . . . . . . . . . . . . . . . . . 25

2 Cascode common-source LNA with inductive source degeneration and LC

load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3 Small-signal model of the transistor M1 , showing the input interface at gate

terminal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4 Small-signal model showing the load connection at the drain terminal of

the transistor M2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5 Small-signal model showing the the noise sources at the terminals of M1 . . 34

6 Cascode common-source LNA with inductive source degeneration, includ-

ing equivalent parallel resistance from load inductor parasitics. . . . . . . . 37

7 LNA circuit showing the biasing circuit, and off-chip parasitic passive ele-
ments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8 Single balanced passive mixer circuit based on MOS switches. . . . . . . . 44

9 Passive mixer showing RON resistances and their related noise voltage
2
sources vn,ron . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10 Single-balanced passive mixer circuit showing biasing and LO buffers. . . . 49

11 RF Front-End circuit showing LNA and Mixer circuits with the chosen
topologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

12 The implemented cascode common-source LNA with inductive source de-

generation and common-source Buffer circuit in 180nm CMOS technology. 55

13 The cascode common-source LNA with inductive source degeneration cir-

cuit in 180nm technology, along with parasitic and other external devices. . 57

14 The common-source Buffer with current-source load circuit in 180nm CMOS

technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

15 S-Parameter results for the schematic simulations of LNA. . . . . . . . . . 62

16 Noise Figure results for the schematic simulation of the LNA. . . . . . . . 62

17 1-dB compression point result for the schematic simulation of the LNA. . . 63

18 IIP3 result for the schematic simulation of LNA. . . . . . . . . . . . . . . 63

19 Layout of the LNA and buffer circuits in 180nm CMOS technology. . . . . 65

20 S-Parameter results for the post-layout simulation of the LNA and Buffer
circuit in 180nm CMOS technology. . . . . . . . . . . . . . . . . . . . . . . 66

21 Noise Figure results for the post-layout simulation of the LNA and Buffer
circuit in 180nm CMOS technology. . . . . . . . . . . . . . . . . . . . . . . 67

22 1-dB compression point simulation for the post-layout of LNA and Buffer. 67

23 IIP3 results for the post-layout simulation of the LNA and Buffer circuit
in 180nm CMOS technology. . . . . . . . . . . . . . . . . . . . . . . . . . . 68

24 Die micrograph for the LNA and Buffer circuit. . . . . . . . . . . . . . . . 69

25 Schematic capture of the designed test PCB for the LNA and Buffer circuit
on Autodesk EAGLE software. . . . . . . . . . . . . . . . . . . . . . . . . 69

26 Fabricated test PCB for the LNA and Buffer circuit. . . . . . . . . . . . . 70

27 Smith Chart plot for S11 of experimental LNA and Buffer circuit. . . . . . 71

28 S-Parameter analysis of experimental LNA and Buffer circuit. . . . . . . . 72

29 Impedance transformation performed after applying the designed matching

circuit in simulation performed by the Smith Chart Tool in the Keysight
ADS software using the data extracted from the measurements of the un-
matched LNA and Buffer circuit. . . . . . . . . . . . . . . . . . . . . . . . 73

30 Designed ideal input matching circuit for the LNA and Buffer circuit. . . . 73

31 Smith chart plot for the simulation of experimental circuit data with de-
signed input matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

32 S-parameter simulation of experimental circuit data with designed input

matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

33 Smith Chart plot showing the measured S11 of the LNA and Buffer circuit
with the real input matching circuit realized in the PCB. . . . . . . . . . . 76

34 Input matching circuit after adjustments on PCB. . . . . . . . . . . . . . . 76

35 S-parameter simulation for the measured circuit with measured input match-
ing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

36 Circuit showing the implementation of the LNA and the Buffer circuit in
180nm technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

37 The second implementation of the cascode common-source LNA with in-

ductice source degeneration circuit in 180nm CMOS technology, along with
parasitic and other external devices. . . . . . . . . . . . . . . . . . . . . . . 81

38 Circuit showing the Buffer circuit in 180nm technology, along with parasitic
and other external devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

39 S-Parameter result for the schematic simulation of the second LNA circuit. 84

40 Noise Figure result for the schematic simulation of the second LNA circuit. 84

41 1-dB compression point result for the schematic of LNA circuit. . . . . . . 85

42 IIP3 result for the schematic simulation of the LNA circuit. . . . . . . . . . 85

43 Layout for the second LNA and the Buffer circuit in 180nm CMOS technology. 87

44 S-Parameter results for post-layout simulation of the second LNA and

buffer circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

45 Noise Figure results for post-layout simulation of the second LNA and
Buffer circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

46 1-dB compression point result for post-layout simulation of the second LNA
and Buffer circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

47 IIP3 result for post-layout simulation of the second LNA and buffer circuit. 89

48 Die micrograph for the second LNA and Buffer circuit. . . . . . . . . . . . 90

49 Fabricated test PCB for the second LNA and Buffer circuit. . . . . . . . . 91

50 Smith Chart plot for S11 of experimental measurement of the second LNA
and Buffer circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

51 S-parameter results for experimental measurement of the second LNA and

Buffer circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

52 Impedance transformation performed by the Smith Chart Tool in the Keysight

ADS software using the data extracted from the measurements of the sec-
ond LNA and Buffer circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . 94
53 Designed ideal input matching circuit for the second LNA and Buffer circuit. 94

54 Smith chart plot for the simulation of experimental circuit data with de-
signed input matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

55 S-parameter simulation of experimental circuit data with designed input

matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

56 The implemented RF Front-End, common-source IF amplifier with resis-

tive load and common-source Buffer with resistive load circuits in 130nm
BiCMOS technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

57 The implemented circuit of the cascode common-source LNA with inductive

source degeneration block in 130nm BiCMOS technology. . . . . . . . . . . 100

58 The implemented single-balanced passive sampling Mixer circuit in 130nm

BiCMOS technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

59 The implemented common-source IF Amplifier with resistive load circuit

in 130nm BiCMOS technology. . . . . . . . . . . . . . . . . . . . . . . . . . 103

60 The implemented common-source Buffer with resistive load circuit in 130nm

BiCMOS technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

61 S-Parameter results for the schematic simulation of the common-source

LNA with inductive source degeneration in 130nm BiCMOS technology. . . 105

62 Noise Figure result for the schematic simulation of the common-source LNA
with inductive source degeneration in 130nm BiCMOS technology. . . . . . 106

63 S-Parameter result for the post-layout simulation of the common-source

LNA with inductive source degeneration in 130nm BiCMOS technology. . . 107

64 Noise Figure result for the post-layout simulation of common-source LNA

with inductive source degeneration in 130nm BiCMOS technology. . . . . . 107

65 1-dB compression point result for the post-layout simulation of the common-
source LNA with inductive source degeneration in 130nm BiCMOS tech-
nology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

66 IIP3 result for the post-layout simulation of the common-source LNA with
inductive degeneration in 130nm BiCMOS technology. . . . . . . . . . . . . 108

67 Layout for the RF Front-End, IF Amplifier and Buffer circuit in 130nm

BiCMOS technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
68 Conversion gain result for the post-layout simulation of the RF Front-End,
IF Amplifier and Buffer circuit for a 2.44 GHz input in 130nm BiCMOS
technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

69 Noise Figure post-layout simulation of LNA and Mixer for a 2.44 GHz input
in 130nm technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

70 1-dB compression point result for the post-layout simulation of the RF

Front-End, IF Amplifier and Buffer in 130nm BiCMOS technology. . . . . 112

71 Leakage signal result from RF to IF port for the post-layout simulation of

RF Front-End, IF Amplifier and Buffer circuit in 130nm BiCMOS technology.113

72 Leakage signal result from LO to IF port for the post-layout simulation of

RF Front-End, IF Amplifier and Buffer circuit in 130nm BiCMOS technology.113

73 Leakage signal result from LO to RF port for the post-layout simulation of

RF Front-End, IF Amplifier and Buffer circuit in 130nm BiCMOS technology.114

74 Die micrograph for the RF Front-End, IF Amplifier and Buffer circuit,

fabricated in GlobalFoundries 130nm BiCMOS technology. . . . . . . . . . 115

75 Schematic capture of the designed test PCB for the RF Front-End, IF

Amplifier and Buffer circuit in Autodesk EAGLE software. . . . . . . . . . 115

76 Fabricated test PCB for the RF Front-End, IF Amplifier and Buffer circuit. 116

77 Smith Chart plot for S11 of experimental RF Front-End, IF Amplifier and

Buffer circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

78 S-Parameter analysis of the experimental RF Front-End, IF Amplifier and

Buffer circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

79 Impedance transformation performed by the Smith Chart Tool in the Keysight

ADS software using the data extracted from the measurements of the un-
matched RF Front-End, IF Amplifier and Buffer circuit. . . . . . . . . . . 119

80 Designed ideal input matching circuit for the RF Front-End, IF Amplifier

and Buffer circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

81 Smith Chart plot simulation for S11 of experimental RF Front-End circuit

with designed LC matching. . . . . . . . . . . . . . . . . . . . . . . . . . . 120

82 S-parameter simulation of experimental RF Front-End circuit with de-

signed LC matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
83 Smith Chart plot showing the measured S11 of the RF Front-End, IF Am-
plifier and Buffer circuit with the real input matching circuit realized in
the PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

84 S-parameter measurement of experimental RF Front-End circuit with im-

plemented LC matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

85 Differential and single-ended output signals for 0.5V supply. . . . . . . . . 124

86 Transient output IF signal for different supply voltages. . . . . . . . . . . . 124

87 Input and output rms signals as a function of VDD . . . . . . . . . . . . . . 125

 LIST OF TABLES

1 Bluetooth standard operation modes. . . . . . . . . . . . . . . . . . . . . . 22

2 Bluetooth Low Energy main performance parameters [1]. . . . . . . . . . . 23

3 Reported State-of-The-Art BLE receiver implementations . . . . . . . . . . 26

4 Design specifications for the RF Front-End design following BLE specifi-

cation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5 Design specifications for the LNA design following BLE specification. . . . 53

6 Design specifications for the Mixer design following BLE specification. . . . 54

7 Device dimensions for the LNA and buffer circuit. . . . . . . . . . . . . . . 56

8 Transfer frequency response as a function of the applied bulk to source

voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9 Threshold voltage response as a function of the applied bulk to source voltage. 58

10 Device dimensions for the LNA circuit. . . . . . . . . . . . . . . . . . . . . 60

11 Device dimensions for the Buffer circuit. . . . . . . . . . . . . . . . . . . . 61

12 Performance obtained after schematic simulations. . . . . . . . . . . . . . . 64

13 Final sizing values for LNA and buffer circuit after adjustments. . . . . . . 66

14 Performance obtained after post-layout simulations of the LNA and Buffer

circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

15 Sizing values for ideal input matching circuit for the measured LNA and
Buffer circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

16 Sizing values for implemented input matching circuit of 180nm LNA. . . . 77

17 Performance obtained in experimental circuit. . . . . . . . . . . . . . . . . 78

18 Device dimensions for the second LNA and Buffer design. . . . . . . . . . . 80

19 Sizing values for second LNA 180nm. . . . . . . . . . . . . . . . . . . . . . 82

20 Sizing values for second buffer 180nm. . . . . . . . . . . . . . . . . . . . . 83

21 Performance obtained after schematic simulations. . . . . . . . . . . . . . . 86

22 Summary of results obtained in post-layout simulations. . . . . . . . . . . . 90

23 Sizing values for ideal input matching circuit for the measured second LNA
and Buffer circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

24 Summary of results obtained in experimental circuit. . . . . . . . . . . . . 96

25 Transfer frequency response as a function of the nMOS transistor channel

length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

26 Threshold voltage response as a function of the nMOS transistor channel

length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

27 Device dimensions for the Front-End, IF Amplifier and Buffer circuit in

130nm CMOS technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

28 Device dimensions for the cascode common-source LNA with inductive

source degeneration in 130nm BiCMOS technology. . . . . . . . . . . . . . 101

29 Device dimensions the single-balanced passive sampling Mixer in 130nm

BiCMOS technolgy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

30 Device dimensions for the common-source IF amplifier with resistive load

in 130nm BiCMOS technology. . . . . . . . . . . . . . . . . . . . . . . . . . 103

31 Device dimensions for the common-source Buffer with resistive load in

130nm BiCMOS technology. . . . . . . . . . . . . . . . . . . . . . . . . . . 104

32 Summary of performance obtained in the LNA after schematic simulations. 106

33 Summary of results obtained in post-layout simulations. . . . . . . . . . . . 114

34 Device dimensions for LC network input matching for the RF Front-End,

IF Amplifier and Buffer circuit in 130nm BiCMOS technology. . . . . . . . 120

35 Device dimensions for the experimental LC network input matching for the
RF Front-End, IF Amplifier and Buffer circuit in 130nm BiCMOS technology.123

36 Summary of results obtained in experimental circuit. . . . . . . . . . . . . 125

 LIST OF ABBREVIATIONS AND ACRONYMS

AC Alternated Current

ADC Analog-to-Digital Converter

BiCMOS Bipolar and Complementary Metal-Oxide-Semiconductor

BLE Bluetooth Low Energy

BR Basic Rate

CMOS Complementary Metal-Oxide-Semiconductor

DC Direct Current

EDR Extended Data Rate

FoM Figure of Merit

GBW Gain-Bandwidth Product

IF Intermediate Frequency

IIP3 Input Third-Order Intermodulation Intercept-Point

IM3 Third-Order Intermodulation Intercept-Point

IoT Internet of Things

IRN Input-Referred Noise

LNA Low-Noise Amplifier

LO Local Oscillator

MiM Metal-insulator-Metal

MOS Metal-Oxide-Semiconductor

MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor

NF Noise Figure
NMOS N-type Metal-Oxide-Semiconductor

PDK Process Design Kit

PGA Programmable Gain Amplifier

PMOS P-type Metal-Oxide-Semiconductor

RF Radio Frequency

SNR Signal-to-Noise Ratio

THD Total Harmonic Distortion

ULP Ultra Low Power

ULV Ultra Low Voltage

 CONTENTS

1 Introduction 19

1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.3 Bluetooth Low Energy Standard . . . . . . . . . . . . . . . . . . . . . . . . 21

1.4 Wireless Receiver Architecture for BLE . . . . . . . . . . . . . . . . . . . . 23

1.5 State of The Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.6 Organization of this document . . . . . . . . . . . . . . . . . . . . . . . . . 27

2 LNA and Mixer Low-Voltage Design Methodology 29

2.1 Low-Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.1.1 Topology choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.1.2 Input Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.1.3 Output Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.1.4 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.1.5 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.1.6 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.1.7 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.1.8 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.2 Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.2.1 Topology Choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.2.2 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.2.3 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.2.4 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.2.5 Input Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

 2.2.6 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2.3 RF Front-End with LNA and Passive Sampling Mixer . . . . . . . . . . . . 49

3 Implementation and Experimental Results 51

3.1 First LNA design in 180nm CMOS technology . . . . . . . . . . . . . . . . 54

3.1.1 Schematic simulations . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.1.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.1.3 Post layout simulations . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.1.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.2 Second Cascode common-source LNA in 180nm technology . . . . . . . . . 78

3.2.1 Schematic simulations . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.2.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.2.3 Post layout simulations . . . . . . . . . . . . . . . . . . . . . . . . . 87

3.2.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.3 RF Front-end design in 130nm BiCMOS technology . . . . . . . . . . . . . 97

3.3.1 Schematic simulations . . . . . . . . . . . . . . . . . . . . . . . . . 105

3.3.2 Post-Layout simulations of the LNA circuit . . . . . . . . . . . . . . 106

3.4 Front-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

3.4.1 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

3.4.2 Post layout simulations . . . . . . . . . . . . . . . . . . . . . . . . . 110

3.4.3 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . 114

4 Conclusion 126

4.1 Results Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

4.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

References 128
 19

1 INTRODUCTION

This chapter presents the motivation and objectives of this work, including discussions
on the issues regarding the reduction of power consumption and supply voltage in the
design of integrated circuits for radio-frequency (RF) communication systems using CMOS
technology, focusing on RF Front-End circuits for wireless receivers using the Bluetooth
Low Energy (BLE) standard, and operating at Ultra Low Voltage (ULV) and Ultra Low
Power (ULP).

1.1 Motivation

The current advancements on the development of ubiquitous systems with network

capabilities contribute on the solution for open problems in the society. Such systems,
often categorized as Internet of Things (IoT) rely on the network connection among
its peers, which enables the information sharing. It can be applied to monitoring and
actuating activities [2, 3]. One of the benefiting areas is that involving Wireless Body
Area Networks (WBAN), including wearable, implanted and hand-held devices which can
be applied to consumer, health care or productivity solutions [2–6].

Since IoT nodes often have restricted access to power supply, usually depending on
battery power, they demand advances on system design towards power consumption min-
imization. In addition to simply reducing static current by changing to less consuming
circuit topologies, the battery life can also be extended by operating at low supply volt-
ages.

The two approaches can be combined, leading to a larger minimization of power con-
sumption, and applying Ultra Low Voltage (ULV) and Ultra Low Power (ULP) solutions.
Reported works suggest that ULV and ULP currently stand for supply voltages under 1.0
V and RF receiver power consumption under 3.0 mW [7–9].

The reduction of the supply voltage also allows working with energy harvesting
 20

sources, such as solar cells, without the need for additional voltage level shifters [9–11].

Moreover, supply voltage reduction becomes mandatory along with the scaling of
CMOS technologies, reaching maximum values near 0.5 V for thin-oxide MOSFETs in
nodes below 22nm [12]. Operating at low supply voltages also reduces quadratically the
dynamic power consumption of digital circuits [12–14].

The circuit blocks included in the wireless radio-frequency (RF) transceiver are often
the most power consuming part of IoT devices [15]. Moreover, among the circuits com-
prising the wireless receiver, the majority of power consumption lies in the circuits of the
RF Front-End, responsible for the interface with the signal source, such as an antenna.

The most prospective network protocols implementing WBAN systems nowadays are
ZigBee, Bluetooth and Wi-Fi. They have been applied in many solutions through the
last years, proving to be solid solutions [4, 16]. The Bluetooth standard has been broadly
available in mobile phones, peripherals and other devices, contributing for its growing
popularity. Recently, the Bluetooth Low Energy standard have been adopted due to the
low consumption and high availability among the existing devices [17]. Bluetooth Basic
Rate (BR) mode designs have been reported and introduced considerable power reduction
comparing to other network protocols available at the time of its release [18–21].

Since its version 4.0, Bluetooth protocol includes the Bluetooth Low Energy (BLE),
also called Bluetooth Smart, standard. BLE has relaxed specifications constraints on
noise requirement and on sensitivity comparing to basic rate Bluetooth operating mode,
thus enabling reduced power consumption and area applications, on the expense of range
and data rate [1, 22].

At this moment CMOS technology is known to be the most used for the development
of large scale electronics solutions, fitting the demands of most IoT systems. CMOS
has the advantage of being capable of operating in radio-frequency range, performing
the demanded operation in the ISM band, near 2.4 GHz, and being able to integrate
communication and signal processing circuits with low area and power consumption.

This work is focused on study of the implementation of the RF Front-End blocks,

including the issues and possible solutions that allow ULV and ULP operation following
the BLE standard. The implementation involves the theory analysis, topology choice,
simulation, layout, fabrication and testing using conventional CMOS process. Moreover,
this work allow to extend the research conducted by previous works in the ”Divisão de
Metodologias de Projetos e Sistemas VLSI” (DMPSV) group at the University of Sao
Paulo [21, 23, 24].
 21

1.2 Objectives

This work aims at designing the blocks comprising the RF Front-End of a wireless
receiver, including a Low-Noise Amplifier (LNA) and a downconversion Mixer circuits for
CMOS technology.

The design follows the performance specifications of the Bluetooth Low energy proto-
col, evaluating the results with schematic and post-layout simulations, as well as exper-
imental results, when available. Moreover, the circuits are required to operate at Ultra
Low Voltage and Ultra Low Power, using the power consumption minimization as the
main factor for topology choice and design strategies. Based on the presented analysis
on the mandatory supply voltage reduction following CMOS technology scaling, and the
benefits for power consumption reduction and energy harvesting applications, this work
proposes a supply voltage of 0.5 V for the designed circuits.

The design strategies formulation, topology choices, circuit analysis, schematic simu-
lations, physical layout and post-layout simulations are also realized.

Following the circuits’ design and adjustments after post-layout simulations, this work
comprises the fabrication of the integrated circuits using CMOS technology.

After Fabrication, it is included the design of test boards to interface the fabricated
chips with the test equipment.

Finally, experimental and post-layout results are compared to desired performance

parameters and suggestions are made for improvements and future works.

1.3 Bluetooth Low Energy Standard

Currently in its 5.0 version, Bluetooth core specification includes Bluetooth Low En-
ergy (BLE) operation mode since its version 4.0 [1]. BLE changes the sensitivity, noise
tolerance and adjacent channel rejection specifications toward enabling the operation with
less power consumption. Table 1 shows a comparison among BLE, Bluetooth v5.0 (BT5),
basic rate (BR) and extended data rate (EDR) Bluetooth operation modes, highlighting
the more spaced spectrum of BLE, allowing a less restrict design. As presented, BLE,
BT5 and BR modes implement Gaussian Frequency Shift Keying (GFSK) modulation,
and EDR mode implements Differential Quadrature Phase Shift Keying (DQPSK) or
8-Phase Differential Phase Shift Keying (8DPSK) [1, 22].
 22

Table 1: Bluetooth standard operation modes.

BLE BT5 BR EDR
Modulation GFSK GFSK GFSK DQPSK / 8DPSK
Data Rate 1 Mbps 2 Mbps 1 Mbps 2 or 3 Mbps
Channels 40 40 79 79
Spacing 2 MHz 2 MHz 1 MHz 1 MHz

BLE devices operate under the unlicensed 2.4 GHz ISM band. BLE uses a binary fre-
quency modulation, with pulse shaping and data transmission rate down to 1 Msymbol/s,
using 1 bit/symbol modulation, giving 1 Mbit/s data rate. It works with 2MHz channel
band, using 1MHz for payload and 0.5MHz guard band between payload and adjacent
channels. From 2402 MHz to 2483.5 MHz, 40 channels are possible. Channel frequencies
receive values of 2400 + 2 × k MHz, being k an integer number from 1 to 40 [1, 22].

The receiver requires a -70dBm minimum and 0dBm maximum sensitivity. Signal is
modulated using gaussian frequency shift keying (GFSK), combining frequency modula-
tion with pulse shaping using gaussian filters. It is very similar to minimum shift keying
modulation, but with variations in the modulation index. To avoid signal interference, it
performs frequency hopping spread spectrum (FHSS) techniques, which keeps changing
the operating channel for periods determined by the link creation.

Table 2 summarizes the performance specifications regarding Bluetooth Low Energy

operation mode, as reported by [1], which will serve as design constraints towards this
work.

Based on the required adjacent channel interference, at the maximum usable input
level of 0 dBm, the compression point P1 dB is set at -15 dBm, and hence the IIP3 at -5
dBm.

The sensitivity performance is directly related to the maximum noise figure (NF) con-
tribution allowed in the receiver. Following the analysis reported in [25,26], an expression
can be derived to obtain the maximum NF.

N FdB = Sin + IL − Ns − SN Rout,min (1.1)

where NF is the maximum noise figure for the receiver, Sin is the sensitivity, or the
minimum detectable input signal level; IL is the input insertion loss; Ns = 10log(kT B)
is the in-band noise source, including the Boltzmann constant k, signal bandwidth B and
 23

the absolute temperature T, in kelvin; SN Rout,min is the minimum Signal-to-Noise (SNR)

for the receiver output required by the demodulator to identify the information with the
specified Bit-Error Rate (BER).

For the noise figure calculation, the value for the input sensitivity Sin is considered to
be 10 dBm lower than the one in table 2, to add a safety margin. The signal bandwidth
B is 1 MHz, an insertion loss of 2 dB is considered at the LNA input, as often an external
band filter is used, having this typical level of insertion loss [25]. The minimum SNR is
derived from the demodulator BER, where an optimal value of 12 dB is assumed [25].

Using the chosen values with equation 1.1, a maximum NF value of 20 dB is found.
This value will be considered for the further design on this work.

Table 2: Bluetooth Low Energy main performance parameters [1].

Parameter Value
Frequency Band 2400 - 2483.5 MHz
Channel length 2 MHz
Signal bandwidth 1 MHz
Sensitivity -70 dBm
Adjacent Channel Interference -17 dB
BER 0.1%
Data rate 1 Mbps

1.4 Wireless Receiver Architecture for BLE

This work focus on the design of blocks in the physical (PHY) layer of bluetooth
low energy protocol. Thus, the study of radio physical architectures is necessary. The
following study is based on the analyses suggested by [26–30].

The signal at the input of the wireless receiver contains the original information, sent
by an external transmitter, modulated around a carrier signal. The original signal have
a bandwidth fb , where fb  fc , being fc the frequency of the carrier signal.

The modulation results in a RF signal having a frequency spectrum with bandwidth

fb centered at fc . Hence, the receiver needs to translate the RF signal back to the original
frequency characteristics before the information processing.

The frequency translation is performed by the RF Front-End block, which lies in the
beginning of the receiver path, and is composed by a Low-Noise Amplifier (LNA) and a
 24

downconversion Mixer [26, 27].

The LNA is responsible for the interface with the signal source, often an antenna, being
the first stage of the receiver. Its noise contribution is the most critical for the overall
noise figure of the receiver, as it is entirely added to the receiver’s noise figure [26,31]. Its
input matching is responsible for achieving maximum power transfer of the input signal.
Also, its gain attenuates the noise contribution of the subsequent stages, justifying the
low noise and high gain characteristic of its design [26].

The downconversion Mixer is responsible for the translation of the RF signal centered
at the carrier frequency to a lower frequency. Depending on the receiver architecture, the
lower center frequency may be zero, or rather an intermediate frequency (IF).

A zero center frequency characterizes a direct-conversion, or Zero-IF receiver. Whereas

the presence of an IF characterizes an indirect-conversion receiver. The later is distin-
guished by the IF value, being called Low-IF receiver for an IF near zero, or High-IF for
higher values.

Some receivers implement more than one conversion steps, describing a Sliding-IF
architecture.

The value of IF is determined by the frequency generated at a Local Oscillator (LO),

where fIF = fRF − fLO , where fRF is the modulated input signal frequency. For Zero-IF
receivers, fLO = fRF .

This work contemplate the adoption of a Low-IF receiver, taking into account the
benefit of avoiding DC offset and flicker noise [7, 10, 32] influence in the DC spectrum
[8, 9, 11, 33–36].

Some works employ a Sliding-IF receiver, seeking to have a more relaxed LO design
[5, 6, 17, 37, 38]. However, this approach increases the number of stages in the receiver,
contributing to power consumption.

Figure 1 shows the architecture of a Low-IF receiver, including the LNA, quadra-
ture downconversion Mixer, polyphase filters, Programmable Gain Amplifiers (PGA) and
Analog-to-Digital converters (ADC).

The quadrature downconversion is performed in conjunction with polyphase filtering

as a way to realize image rejection on the resulting IF signal [26, 39]. To perform the
quadrature downconversion, the LO generates two outputs with 90◦ phase separation
between the In-Phase (I) and In-Quadrature (Q) IF paths.
 25

After the polyphase filter, the signal voltage level is adjusted by the PGA, and finally
converted to digital domain by the ADC.

Figure 1: Receiver system considered for this work, with RF Front-End implementing a
Low-IF quadrature downconversion.

Source: Author

1.5 State of The Art

Table 3 shows a summary of recently published works, which contribute to observe re-
portedly State-of-The-Art performance results. The work selection criteria seek to match
with the objectives of this work, intending to contribute with suitable comparison ref-
erences. Moreover, they serve to show the tendency for topology choice and design ap-
proaches.

The performance parameters reported are the technology node, power consumption,
supply voltage, receiver type, sensitivity, noise figure (NF), integrated area, and power
consumed by the Front-End (FE) circuit.

It is worthwhile to analyze the type of receiver architecture implemented, the factors

that justify the choice of the topologies for the LNA and Mixer circuits, as well as design
considerations, and the further effect on the system’s performance. It can be observed
that all works include either direct-conversion (Zero-IF) or Low-IF receivers, avoiding the
implementation of heterodyne architectures. Thus, they avoid the requirement for off-chip
image rejection filters, and also reduce the number of stages in the receiver path [26, 33].

Most implementations cited on table 3 were performed using sub-micron technology

nodes, except [33]’s, whose design choice was for a 130nm technology, coping with the
reduction of fabrication costs. That is a remarkable choice, since consumer Internet of
 26

Things applications also often include requirements for production cost reduction, turning
into an interesting choice, provided that the performance requirements are sustained.

The results show that the designs exploit the relaxed noise figure requirements of the
BLE standard, showing considerably high NF values, compared to BR/EDR Bluetooth [1]
or other more restrained standards, whose NF is often below 3 dB [26, 27]. The relaxed
noise response characteristics contribute to lower power consumption.

Table 3: Reported State-of-The-Art BLE receiver implementations

Parameter EDSSC 19 [11] ISSCC 18 [7] ISSCC 18 [8] TMTT 18 [33] JSSC 18 [9]
Technology (nm) 55 40 65 130 28
Power (mW) 20.4 2.3 2.3 1.69 0.38
Supply (V) 3 0.8 1 1.2 0.18
Receiver Type Low-IF Zero-IF Low-IF Low-IF Low-IF
Sensitivity (dBm) -95 -95 -94 -92 -
NF (dB) - 5.9 6 7.2 11.3
Area (mm2 ) - 0.8 1.64 0.7 1.65
FE Power (mW) - 0.69 0.7 0.76 0.13

A full System-on-Chip is included in [11]’s implementation with focus on consumer

applications, including digital processing, modem and link manager blocks besides the
physical layer. It claims a reduction on production costs, as it includes in-chip the nec-
essary memory structures, thus reducing the cost with off-chip materials on a further
product application. The sensitivity requirement for the protocol is extended, with a -95
dBm limit, yet having less attractive performance results than the other works regard-
ing power consumption and supply voltage. It implements a low-IF receiver, with RF
Front-End including a cascode common-source LNA with inductive source degeneration.

In [7], the receiver works with zero-IF downconversion, and uses a phase-tracking ar-
chitecture, where an all-digital phase-locked-loop (ADPLL) replace the analog-to-digital
converter (ADC) and allows using a single signal path, instead of quadrature downconver-
sion, thus saving power. The RF Front-End is composed by a single-ended, inverter-based
LNA, and a single-balanced, current-driven passive mixer. The use of a low supply voltage
of 0.8 V also contributes for the power reduction. The choices lead this design to a very
reduced power consumption, with low noise figure and chip area.

In [8], a low-IF receiver was chosen for its advantages in low power implementa-
tions, reportedly achieving attractive in-band and out-band blocker performance. It uses
 27

an ADPLL centric receiver, as in [7], with RF Front-End composed by a single-ended

common-source LNA with inductive source degeneration, integrated balun to modify the
signal path to differential, and a double-balanced current-driven passive mixer.

The implementation in [33] exploits the BLE standard frequency requirements to

improve power reduction by choosing an IF value of 1 MHz. Since the BLE channels
have 1 MHz of signal space and 1 MHz of spacing, using 1 MHz IF avoid the necessity
of a band-pass filter, as usual in low-IF receivers, using a low-pass filter instead. The
RF Front-End is composed by an inverter-based LNA, whose topology is based on [40].
Modifications are made to reduce power consumption without compromise the noise figure
and gain response.

The lowest RF Front-End power consumption is found in [9], where a massive re-
duction on the supply voltage is performed, reaching 0.18 V. The Front-End includes a
two-stage power gating LNA with a common-source inductive degenerated source topol-
ogy, using a transformer coupling between source and gate in order to implement input
matching, and passive gain boosting. It reportedly reduced the DC current on the LNA’s
first stage after including the transformer.

The observed characteristics on the art presented in this chapter will serve as a strong
reference during the design choices of this work, guiding the choice of topologies and
design strategies adopted.

1.6 Organization of this document

In chapter 1 the motivation and specification of the problem proposed by this work
was presented. Moreover, a study on the state-of-the-art reported works including the
design of RF Front-End systems for BLE receivers was conducted, contributing with
references for the design of Low-Noise Amplifiers, downconversion Mixers and RF Front-
Ends including them.

Chapter 2 realizes an theoretical analysis on the Low-Noise Amplifier, Mixer and

RF Front-End blocks, allowing the formulation of the mathematical equations that re-
late circuit parameters and performance specifications. The equations obtained are the
foundation for the topology choices and the development of the design strategy.

Chapter 3 describes the design of the Low-Noise Amplifier, Mixer and RF Front-
End using conventional CMOS technologies, presenting their circuit sizing, schematic
simulation results, physical layout, post-layout simulation results, fabrication results, test
 28

boards design, measurement procedures and experimental results.

Finally, in chapter 4 the experimental results are discussed and compared with post-
layout simulations and design performance objectives tables, verifying how close in the
final results to the desirable performance. Also, recommendations for future works are
stated, based on the flaws and success of this work.
 29

2 LNA AND MIXER LOW-VOLTAGE DESIGN

METHODOLOGY

This chapter presents the theoretical bases for the RF Front-End, Low-Noise Ampli-
fier (LNA) and Mixer circuits analysis and design. The presented theory will guide the
topology choice and formulation of equations describing the relation between the perfor-
mance specifications and the circuit parameters. In the implementation chapter of this
work, the equations gathered will be applied to CMOS technology parameters, to verify
the feasibility of the proposed circuit, as well as finding the initial circuit sizing.

The proposed supply voltage of 0.5 V imposes restrictions on the topology choices.
The main guideline is the choice of circuits with no more than two stacked transistors,
thus allowing sufficient voltage headroom to maintain the devices operating in saturation
region [12].

To help in the reduction of power consumption, the topology choices will try to min-
imize the number of circuit stages consuming static current.

2.1 Low-Noise Amplifier

The previous chapter introduced the LNA as an important block for the overall noise
figure level on the receiver, and also for performing the proper input matching with the
off-chip signal source. Implementations lacking a LNA block, with rather simpler input
matching and direct downconversion of the received signal exist [10], yet resulting in a
substantial increment in the system’s noise figure.

Considering those attributes, the following analysis present the topology choice, and
formulation of input and output impedances, noise, gain, linearity and stability relations.
Moreover, a design procedure based on the gathered formulations is presented.
 30

2.1.1 Topology choice

To minimize noise contribution, LNAs usually employ a minimal number of devices

and stages, often been implemented as an one-stage amplifier [27]. The circuits can be
implemented as differential or non-differential input. Differential input is required when
the common-mode noise reduction is critical, but as it contributes with more power and
noise, due to the components being doubled, it is not considered when common-mode
noise requirements are moderate. Also, differential amplifiers need a balun to interface
with the antenna, adding extra external components.

As suggested by [12, 21, 26], the cascode common-source amplifier with inductive de-
generation topology, shown in Figure 2, is preferred for optimal noise reduction and yet a
satisfactory gain. Also, several recent reported works for BLE support the choice of this
topology for ULP design [5, 11, 35, 37, 38, 41, 42]. In [12], the analysis is extended for the
case of ULV design, observing that this type of topology is still feasible towards 0.5 V
supply voltage (VDD ). However, the design procedure has to be adapted, being aware of
the low overdrive voltage (VOV ). As a consequence of the massive VDD reduction relative
to the VT H , VOV may reach values below 100 mV, driving the MOSFET channel inversion
level towards weak inversion, hardly maintaining moderate inversion conditions [12]. This
condition is distinct to the usual operation of LNAs supplied with nominal VDD , often
operating at moderate to strong inversion [27].
 31

Vdd

Ld Cd
Cc
vOUT

M2
vIN Lg
M1

Ls

Figure 2: Cascode common-source LNA with inductive source degeneration and LC load.

Source: Author

Despite the advantages of the presented topology, inverter-based topologies are also
found among recent ULP implementations, thriving for better operating conditions in
ULV conditions [7, 33, 40, 43]. Albeit being a better choice for biasing in ULV condition,
the inverter-based topologies show a large bandwidth frequency response compared to the
cascode common-source presented. The LC tank, comprising inductor Ld and capacitor
Cd shown in Figure 2, result in a narrow bandwidth response, contributing to filter out-of-
band blockers [26]. The narrow bandwidth LNAs are a better choice, as filtering out-of-
band blockers supports the alleviation of band filtering in the subsequent stages, reducing
power consumption.

The use of a cascode configuration instead of a simple common-source is due to re-

verse isolation. In the cascode common-source, the path from the output node, vOU T to
the input node, vIN is isolated by the impedance composed by the M2 drain to source
capacitance, Cds,2 , drain to source resistance Rds,2 , and the gate to drain capacitance
from M1 , Cgd,1 , hence showing a larger isolation than only Cgd,1 , as found in the simple
common-source [44]. The capacitance Cc realizes the coupling with vOU T , filtering the
DC voltage from M2 drain terminal.
 32

2.1.2 Input Matching

The design of the LNA must ensure a proper input matching with the source impedance,
assuring the maximum power transfer [26]. Figure 3 shows the small-signal model of the
transistor M1 , from Figure 2. In the model, the drain connections are omitted, high-
lighting the characteristics of the input interface, at the gate node G. The input signal
is represented by the voltage source vs , having a impedance Zs . For maximum power
transfer, and avoiding signal reflection, the input impedance of the LNA, Zin , must be
equal to Zs [26].

Zs vin Lg G D

Cgs
vs gmvgs
S
Zin
Ls

Figure 3: Small-signal model of the transistor M1 , showing the input interface at gate
terminal.

Source: Author

The expression for the input impedance Zin is shown in Equation 2.1, where the
capacitance seen at the gate of M1 is approximately Cgs , the capacitance from gate to
source terminals.

The presence of the inductors Lg and Ls result in an impedance with real and imagi-
nary part, giving the necessary means to control the input matching.

 
1 gm1
Zin = j ω(Lg + Ls ) − + Ls (2.1)
ωCgs Cgs

where ω is the angular frequency at which the impedance is calculated; gm1 and Cgs
are the transconductance and gate to source capacitance of the transistor M1 , respectively.

In wireless systems such as BLE, the input terminal of the LNA is often connected
to an antenna having an impedance of 50 Ω [26]. To design a input matching resulting in
Zin = 50 Ω, its imaginary part, Im {Zin }, must be zero, and its real part, Re {Zin } must
be 50 Ω.
 33

gm1
The real part of Zin can be calculated to make L
Cgs s
= 50. And the imaginary part
1
reduced to zero, with ω(Lg + Ls ) = ωCgs
.

2.1.3 Output Matching

The analysis of the output matching is performed at the load connection, which con-
sidering the circuit in Figure 2 is made at the drain of the cascode device, M2 . Unlike the
input impedance, that has to match with the antenna’s 50 Ω impedance, the impedance
from the load of the LNA, ZL , often has a large real value. Hence, the matching of the
output impedance from the LNA, Zout , and ZL is not focused on maximum power transfer.
The impedance Zout is adjusted so that the resulting impedance, Zout ||ZL , has a resonance
frequency, ωc , at the center of the BLE frequency band, ωc = 2π × 2.44 × 109 rad/s.

Ld Cd vout

D
CM2
ZL
Zout

Figure 4: Small-signal model showing the load connection at the drain terminal of the
transistor M2 .

Source: Author

Equations 2.2 and 2.3 show the procedure for calculating a Cd value resulting in the
desired tuning of the LC load at ωc . In the equations, Ceq represents the equivalent capac-
itance from the parallel connection between the capacitance seen at M2 drain, represented
by CM 2 , and the capacitance from ZL .

1
ωc2 = (2.2)
Ld CCdd+C
Ceq
eq

1
Cd = (2.3)
ωc2 Ld − 1/Ceq

where ωc is the required tuning frequency for the LC load; Ld and Cd are the inductor
 34

and capacitor from the LC tank of Figure 2, respectively; CM 2 represent the capacitances
seen at the drain terminal of M2 ; And ZL represent the input impedance of the subsequent
stage.

2.1.4 Noise

The analysis presented in [26, 44] suggest that the noise in the amplifier seen in fig-
ure 2 is dominated by the noise source at the channel of M1 , the input MOSFET. It is
proved that the noise at M2 channel have a high-pass characteristic, being negligible for
the frequency range of interest in this work. If the noise from the drain inductor, Ld , is
concerned, the analysis can be approximated to that of an cascode common-source ampli-
fier with resistive load, where the noise is also dominated by the M1 channel. Therefore
the analysis is performed considering the noise sources in M1 .

Figure 5 shows the small-signal model for the transistor M1 , including the noise source
2 , the noise current at M
representing the noise generated by the source impedance, vn,s 1

gate, i2n,g , and the noise current at M1 drain, i2n,d .

Zs vin Lg G D

Cgs
2 i2n,g
gmvgs i2n,d
v n,s S

Ls

Figure 5: Small-signal model showing the the noise sources at the terminals of M1 .

Source: Author

The noise performance of the LNA is usually quantified using the Input Referred
Noise (IRN) or the Noise Figure (NF). The IRN measures the noise contributed by a
circuit referred to its input, as if the circuit was a noiseless block with IRN noise source
as input. The NF is the ratio of the input to the output SNR, as shown in Equation 2.4.
It indicates the ratio of noise magnitude in the output to the input, and is a more used
parameters, as it is measurable [26].

2
SN Rin Vn,out
NF = = (2.4)
SN Rout 2
Vn,in
 35

where NF is the LNA noise figure; SN Rin and SN Rout the signal-to-noise ratio of the
2 2
input and output signals, respectively; Vn,in and Vn,out are the mean square noise voltage
at the input and output of the LNA, respectively.

The NF can also be defined as the ratio of the total noise at the output to the noise
at the output due to the source impedance [26]. Equation 2.5 shows this relation, where
2
Vn,R s
|α|2 A2v stands for the output noise due to source impedance. The noise contributed
by the noise source at the gate is negligible [26] and will be omitted in this simplified
calculation.

2
Vn,R s
|α|2 A2v + Vn,out
2
NF = (2.5)
2
Vn,R s
|α|2 A2v

Zin
where α is the input attenuation factor, α = Zin +Zs
; Av the small-signal gain of the
2
LNA, and Vn,R s
the mean square noise voltage from the source resistance Rs .

If an ideal match condition is considered, the factor |α| equals 0.5, then |α|2 = 1/4.
2
Moreover, the noise from source resistance, Vn,R s
= 4kT Rs . Equation 2.6 shows the
equations with these considerations, where k stands for the Boltzmann constant and T
the temperature.

2
Vn,R s
A2v + 4Vn,out
2 2
Vn,out
N Fmatch = =1+ (2.6)
2
Vn,R A2v kT Rs A2v
s

where N Fmatch is the noise figure of the LNA for an optimal match between the source
resistance and LNA input impedance; k is the Boltzmann constant; And T the absolute
temperature in Kelvin.
2
From [26], the noise current at M1 channel can be described as In,d = 4kT γgm1 , where
γ is the ”noise excess coefficient” [26], and gm1 the transconductance of M1 . Thus, the
2
noise at the output node can be represented as Vn,out 2
= In,d × ro2 , where ro is the channel
resistance for the MOSFET operating in saturation region. The intrinsic voltage gain can
be calculated as AV = gm ro [44].

Equation 2.7 shows the resulting approximation of the noise figure. It allows to observe
the relations between each circuit parameter and the NF, enabling a noise aware design
procedure.

4γ
N Fmatch ≈ 1 + (2.7)
gm1 Rs
 36

where γ is the ”noise excess coefficient” [26]; And gm1 the input MOSFET M1
transconductance.

Equation 2.7 reveals a dominance and inverse relation of M1 transconductance, gm1 ,

to noise figure. As the transconductance is directly proportional to the bias current, lower
noise figure values would require higher power consumption.

2.1.5 Gain

The integrated inductors are not ideal, hence showing series resistance associated
with the inductance. This resistance can be related to the quality factor (Q) of the
inductor, which measures the ratio between the imaginary and real parts of the component
impedance, related to inductive reactance and the parasitic resistance, respectively. The
quality factor for a series parasitic resistance is described in equation 2.8, from [26].

ωL
Qs = (2.8)
Rs
where Qs is the quality factor for a series connected parasitic resistance; ω the operating
angular frequency in rad/s; L the inductance; Rs the equivalent parasitic series resistance.

Ideally, for signals in frequencies near the resonating frequency, ωc , of LNA’s LC tank
load, formed by Ld and Cd , the tank behaves as a open circuit, and the current from M1
drain flows directly to vOU T . However, in a real situation, the parasitic resistance results
in a lower load impedance at the resonating frequency. To better analyze this effect, a
series to parallel equivalence is performed, to describe the parasitic resistance as a parallel
element, Rp [26]. Figure 6 shows the LNA circuit and the parasitic resistance Rp parallel
to the LC tank at the load.

The quality factor for the parallel resistance is described in Equation 2.9, from [26].

Rp
Qp = (2.9)
ωL
where Qp is the quality factor for a parallel connected parasitic resistance; ω the oper-
ating angular frequency in rad/s; L the inductance; Rp the equivalent parasitic parallel
resistance.

If the quality factor Qp is known, the parallel resistance value can be estimated and
used for further voltage gain calculation. Using the relation in Equation 2.9, Rp = ωLd Qp .
 37

Vdd

Ld Rp Cd
vOUT

M2 Cc
Lg
vIN
M1

Ls

Figure 6: Cascode common-source LNA with inductive source degeneration, including

equivalent parallel resistance from load inductor parasitics.

Source: Author

The voltage gain can be obtained using the relation Av = −Gm Rout , using two-port
analysis [44], where Gm is the total transconductance of the circuit, and Ro ut its output
impedance. If the channel resistance of M1 is neglected, Gm = gm1 Qin , where Qin is the
input quality factor 1/(Zin ωCGS ). Equation 2.10 shows the resulting expression for the
LNA in figure 6.

Av = Gm (Rp ||gm2 ro1 ro2 ) ≈ Gm Rp = gm1 Qin ωLd Qp (2.10)

where Av is the LNA voltage gain; Gm its total transconducance; gm1 and gm2 the
transconductance from M1 and M2 , respectively; ro1 and ro2 the channel resistance from
M1 and M2 , respectively.

The resulting gain expression shows a direct relation with gm1 , Ld and Qp . Therefore,
to obtain high gain with low power consumption, the inductor have to be designed to
have a high Q, and high inductance, thus avoiding increments in gm1 .
 38

2.1.6 Linearity

The linearity analysis of the LNA is performed by applying a two-tone test, allowing
to observe intermodulation and gain compression effects. The test involves applying two
tones with equal magnitude at the LNA input, and measuring the resulting intermodu-
lated signal at the output. Varying the input magnitude, it is observed a higher increment
in the third-order component of the signal, characterized by the coefficient α3 , than in
the first-order one, characterized by the coefficient α1 . Thus, the point of convergence
between the first and third order responses is calculated as the Third-Order Intermod-
ulation Intercept-Point (IM3 ). The input magnitude related to the IM3 is the Input
Third-Order Intermodulation Intercept-Point (IIP3 ), and represent the input magnitude
at which the magnitude of the third-order component starts to dominate the signal over
the first-order [26].

Also, the first-order magnitude output can be observed to find the point at which the
gain falls by 1 dB, representing the 1-dB Compression Point (P1dB ).

Equations 2.11 and 2.12 show the IIP3 and P1dB expressions, respectively, as a func-
tion of the first order coefficient, α1 , and the third order coefficient, α3 . The expressions
for the coefficient values are given in equations 2.15 and 2.17, respectively.

s
4 α1
IIP3 = (2.11)
3 α3

s
α1
P1dB = 0.145 (2.12)
α3

Equations 2.15, 2.16 and 2.17 show the expressions for the first, second and third order
coefficients, respectively, for a cascode common-source amplifier with source degeneration
[44], where the degeneration is represented by a resistance, Rs , comprising the inductor
Ls parasitic series resistance. For the development of the expressions, a large-signal model
of the transconductance of the transistor M1 , gm0 , is used as presented in equation 2.14.
The factor K in the gm0 expression stands for the CMOS technology parameters at M1
current expression [44], mobility µN and gate oxide capacitance, Cox .

 
1 W
K = µN Cox (2.13)
2 L M1
 39

gm0 = 2K(Vgs − Rs ID − VT H ) (2.14)

∂ID gm0
α1 = = (2.15)
∂Vgs 1 + gm0 Rs

∂ 2 ID 1 K
α2 = 2
= (2.16)
∂Vgs 2 (1 + gm0 Rs )3

∂ 3 ID 1 2K 2 Rs
α3 = = − (2.17)
∂Vgs3 6 (1 + gm0 Rs )5

where µN is the carrier mobility for M1 substrate; Cox is the gate-oxide capacitance
of M1 ; W and L are the width and length of M1 ’s gate; gm0 is a large-signal model of the
transconductance of the transistor M1 ; Vgs the gate to source voltage in M1 ; Rs is the
equivalent parasitic series resistance of inductor Ls from figure 2; ID is the large-signal
current in M1 ; VT H is the threshold voltage of transistor M1 ; α1 , α2 and α3 are the first,
second and third order coefficients for the current in M1 .

The expressions given in the Equations 2.15, 2.16 and 2.17 can be applied in Equation
2.11 to analyze the IIP3 behavior as a function of the circuit parameters. The resulting
expression is shown in Equation 2.18.

r
2 gm0 (1 + gm0 )2
IIP3 = (2.18)
3 Rs K

Equation 2.18 shows that the linearity of the circuit benefits from the increment of gm0
and the improvement of the quality factor of the inductor Ls , resulting in Rs reduction.

The same substitution is made in the 1-dB compression point expression given by
2.12, resulting in the expression of the Equation 2.19. The expression shows that the
increment on P1dB benefits from the increment of gm0 and the improvement of the quality
factor of the inductor Ls , resulting in Rs reduction, as with IIP3 .

s r
α1 2 gm0 (1 + gm0 )2
P1dB = 0.145 ≈ 0.1IIP3 = (2.19)
α3 3 Rs 10K
 40

2.1.7 Stability

The K stability factor, K > 1, must be satisfied to guarantee stability with any load
and source impedance [26]. Equation 2.20 shows its expression, where it is possible to
observe a relation with the scattering parameter (S-Parameters) from the two-port derived
S-Parameter analysis of the LNA circuit [26].

1 + (S11 S22 − S12 S21 )2 − |S11 |2 − |S22 |2

K= (2.20)
2|S21 ||S12 |
where K is the stability factor [26]; S11 , S12 , S21 and S22 are the scattering parameters of
the LNA.

Assuming a high reverse isolation and relatively high output impedance, a usual sce-
nario in integrated LNAs [26], the expression can be reduced to the one shown by Equation
2.21.

1 − |S22 |2
K= (2.21)
2|S21 ||S12 |

Hence, LNA can be stabilized by maximizing its reverse isolation. The chosen topology
contributes for that, as the addition of the cascode transistor increases the reverse isolation
compared to the common-source amplifier.

2.1.8 Design Procedure

The design procedure of the LNA involves the use of the knowledge acquired with
the expressions for matching, noise, gain and linearity applied for sizing of the circuit,
fulfilling the specification requirements.

Figure 7 shows the full circuit for the LNA including bias network and parasitic
devices. Transistor M3 , and resistors Rb1 and Rb2 comprise the biasing circuit, responsible
for generating the DC common-mode voltage at the gate of M1 , biasing it to the required
overdrive voltage.

The resistor Rbw and inductor Lbw relate to the resistance and inductance from the
bonding wire connecting the die pad to the chip external pin, respectively. The capaci-
tances Cpin and Cpad are the external pin and internal die pad capacitances, respectively.
 41

Vdd

Rb1 Vdd

Rb2 Ld Cd
M3 vOUT

M2 Cc

Cc Lg
vIN Rbw Lbw
M1

Cpin Cpad

Off-Chip Ls
Parasitic devices

Figure 7: LNA circuit showing the biasing circuit, and off-chip parasitic passive elements.

Source: Author

As a suggestion for the circuit sizing, the following steps may be applied.

For an ULV design, it is important to assure that the transistors are capable of
operating at the required frequency range. Equation 2.22 shows the expression for the
transistor M1 transfer frequency, a measure of the maximum frequency in which the
transistor allows amplification [44]. Therefore, it is required that fT  fb , where fb
represents the maximum frequency in the required operating frequency band.

gm1
fT = (2.22)
2πCgs

where fT is the transfer frequency for MOSFET M1 ; gm1 is the transconductance of

M1 ; And Cgs is the gate to source capacitance of M1 .

Therefore, due to the low overdrive voltage imposed by the ULV supply, gm1 requires
a carefully inspection as to assure the required fT . For the operation in saturation region,
the capacitance Cgs may be approximated to Cgs ≈ (2/3)W LCox , where W and L are
the MOSFET width and length, respecively, and Cox its gate-oxide capacitance. The
transconductance, gm1 can be defined as gm1 = µN Cox (VOV ), where VOV is the overdrive
voltage, VOV = VGS − VT H , and µN is the carrier mobility at M1 channel.

Equation 2.23 shows the resulting expression after replacing the referred quantities.
It implies that, at minimum channel length, a minimum VOV must be satisfied to allow
the operation in the required frequency range. The minimum VOV must be determined at
 42

the design beginning, thus setting a limit for the input common-mode voltage. Moreover,
the MOSFET VT H have its value related to the transistor length, thus an analysis may
be applied on finding the optimal length for maximum fT response.

3 VOV
f T ≈ µN 2 (2.23)
2 L
where L is the channel length of M1 .

Then, for the input matching realization, the expression of Zin is observed. Its real
gm1
part, L
Cgs s
can be changed into the relation in Equation 2.24, where ωT is the angular
transfer frequency, gm1 /Cgs and Ls the source inductance.

Re {Zin } = ωT Ls (2.24)

where Re {Zin } is the real part of the input impedance Zin ; And ωT is the angular transfer
frequency for MOSFET M1 .

Since ωT = 2πfT , the value of Re {Zin } can be adjusted by changing the value of the
inductor Ls , or changing VOV , if possible.

The value of the gate inductor, Lg , is chosen to set the imaginary part of Zin , Im {Zin },
to zero.

The frequency of the minimum noise figure is related to M1 channel width [27], which
can be adjusted to set the minimum noise figure at the center of the frequency range of
interest.

The size for M2 can be the same obtained for M1 , helping to achieve a better layout
matching.

The load inductor Ld is chosen to adjust the gain, where a quality factor maximization
is favorable for a large gain. Moreover, the capacitor Cd is sized to set the load resonating
frequency at the center of the frequency range of interest.

2.2 Mixer

The Mixer block is responsible for frequency translation in the receiver. In the case
of the RF Front-End at the receiver, it is referred as downconversion mixer, due to its
characteristic of converting a high frequency input signal in a low frequency output.

As shown in Equations 2.25 and 2.26, the mixer function applies a multiplication
 43

between the sinusoidal signals coming from the LNA and from the LO. The multiplication
results in a frequency translated output, with a low frequency component at ωRF − ωLO
and other high frequency component at ωRF +ωLO . In the case of a downconversion Mixer,
the low frequency component is the signal of interest, and the high frequency component
will be filtered out by the next stages of the receiver.

ymixer = A1 cos(ωRF t) × A2 cos(ωLO t) (2.25)

1
ymixer = [A1 A2 cos(ωRF − ωLO ) + A1 A2 cos(ωRF + ωLO )] (2.26)
2

where ymixer represents the signal at the output of the mixer block; A1 and A2 are
the peak amplitude of the RF signal coming from the LNA and the signal from LO,
respectively; ωRF and ωLO are the angular frequency of the sinusoidal signal representing
the output of the LNA and LO, respectively.

The following analysis present the topology choice, and development of expressions
that describe the Mixer noise, gain, linearity and input impedance behavior. Moreover, a
design procedure based on the gathered expressions is presented.

2.2.1 Topology Choice

Recent works show a strong tendency in using a passive topology to implement the
downconversion Mixer [7,11,33,43], reinforcing the benefits of applying it to ULP designs.
Also, its passive structure does not demand great voltage headroom.

As shown in figure 8, the simple structure of a single-balanced passive mixer is com-

posed by two MOS switches, that modulate the input single-ended signal into a differential
signal containing the high and low signals resulting from the frequency translation [26].
 44

vLOp

vIFp
vOUT,LNA M1

M2 vIFm

vLOm

Figure 8: Single balanced passive mixer circuit based on MOS switches.

Source: Author

As suggested by [26], the use of a sampling mixer, or ”non return to zero” (NRZ)
mixer, using capacitors as load, as in sample-and-hold circuit, results in a gain slightly
above 0 dB.

2.2.2 Noise

For the mixer, Single Side-Band (SSB) noise is considered. It gets contribution from
image band, having 3dB noise contribution despite of mixer circuit contribution [26].

For Zero-IF receivers, the major concern is in reducing the noise around DC, employing
techniques to reduce the flicker noise from the MOSFETs [45, 46]. However, in a Low-IF
implementation, as the signal of interest will be centered at an IF frequency, the flicker
noise is not a major concern, allowing the implementation of a DC biased passive mixer
[26, 47]. The DC biased mixer brings the advantage of having a larger input impedance,
avoiding the need for a buffer stage in the LNA, as in the case of a current-driven mixer.
Also, it allows the interfacing with a high impedance load at the IF stage, apart from the
current-drive that often requires a Transimpedance Amplifier (TIA) interface [33, 45].

In this work, the implementation of a Low-IF receiver is considered, alleviating the

concern about the flicker noise near DC spectrum. Figure 9 shows the single-balanced
passive mixer topology, along with the noise sources related to RON resistance.
 45

vLOp CL
2
RON v n,ron
vIFp

+
−
vOUT,LNA M1

M2

+
−
vIFm
RON 2
v n,ron
vLOm CL

Figure 9: Passive mixer showing RON resistances and their related noise voltage sources
2
vn,ron .

Source: Author

A complete analysis of the thermal noise behavior in the RON resistance is presented
by [47], where the noise behavior is presented for the periods when the switch is on or off.
Simplifying the expression shown in [47], it is possible to see that in any case the thermal
kT
noise spectral density is proportional to C
, where k is the Boltzmann constant, T the
absolute temperature in Kelvin, and C the capacitance connected to the switch, in the
case of Figure 9 being represented by CL , the input capacitance of the next stage.

This noise behavior is expected in the analysis of sample-and-hold circuits with a

similar arrangement of MOS switch and capacitor [48]. Therefore, this result suggests
that a possible design procedure to adjust noise contribution from the mixer is to control
the capacitance seen in its output, although this approach may be difficult due that it is
not always possible to control the sizing of the next stage.

2.2.3 Gain

In [26], an extensive analysis on the gain of the sampling mixer is presented, based on
the study of the discrete-time system response for when the switch is on, and the mixer
is sampling the input signal, and for when the switch is off, in which the load capacitor
holds the previously sampled signal.

Equation 2.27 shows the gain relation for the mixer, where Y1 (f ) and Y2 (f ) represent
the response of the MOS switch and capacitor pair in the sampling and hold periods,
respectively [26]. It is possible to see the frequency translation on the input X(f ) to
 46

X(f ± fLO ) at the mixer output, where a high frequency and low frequency components
are generated.

r
1 1
|Y1 (f ) + Y2 (f )| = + |X(f ± fLO )| = 0.593|X(f ± fLO )| (2.27)
π2 4

where Y1 (f ) and Y2 (f ) represent the response of the MOS switch and capacitor pair in
the sampling and hold periods, respectively; X(f ±fLO ) is the input signal after frequency
translation, generating a high and a low frequency components.

For the case of the single-balanced circuit in Figure 8, where two MOS switch and
capacitor pairs are implemented with complementary LO signal, the gain result is doubled,
as shown in Equation 2.28.

Equation 2.28 shows the case of single-balanced topology gain.

|Y1 (f ) + Y2 (f )| = 2 × 0.593|X(f ± fLO )| = 1.186|X(f ± fLO )| ≈ 1.48dB (2.28)

This result shows a gain above 0 dB for the mixer, a satisfactory result for a passive
circuit. The presence of a gain instead of an attenuation in this passive circuit is due to
the sample-and-hold effect at the capacitors [26].

2.2.4 Linearity

The On-Resistance of MOS switches in a sampling circuit varies with the input and
output levels [44], therefore affecting the signal linearity. For an input signal vIN (t) =
V0 cos(ω0 t) + VM , where VM represents the mean value, and V0 = VDD /2, the output
voltage held at the capacitor is represented by Equation 2.29.

V0
cos ω0 t − tan−1 (Ron CL ω0 ) + VM
 
Vout (t) = p (2.29)
2 C 2 ω2 + 1
Ron L 0

where Vout (t) is the output voltage held by the load capacitor CL ; V0 is the mean
voltage level of the input signal; Ron is the on-resistance of the MOS switch; CL is the
load capacitor at the output of the mixer; ω0 is the angular frequency of the input signal
in rad/s.

The bandwidth must be large to negligibly attenuate the signal, thus Ron C1 ω0  1.
 47

With periodic input, Ron varies periodically, therefore can be approximated by a

fourier series, as seen in Equation 2.30.

Ron (t) = R0 + R1 cos(ω0 t) + R2 cos(2ω0 t) + · · · (2.30)

where Ron (t) is the time-varying on-resistance of the MOS switch; Rn the coefficients
for each harmonic n; ω0 is the angular frequency of the input signal in rad/s.

Based on the Equation 2.30, the total harmonic distortion (THD) in the mixer can
be calculated, as seen in Equation 2.31. The THD thus serves as a metric for the mixer
nonlinearity.

R12 + R22 2 2
T HD = CL ω 0 (2.31)
4

where THD is the total harmonic distortion measurement for the MOS switch and
capacitor mixer; R1 and R2 are the coefficients for the first and second harmonics, respec-
tively; CL is the load capacitance at the output of the mixer; ω0 is the angular frequency
of the input signal in rad/s.

The expression in 2.31 suggests that the distortion may be alleviated by minimizing
the capacitance CL . Also, the hamonics’ coefficients R1 and R2 can be obtained by
derivating the resistance function in the time-domain, shown in Equation 2.32.

1
RON (t) = (2.32)
kn0 W
L
(VDD − vIN (t) − VT H )

As shown in [44], the resistance of the switch rapidly grows as VDD − vIN approaches
VT H , stating that the switch is approaching the off-state. Therefore, an operation condi-
tion where the signal vIN (t) spans a peak-to-peak value of VDD − VT H is the worst case
for distortion, as the steeper RON (t) response in time would result in great values for the
harmonic coefficients R1 and R2 , related to the time-domain derivative of RON (t).

Therefore, a proper design strategy to minimize distortion is to minimize CL , and

work with peak-to-peak vIN span much less than VDD − VT H , or vIN (t)max  VDD − VT H .
 48

2.2.5 Input Impedance

The input impedance analysis for the sampling mixer is based on its discrete-time
behavior, where the input impedance Zin,sb of the single-balanced passive mixer is derived
from the expression of its frequency-domain current response, Iin (f ), and the input signal
in frequency domain, X(f ), as reported in [26]. Result in the final expression is shown in
Equation 2.33.

 
1 1
Zin,sb (ω) = RON + (2.33)
2 jωCL

The result for the input impedance Zin,sb will be applied in the RF Front-End design,
where it will represent the load impedance seen in the output of the LNA.

2.2.6 Design Procedure

The following design steps are suggested in this work for the Mixer design, where its
bandwidth, linearity and DC biasing is concerned.

The Mixer bandwidth, gave by the relation of its time-constant RON CL , suggests that
as CL is often given by the input capacitance of the subsequent stage, the value of RON
1
may be calculated, so that RON CL
 ωc , where ωc stands for the maximum frequency of
the input signal.

For linearity improvement, the relation obtained in the previous Linearity section
must be satisfied, thus vINmax < VDD − VT H .

Figure 10 shows the DC bias placement for the mixer. Ideally, a common-mode value
of vIN max /2 may be defined for the mixer DC biasing voltage Vb , thus assuring the required
operation or a peak-to-peak vIN of vIN m ax.
 49

Buffer
vLOp

CL
vIFp
vOUT,LNA Cc
M2

M1 vIFm
Rb

Vb CL
vLOm

Buffer

Figure 10: Single-balanced passive mixer circuit showing biasing and LO buffers.

Source: Author

2.3 RF Front-End with LNA and Passive Sampling

Mixer

Figure 11 presents the connection of the LNA and mixer, forming the RF front-end
circuit. Since the design of the Mixer changes the input impedance seen by the LNA,
and other parameters of the LNA depend on the mixer performance, such as LNA gain
related to mixer noise, it is expected that design iterations have to be made to assure the
maintenance of the desired performance for the two blocks.

Therefore, the design procedure for the RF Front-End may start with the LNA design,
using a expected theoretical load impedance value, based on the previously presented
input impedance expression for the Mixer. After, the design of the mixer, using the data
from the impedance of the subsequent block, and performance specifications of the input
signal, linearity and noise is done. Finally, the inspection of the two blocks connected,
forming the RF Front-End, and adjustment of the performance parameters are executed.
 50

Vdd
Buffer
vLOp
Rb1 Vdd

CL
vIFp
Rb2 Ld Cd
M3 M2

M2 Cc M1 vIFm
Rb

Cc Vb CL
vIN Rbw Lbw Lg
vLOm
M1
Buffer
Cpin Cpad

Off-Chip Ls
Parasitic devices

Figure 11: RF Front-End circuit showing LNA and Mixer circuits with the chosen topolo-
gies.

Source: Author
 51

3 IMPLEMENTATION AND EXPERIMENTAL

RESULTS

This chapter includes the implementation of the circuits proposed for the solution of
the stated problem. Three design implementations are presented, using 180nm CMOS
technology and 130nm CMOS technology.

The first design corresponds to the first approach to design a LNA with a reduced
voltage supply of 0.5 V, minimizing its power consumption. Using the theoretical formu-
lations from the methodology chapter, the boundaries of the solution are analyzed. Thus,
resulting in a good start point for performing the simulations. The initial assumptions are
used to perform the design using a 180nm CMOS technology from TSMC. The problem
of having a VT H near to the supply voltage is studied, applying the forward bulk biasing
technique when necessary [12, 49, 50].

The second design uses the same 180nm CMOS technology, making an effort to en-
hance the performance seen on the first design, changing parameters related to gain,
linearity, matching and power consumption.

The third design uses a 130nm CMOS technology from GlobalFoundries, and applies
the knowledge obtained from the LNA designs, extending it to implement a sampling
mixer and an IF amplifier.

All the designs include further study on post-fabrication tests. The design of test
boards and strategies for testing the integrated circuits performance are included. More-
over, the designs of the integrated circuits include adjustable biasing structures and Buffer
circuits to support the test procedures.

The designs include a Buffer circuit, intended to match the output of the circuit in the
last stage with the 50 Ω input impedance of the measuerement equipment. This approach
guarantees that the circuit’s gain is not affected. In each design case, the Buffer topology
choice is detailed showing the benefits of each choice.

During the design, the performance of the circuits is evaluated using schematic and
 52

post-layout simulations. The design and simulations were realized using software tools
by Cadence Design Systems. The schematic capture and layout used is the Virtuoso, the
simulations were configured using the Analog Design Environment (ADE) and performed
using the Spectre simulator. Assura was used for the layout verification, including design
rule check (DRC) and layout versus schematic (LVS) simulations. Quantus QRC was
used for the parasitic extraction after the layout verification. The post-layout simulations
were performed with ADE and Spectre using the extracted models from Quantus QRC.
Moreover, Mentor Calibre software was also used for design rule check (DRC) simulation
after the circuits layout.

After the design of the integrated circuits, the design of the test structures have been
performed. The Autodesk EAGLE software was used for the design of printed circuit
boards (PCB) to perform the interface between the fabricated integrated circuits and
the test equipment [51]. In the PCBs are included interface circuits for the RF inputs
and outputs, such as passive matching networks and SubMiniature version A (SMA)
coaxial connectors. Moreover, structures for DC biasing setting are also included. The
PCB design mostly used surface-mounted devices (SMD) to reduce the board area, as
well as to reduce path lengths and component parasitics, thus reducing the performance
degeneration in RF circuits.

The Keysight ADS software was used to aid in the sizing of the PCB tracks in the RF
signal paths. Those tracks were considered transmission lines, observing the reflection and
phase displacement through the track. The LineCalc tool in ADS was used, based on the
FR-4, material of the PCB substrate, its permittivity, the substrate thickness and track
length. The track width was designed for a characteristic impedance of 50 Ω, making an
optimal matching with the test equipment and the integrated circuits.

In the first design, including integrated LNA and Buffer circuits fabricated using
180nm CMOS technology, the chip-on-board method [52] was used to connect the fabri-
cated die to the PCB. Wire bonding was used to connect the pads of the fabricated die
to the PCB pads. The other two designs used standard SMD packages instead.

Tables 4, 5 and 6 present the design specifications for the RF Front-End, the LNA
and the Mixer blocks, respectively. The specifications are to be followed as the design
objective for the blocks in this chapter.
 53

Table 4: Design specifications for the RF Front-End design following BLE specification.
Parameter Value
Supply Voltage 0.5 V
Power Consumption < 1 mW
Noise Figure, SSB < 20 dB
Input Power ≤ -20 dBm
1 dB Compression Point > -35 dBm
IIP3 > -25 dBm
Conversion Gain > 10 dB
Input Reflection Ratio (S11 ) < -10 dB
Input Impedance 50 Ω
Input frequency band 2.4 GHz - 2.4835 GHz
Input center frequency 2.44 GHz
Output Intermediate Frequency 2 MHz

Table 5: Design specifications for the LNA design following BLE specification.
Parameter Value
Supply Voltage 0.5 V
Power Consumption < 1 mW
Noise Figure < 10 dB
Input Power ≤ -20 dBm
1 dB Compression Point > -35 dBm
IIP3 > -25 dBm
Power Gain (S21 ) ≥ 10 dB
Input Reflection Ratio (S11 ) < -10 dB
Input Impedance 50 Ω
Input frequency band 2.4 GHz - 2.4835 GHz
Input center frequency 2.44 GHz
 54

Table 6: Design specifications for the Mixer design following BLE specification.
Parameter Value
Noise Figure, SSB < 20 dB
1 dB Compression Point > -35 dBm
IIP3 > -25 dBm
Conversion Gain ≈ 0 dB
Input frequency band 2.4 GHz - 2.4835 GHz
Input center frequency 2.44 GHz
Output Intermediate Frequency 2 MHz

3.1 First LNA design in 180nm CMOS technology

The first design implementation included in this work is a cascode common-source

LNA with inductive source degeneration in 180nm CMOS technology. The device pa-
rameters are based on a process design kit (PDK) from the TSCM foundry. The PDK
also includes simulation models using BSIM3 standard and design rules files for layout
verification.

The design follows the chosen specifications, which include supply voltage (VDD ) at
0.5 V. The main design objective is to minimize power consumption, keeping a gain value
higher than 10 dB and noise figure below the calculated maximum. Thus, the transistors’
operation must be driven towards weak inversion, which brings difficulties to RF design,
since the maximum operational frequency is reduced on this inversion mode. Therefore,
the devices are required to achieve a transconductance level that results in a good gain
and noise figure performance.

Due to reverse short-channel effect, The threshold voltage (VT H ) behavior in the
180nm CMOS technology used in this work increases as the channel length approaches the
technology minimum [53]. Consequently, the design for operation at higher frequencies,
despite benefiting from channel length reduction, has an added complexity for low supply
voltage due to the VT H behavior.

The first design also includes a Buffer in a common source configuration with current-
source load topology. The Buffer is designed to have a gain near to 0 dB. Thus, it has low
impact on the measured gain, which approximates the LNA gain. However, compared to
the other buffer designs in this work, shows a larger area, power consumption, and an
added complexity to define the output common-mode voltage [44].
 55

Figure 12 shows the full design of the LNA and Buffer, showing integrated and discrete
parts, as well as the board and chip parasitic devices.

The considered parasitic passive devices come from the bondwire, internal pad and
PCB or package pins. Rbw and Lbw stand for the bondwire resistance and inductance,
respectively [54]. Cpin and Cpad represent the capacitance from off-chip connection and
integrated pad, respectively. Cpin may receive capacitive contributions from package pins,
when the die has a package, or solely PCB connection when chip-on-board connection
is used. The parasitic devices from bondwires, pads and pins are present in connections
between the integrated circuits and off-chip components. Those parasitic components
are represented in the circuit by the impedance values Zpar in and Zpar out . The resistors
Rbias adjust the reference current Ibias biasing the LNA and Buffer circuits. Cc and Cc int
capacitors perform the ac coupling between input source and LNA input pin, and between
LNA output and Buffer input, respectively. The input matching network, responsible for
controlling the LNA input impedance Zin is realized using inductor Lmatch and capacitor
Cmatch .

Apart from the devices represented inside the rectangle with label ”Integrated” and
Cpad , all elements in the figure represent off-chip devices or parasitic entities.

Rbw Lbw Rbw Lbw

Cpin Cpad Cpad Cpin

Zpar_out
Zpar_in Vcap Zpar_in
Vdd_buffer
Vdd
Rbias Zpar_in
Rbias
Integrated

Rs Cc Lmatch Cc_int Cc

Zpar_in LNA Buffer Zpar_out

Vsource Cmatch RL

Lbw Lbw
Input Match
Rbw Rbw
Zbw Zbw

Figure 12: The implemented cascode common-source LNA with inductive source degen-
eration and common-source Buffer circuit in 180nm CMOS technology.

Source: Author
 56

Cpin and Cpad are estimated values based on connection dimensions. Cc is chosen to
be a value to give a sufficient low frequency high-pass cutoff, performing the required
signal coupling. Load resistance RL value is based on the standard load resistance of the
measurement equipment.

The resulting dimensions for the LNA and Buffer circuit are shown in Table 7.

Table 7: Device dimensions for the LNA and buffer circuit.

Parameter Value
Rs 50 Ω
Rbias 3 kΩ
Rbias,buf f er 5 kΩ
Lmatch 9.88 nH
Cmatch 1.85 pF
Rbw 1Ω
Lbw 1 nH
Cpin 100 fF
Cpad 100 fF
Cc 100 nF
RL 50 Ω
VDD 0.5 V
VDD buf f er 1.8 V

Figure 13 shows the LNA circuit, implementing the cascode common-source with in-
ductive degeneration topology, along with parasitic and external components. The topol-
ogy was adapted from the one shown in the methodology chapter of this work. The LC
tank capacitor was replaced for a variable capacitor to allow adjustments on the resonat-
ing frequency of the LC tank after fabrication. The gate inductor was removed from the
integrated circuit and is implemented as off-chip by the matching network inductor Lmatch .
The source inductor was also removed, being replaced by the bondwire inductance on the
source terminal, Lbw . The removal of the gate and source inductors resulted in a substan-
tial reduction on the circuit area after the layout phase. Moreover, the implementation
added terminals for bulk biasing of the MOSFETs.

The elements in the input match circuit, and parasitic devices in Zpar in are the same
as described for the LNA and Buffer circuit.

Transistor M3 drain voltage is defined by the sizing of M3 and the incoming Ibias , and
 57

set the input common-mode voltage of M1 . The resistor Rbias combined with M3 gate
capacitance perform a low-pass filtering, avoiding signal leakage from the input node.

Cc and Cc int capacitors perform the ac coupling between input source and LNA input
pin, and between LNA output and Buffer input, respectively. The input matching net-
work, responsible for controlling the LNA input impedance Zin is realized using inductor
Lmatch and capacitor Cmatch .

As with the LNA and Buffer circuit, input match, Zpar in and Zbw represent off-chip
devices or parasitic entities.

CL represents the load capacitance, in this case coming from the input of the Buffer
stage.

LD act as a tuned load for the amplifier, and is designed to give the required gain,
based on its embedded parallel resistance.

CD is a variable capacitor that permits adjusting the output matching of the circuit
with LD and CL .
Zpar_in Zpar_in
Ibias VDD
Zpar_in
Vcap
M3 Rbias LD CD
Vbody
Cc_int
Zbw Vout
M2

Vbody CL
Cc Lmatch Rbw Lbw M1
Pin

Cmatch Cpin Cpad

Lbw
Zbw
Zpar_in
Input Match Rbw

Figure 13: The cascode common-source LNA with inductive source degeneration circuit
in 180nm technology, along with parasitic and other external devices.

Source: Author

The LNA circuit design followed the steps of the design strategy proposed in the
methodology chapter of this work. The PDK parameters were observed through simu-
lations with the available NMOS and PMOS transistors. As suggested in the proposed
 58

strategy, the first approach is to verify if the transfer frequency (fT ) for the MOSFETs
biased with 0.5 V supply is sufficient to allow the operation in the desired frequency range,
between 2.4 GHz and 2.4835 GHz.

This design comprises VT H reduction using the forward bulk biasing (FBB) approach
[12, 49, 50]. This technique uses a positive bulk to source voltage VBS , as a way to lower
the threshold due to depletion region length reduction on the MOSFET substrate.

Equation 3.1 [44] shows the relation between VT H and the bulk to source voltage VBS .
For φF representing the fermi potential, with voltage level between 0.3 V and 0.4 V.

p p 
VT H = VT H0 + γ 2φF − VBS − 2φF (3.1)

where VT H is the MOSFET threshold voltage; VT H0 is the MOSFET threshold voltage

component without body effect; γ is the body effect coefficient; φF is the fermi potential
for the bulk semiconductor; Vbs is the voltage potential between the MOSFET bulk and
source terminals.

Table 8 shows the fT response as a function of the applied VBS voltage, simulated
using the technology device models for a nMOS transistor, the same used for the input
stage of the amplifiers in this design. The nMOS device used a minimum channel length
of 180nm. It shows that for a biasing without applied FBB the fT would not be sufficient
for the desired operational frequency range.

Table 9 shows the simulated threshold voltage response as a function of the applied
VBS voltage for a nMOS transistor using a minimum channel length of 180nm. Again,
the results show VT H values matching the design needs for higher VBS values.

Table 8: Transfer frequency response as a function of the applied bulk to source voltage.
VBS (V ) 0 0.1 0.2 0.3 0.4 0.5
fT (GHz) 0.95 1.7 2.9 4.8 7.5 11

Table 9: Threshold voltage response as a function of the applied bulk to source voltage.
VBS (V ) 0 0.1 0.2 0.3 0.4 0.5
VT H (V ) 0.55 0.52 0.49 0.46 0.425 0.39

While resulting in satisfactory reduction of the VT H , applying FBB exponentially

increases the current leakage through the forward biased junction between bulk and source
 59

terminals, and therefore, leading to additional power consumption and possible latch-up
failure. To account for those drawbacks, the VBS voltage used in the FBB has to be
constrained to a maximum harmless value. The maximum voltage of 0.5 V considered
for this design assures that the critical current conduction levels in the forward biased
junction are not achieved.

Moreover, the increased bulk potential also results in a reduction of the depletion
region length in the MOSFET substrate. This effect leads to higher device capacitances.

The choice of the input common-mode gate voltage, VCM , was based on the results
showed in the fT simulations as a function of VGS and the channel length. A VCM of 400
mV is proposed, giving a room for maximum 200 mVpp input, or -10 dBm. A safety
margin is added, considering maximum -20 dBm input, with maximum 100 mVpp input
signal.

Following, the input matching is performed, by analyzing the impedance of the LNA
input, and applying L-type network match procedure to achieve a input impedance of 50
Ω [26]. The L-type network was implemented by the Lmatch and Cmatch components.

The width of M1 was adjusted to set the minimum noise figure response at the center
of the required input signal frequency range [27, 55].

After the input matching, the value of the inductor LD was adjusted to achieve the
required gain. Moreover, the center of the capacitance range given by CD is set to match
the LC tank with the capacitance from the subsequent stage’s input and the capacitances
attached to the drain of M2 .

The resulting dimensions for the LNA circuit are shown in Table 10.

The value of the parasitic devices and coupling capacitor Cc are the same for the LNA
and buffer circuit. The value of Lmatch and Cmatch from the input matching circuit are
also the same as given in table 7.

Transistors M1 and M2 dimensions are given by the ratio of their channel width and
length.
 60

Table 10: Device dimensions for the LNA circuit.

Parameter Value
M1 , M2 128 µm/ 0.18 µm
LD 1.16 nH
CD 0.3 - 1 pF
Rbias 16 kΩ
Cci nt 7 pF
Vbody 0.5 V

Figure 14 shows only the Buffer circuit, implementing the cascode common-source
topology, along with parasitic and external components.

For this circuit and the following implementations shown in this work, unless otherwise
represented or stated, the bulk terminals of NMOS and PMOS transistors are connected
to ground and VDD pins, respectively.

The elements in the input match circuit, and parasitic devices in Zpar in are the same
described for the LNA and Buffer circuit.

The M5 drain voltage acts as common-mode reference to transistor M1 . Its drain

W
voltage is defined by the relation of its aspect ratio, L
, R1 and Ibias . Moreover, it is a
current reference for M3 and M4 . M3 and M2 set the DC bias current for the output in the
drain of M1 . The resistor Rbias combined with M5 gate capacitance perform a low-pass
filtering, avoiding signal leakage from the input node.

Cc and Cc int capacitors perform the ac coupling between Buffer output and output
pin, and between LNA output and Buffer input, respectively.

As with the LNA and Buffer circuit, input match, Zpar in and Zbw represent off-chip
devices or parasitic entities.

Transistor M1 and M2 are designed to have gain near 0 dB with a 50 Ω load within
the BLE frequency band.
 61

Zpar_in
VDD_buffer

M3 M2
Zpar_in
Rbw Lbw Cc
Ibias_buffer Pout

M5 M4 Rbias M1 Cpad Cpin

Rbw Lbw

Zbw Zbw
Zpar_out
Cpin Cpad Lbw
Zbw
Cc_int Rbw
Zpar_in
Vout_lna

Figure 14: The common-source Buffer with current-source load circuit in 180nm CMOS
technology.

Source: Author

The resulting dimensions for the Buffer circuit are shown in Table 11.

The value of the coupling capacitor between LNA and buffer, Cci nt , is the same as in
table 10. The value of the coupling capacitor, Cc , between Buffer and output pin, Pout , is
the same as in Table 7.

The supply voltage for the buffer, VDD buf f er is the same as described in Table 7.

Table 11: Device dimensions for the Buffer circuit.

Parameter Value
M1 120 µm/ 0.4 µm
M2 136 µm/ 0.4 µm
M3 2 µm/ 0.4 µm
M4 , M5 1.9 µm/ 0.4 µm
Rbias 16 kΩ

3.1.1 Schematic simulations

After circuit sizing, following the described design procedures, the schematic simula-
tions were used to adjust the results. Figure 15 shows the results for scattering parameters
(S-Parameters) simulation of the LNA.

The S21 parameter represents the power gain of the circuit, and shows that it meets
the specifications for gain magnitude and frequency tuning. S11 parameter shows the
 62

input insertion loss, and shows a value below -15 dB for the frequencies of interest. The
S22 and S12 parameters measure the output reflection and reverse gain, respectively, and
show a satisfactory behavior.

16
11
6
1
4
Magnitude (dB)
9
14 S11
19 S12
24 S21
29 S22
34
39
44
49
54
59
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
Frequency (GHz)

Figure 15: S-Parameter results for the schematic simulations of LNA.

Source: Author

Following the simulations, Figure 16 shows the results for the noise figure simulation of
the LNA. The result shows a satisfactory noise figure result, below 4 dB for the frequency
range of interest.

Noise Figure
14

12
Magnitude (dB)

10

1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50

Frequency (GHz)

Figure 16: Noise Figure results for the schematic simulation of the LNA.

Source: Author
 63

The linearity measures are performed using a two-tone test simulation [26]. Figure
17 shows the results for the 1-dB compression point simulation of the LNA. The 1-dB
compression point result is satisfactory comparing to the expected results.

8
3 Linear -1dB
Output Power
−2
Output Power (dBm)
−7
−12
−17
−22
−27
P1dB = − 32 dBm
−32
−37
−42
−47
−60 −55 −50 −45 −40 −35 −30 −25 −20 −15 −10
Input Power (dBm)

Figure 17: 1-dB compression point result for the schematic simulation of the LNA.

Source: Author

Figure 18 shows the results for two-tone test simulation of the LNA showing third-
order intercept point (IP3 ) results. The IIP3 result is satisfactory comparing to the
expected results.

20
0
IIP3 = − 16.5 dBm
Output Power (dBm)

−20
−40
−60
−80
Linear 1st order
−100 Linear 3rd order
−120 1st Order
3rd Order
−140
−60 −55 −50 −45 −40 −35 −30 −25 −20 −15 −10
Input Power (dBm)

Figure 18: IIP3 result for the schematic simulation of LNA.

Source: Author
 64

Table 12 shows the performance specifications achieved after schematic simulations.

IDC stands for the DC current from VDD terminal to ground, and PDC the power achieved
multiplying it by the supply VDD .

Re{Zin } and Im{Zin } represent the real and imaginary components of the input
impedance Zin , respectively.

Table 12: Performance obtained after schematic simulations.

Parameter Value
Power Gain (S21) (dB) 15.8
Input Return Loss (S11) (dB) -18
Noise Figure (dB) 3
1-dB Compression Point (dBm) -32
IIP3 (dBm) -32
IDC (mA) 0.44
PDC (mW) 0.22
Re{Zin } (Ω) 58.4
Im{Zin } (Ω) -6.11

After assuring that the results obtained satisfy the required specifications, the layout
of the circuits is performed.

3.1.2 Layout

Figure 19 shows the layout for the LNA and Buffer circuit, describing the specific
blocks and the total size.

The layout comprises the integrated components shown during the design steps, where
only one integrated inductor is used. The resulting layout shows a dominance of the
inductor in the area occupation. The choice of using external matching for the gate
inductor, which is usually larger than the others, copes with saving area.

A pitch of 200 µm was added at the input and output pads, where each of them
presents two ground pins by their sides, in order to reduce noise when interfacing with
RF Ground-Signal-Ground (GSG) microprobes.

To save area, no ESD protections are included, demanding careful handling during
experimental tests.
 65

Guardring protections are added in the RF transistors to reduce noise. Also, plenty
of substrate connections are used, with the same objective.

Metal crossing is avoided to reduce cross coupling noise among metal levels. Each
metal level is used either for vertical or horizontal connections, helping to reduce crossing
area.

Figure 19: Layout of the LNA and buffer circuits in 180nm CMOS technology.

Source: Author

After iterations between schematic and post-layout simulations, some component val-
ues were adjusted accounting for the parasitic variations after the layout.

Table 13 shows the final values for the LNA and buffer circuit, after the necessary
adjustments from the initial values on table 7.
 66

Table 13: Final sizing values for LNA and buffer circuit after adjustments.
Parameter Value
Lmatch 8.6 nH
Cmatch 1.55 pF
Rbias 1 kΩ
Rbias,buf f er 5 kΩ

3.1.3 Post layout simulations

After layout and parasitic extraction, the same tests were applied and the results
adjusted and compared.

Figure 20 shows the results for scattering parameters (S-Parameters) simulation of

the LNA and Buffer circuits.

10
5
0
−5
Magnitude (dB)

−10
−15
−20
−25
−30
−35 S11
−40 S12
−45 S21
−50 S22
2.0 2.2 2.4 2.6 2.8 3.0
Frequency (GHz)

Figure 20: S-Parameter results for the post-layout simulation of the LNA and Buffer
circuit in 180nm CMOS technology.

Source: Author

Figure 21 shows the results for noise figure simulation of the LNA and Buffer circuit.
 67

Noise Figure
15
14

Magnitude (dB)
13
12
11
10
9
2.0 2.2 2.4 2.6 2.8 3.0
Frequency (GHz)

Figure 21: Noise Figure results for the post-layout simulation of the LNA and Buffer
circuit in 180nm CMOS technology.

Source: Author

Figure 22 shows the results for 1-dB compression point simulations of the LNA and
Buffer circuit.

−2
−7 Linear -1dB
Output Power
−12
Output Power (dBm)

−17
−22
−27
−32
−37 P1dB = − 31.76 dBm
−42
−47
−52
−57
−60 −55 −50 −45 −40 −35 −30 −25 −20 −15 −10
Input Power (dBm)

Figure 22: 1-dB compression point simulation for the post-layout of LNA and Buffer.

Source: Author

Figure 23 shows the results for two-tone simulations of the LNA and Buffer circuit
showing third-order intercept point (IP3) results.
 68

0 IIP3 = 17.63 dBm

20

Output Power (dBm)

40
60
80
100 Linear 1st order
Linear 3rd order
120 1st Order
140 3rd Order
−60 −55 −50 −45 −40 −35 −30 −25 −20 −15 −10

Input Power (dBm)

Figure 23: IIP3 results for the post-layout simulation of the LNA and Buffer circuit in
180nm CMOS technology.

Source: Author

Table 14 shows the performance specifications achieved after post-layout simulations.

IDC stands for the DC current from VDD terminal to ground, and PDC the power con-
sumption achieved multiplying it by the supply VDD .

Re{Zin } and Im{Zin } represent the real and imaginary components of the input
impedance Zin , respectively.

Table 14: Performance obtained after post-layout simulations of the LNA and Buffer
circuit.
Parameter Value
Power Gain (S21) (dB) 8.5
Input Return Loss (S11) (dB) -25
Noise Figure (dB) 8.8
1-dB Compression Point (dBm) -31.76
IIP3 (dBm) -17.63
IDC (mA) 0.77
PDC (mW) 0.38
Re{Zin } (Ω) 51.5
Im{Zin } (Ω) -0.58

After comparing the obtained results with the required specifications, the LNA and
 69

Buffer circuit was fabricated using a 180nm CMOS technology.

3.1.4 Experimental results

Figure 24 shows the die micrograph after fabrication of the LNA and Buffer circuits
in TSMC 180nm CMOS technology.

Figure 24: Die micrograph for the LNA and Buffer circuit.

Source: Author

The design of the PCB for testing the fabricated circuit followed the strategy describes
at the beginning of this chapter. Figure 25 shows the schematic capture of the PCB design
realized using Autodesk EAGLE software.

Figure 25: Schematic capture of the designed test PCB for the LNA and Buffer circuit
on Autodesk EAGLE software.

Source: Author
 70

Figure 26 shows the test PCB after fabrication. It is possible to observe the placement
of the die, using chip-on-board technology. It is also shown the location of the passive
network to perform the input matching.

Figure 26: Fabricated test PCB for the LNA and Buffer circuit.

Source: Author

The data was obtained using the Vector Network Analyzer (VNA) model HP8510B
[21], which was calibrated for the ISM band, from 1.5 GHz to 3.5 GHz.

Figure 27 shows the Smith Chart plot for the input reflection ratio (S11) obtained with
the data extracted from the measurement with the VNA. It shows that before applying
the matching circuit, the impedance was distant of the desired 50 ohm for 2.4 GHz.
 71

Figure 27: Smith Chart plot for S11 of experimental LNA and Buffer circuit.

Source: Author

Figure 28 shows the S-Parameters measurement results with data extracted from the
measurements in the VNA. It is possible to see that the input reflection (S11) is fairly
high for all the band, showing no match, therefore no selectivity. Also, the power gain
(S21) shows no tuning in the output, probably due to lack of input matching.
 72

6
1
4
9
14

Magnitude (dB)
19
24
29
34
39
S11
44
49 S12
54 S21
59 S22
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
Frequency (GHz)

Figure 28: S-Parameter analysis of experimental LNA and Buffer circuit.

Source: Author

The extracted data was imported in the Keysight ADS software, as a way to design
a proper input matching circuit. Figure 29 describe the matching procedure using LC
elements. The procedure was performed using the Smith Chart Tool of Keysight ADS
software. Starting from the impedance seen on the previous figure for the measured
unmatched S11, the components were sized such that the final network could drive the
input impedance seen at its input to 50 Ω.
 73

Figure 29: Impedance transformation performed after applying the designed matching
circuit in simulation performed by the Smith Chart Tool in the Keysight ADS software
using the data extracted from the measurements of the unmatched LNA and Buffer circuit.

Source: Author

Figure 30 describes the obtained LC network, in which the component values are
described in the Table 15.

L1

C1 C2

Figure 30: Designed ideal input matching circuit for the LNA and Buffer circuit.

Source: Author
 74

Table 15: Sizing values for ideal input matching circuit for the measured LNA and Buffer
circuit.
Parameter Value
L1 2.59 nH
C1 7.79 pF
C2 1.82 pF

Figure 31 shows the Smith Chart simulation for the input reflection ratio, S11, us-
ing the designed ideal matching network and the experimental data extracted from the
unmatched LNA and Buffer circuit.

Figure 31: Smith chart plot for the simulation of experimental circuit data with designed
input matching.

Source: Author

Figure 32 shows the S-Parameters results using the same configuration of ideal input
matching and unmatched data from measurements of the LNA and Buffer.
 75

8
3
2
7
12

Magnitude (dB)
17
22 S11
27 S12
32 S21
37 S22
42
47
52
57
62
67
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
Frequency (GHz)

Figure 32: S-parameter simulation of experimental circuit data with designed input
matching.

Source: Author

After the simulations using Keysight ADS, the values were rounded to a near comercial
component value. With the adjusted component value, the input matching network was
realized in the PCB. After adjustments in the PCB, the matching network elements were
resized to better approximate the 50 Ω input impedance. The VNA was used to verify
the input impedance. The final result of the measured LNA and Buffer circuit using the
real input matching is shown in figure 33.
 76

Figure 33: Smith Chart plot showing the measured S11 of the LNA and Buffer circuit
with the real input matching circuit realized in the PCB.

Source: Author

Figure 34 shows the real input matching circuit, as realized in the PCB, after adjust-
ments on the initial ideal network designed in the Keysight ADS.

L1

C1 L2

Figure 34: Input matching circuit after adjustments on PCB.

Source: Author

Table 16 shows the values of the comercial components used to implement the real
input matching network in the PCB.
 77

Table 16: Sizing values for implemented input matching circuit of 180nm LNA.
Parameter Value
L1 3.3 nH
L2 1.8 nH
C1 1 pF

Figure 35 shows the result for the S-Parameter measurement performed by the VNA
in the LNA and Buffer circuit using the realized input matching circuit.

10
5
0
−5
−10
Magnitude (dB)

−15
−20
−25
−30
−35
−40 S11
−45 S12
−50 S21
−55
−60 S22
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
Frequency (GHz)

Figure 35: S-parameter simulation for the measured circuit with measured input match-
ing.

Source: Author

Table 17 shows the performance specifications achieved in experimental circuit.

Re{Zin } and Im{Zin } represent the real and imaginary components of the input
impedance Zin , respectively.
 78

Table 17: Performance obtained in experimental circuit.

Parameter Value
Power Gain (S21) (dB) 5.5
Input Return Loss (S11) (dB) -33
IDC (mA) 0.45
PDC (mW) 0.23
Re{Zin } 48.05
Im{Zin } 1.1

3.2 Second Cascode common-source LNA in 180nm

technology

After the first design and fabrication, the design was restarted as a way to review the
previous circuit. This time the circuit gain was improved seeking to overcome the flaws
on the previously measured circuit.

In the second design of LNA in 180nm design, a source-follower buffer was used for
matching with 50Ω load. Although the gain will not be 0dB, a more stable biasing and
output common-mode voltage are defined.

The gate inductor LG is now integrated. It permits evaluating the variation from
design to experimental results, and evaluate if it is worth to have it integrated instead of
an off chip matching circuit.

This design also follow the specifications set on the start of the chapter, trying to
improve the performance compared to the first design.

Figure 36 show the LNA and Buffer circuit in this second implementation.

The parasitic passive devices considered come from the bondwire, internal pad and
PCB or package pins. Rbw and Lbw stand for the bondwire resistance and inductance,
respectively. Cpin and Cpad represent the capacitance from off-chip connection and in-
tegrated pad, respectively. Cpin may receive capacitive contributions from package pins,
when the die has a package, or solely PCB connection when chip-on-board connection
is used. The parasitic devices from bondwires, pads and pins are present in connections
between the integrated circuits and off-chip components. Those parasitic components are
represented in the circuit by the impedance values Zpar in and Zpar out .
 79

The resistors Rbias is placed to isolate the terminal Vbias of the RF signal. The terminal
Vbias is responsible for setting the common-mode voltage at the gate of the input transistor
M1 of the LNA.

Cc and Cc int capacitors perform the ac coupling between input source and LNA input
pin, and between LNA output and Buffer input, respectively. The input matching net-
work, responsible for controlling the LNA input impedance Zin , is realized using inductor
Lmatch and capacitor Cmatch .

Apart from the devices represented inside the rectangle with label ”Integrated” and
Cpad , all elements in the figure represent off-chip devices or parasitic entities.

Rbw Lbw

Rbw Lbw
Cpin Cpad

Zpar_in Cpad Cpin

Vbody
Zpar_in Vdd_buffer
Vdd
Vbias Rbias
Integrated

Rs Cc Cc_int Cc

Zpar_in LNA Buffer Zpar_out

Vsource RL

Lbw Lbw

Rbw Rbw
Zbw Zbw

Figure 36: Circuit showing the implementation of the LNA and the Buffer circuit in
180nm technology.

Source: Author
 80

Table 18: Device dimensions for the second LNA and Buffer design.
Parameter Value
Rs 50 Ω
Rbias 10 kΩ
Rbw 1Ω
Lbw 1 nH
Cpin 100 fF
Cpad 100 fF
Cc 100 nF
RL 50 Ω
VDD 0.5 V
VDD buf f er 1.8 V

Figure 37 shows the LNA circuit, implementing the cascode common-source with
inductive source degeneration topology, along with parasitic and external components.

Cc and Cc int capacitors perform the ac coupling between input source and LNA input
pin, and between LNA output and Buffer input, respectively. The input matching net-
work, responsible for controlling the LNA input impedance Zin is realized using inductor
Lmatch and capacitor Cmatch .

As with the LNA and the Buffer circuit, input match, Zpar in and Zbw represent off-
chip devices or parasitic entities.

CL represents the load capacitance, in this case coming from the input of the Buffer
stage.

LD act as a tuned load for the amplifier, and is designed to give the required gain,
based on its embedded parallel resistance.

CD capacitor is part the output impedance of the circuit with LD and CL . It adjusts
the value to give resonance in the center frequency of the band of interest.
 81

Zpar_in
VDD

LD CD

Cc_int
Vout
Rbias
Vbias M2
Zpar_in
CL
Cc Rbw Lbw LG Vbody
M1
Pin

Cpin Cpad
Lbw
Zbw
Zpar_in
Rbw

Figure 37: The second implementation of the cascode common-source LNA with inductice
source degeneration circuit in 180nm CMOS technology, along with parasitic and other
external devices.

Source: Author

Different from the first design, now for saving pins on the chip, the capacitor on the
drain is chosen to be fixed. Otherwise, a pin is added to change the value of Vbody biasing
on transistor bulk terminal. Because of the suspicion that the voltage at the bulk caused
undesired effects on the first design, it is added the possibility of changing it and observe
the consequences.

The value of coupling capacitor between LNA and buffer, Cc int , also changed as it
was observed in the simulations that a smaller capacitor could be used without altering
the coupling effects on the frequency band of interest.

The transistors are made bigger to increase gm and thus reduce noise and increase
the gain. Also the load inductor LD is made larger to help increasing the gain.
 82

Table 19: Sizing values for second LNA 180nm.

Parameter Value
M1 , M2 144 µm/ 0.18 µm
LD 3.9 nH
CD 0.8 pF
Rbias 10 kΩ
Cc int 1.77 pF
Vbody 0.5 V

Figure 38 shows the Buffer circuit, implementing the NMOS source follower topology,
along with parasitic and external components. This topology is one of the most simple
buffer implementations, giving predictable DC values and attenuation around 3 dB [44].

The parasitic devices in Zpar in are the same described for the LNA and Buffer circuit.

The M3 drain voltage acts as common-mode reference to transistor M1 . Its drain

W
voltage is defined by the relation of its aspect ratio, L
, R1 and VDD buf f er at the desired
DC current. And the current at M3 drain serve as reference for the output current biasing
of the buffer, passing by M1 and M2 drain.

Cc and Cc int capacitors perform the ac coupling between Buffer output and output
pin, and between LNA output and Buffer input, respectively.

As with the LNA and Buffer circuit, input match, Zpar in and Zbw represent off-chip
devices or parasitic entities.

Transistor M1 and M2 are designed to give a gain near 0 dB with a 50 Ω load within
the BLE frequency band.
 83

Rbw Lbw

Cpin Cpad Zpar_in

Vdd_buffer

Zpar_in Cc_int
M1
Vout_lna

R1 R2 Rbw Lbw Cc

Lbw M3 M2
Cpad Cpin RL

Rbw
Zbw Zbw Zpar_out
Zbw

Figure 38: Circuit showing the Buffer circuit in 180nm technology, along with parasitic
and other external devices.

Source: Author

The buffer topology was changed to a source follower to avoid problems with output
common-mode voltage setting, reduce area and power consumed by the buffer. On the
other hand, it is expected that the gain be reduced by 3 dB [44].

Table 20: Sizing values for second buffer 180nm.

Parameter Value
M1 64 µm/ 0.18 µm
M2 6 µm/ 0.18 µm
M3 1.5 µm/ 0.5 µm
R1 1 kΩ
R2 10.8 kΩ

3.2.1 Schematic simulations

After circuit sizing, following the described design procedures, the schematic simula-
tions were used to adjust the results. Figure 39 shows the results for scattering parameters
(S-Parameters) simulation of the LNA.

The S21 parameter shows that the gain values are higher than the achieved in the
first design. S11 parameter continues to show values below -15 dB for the frequencies of
interest, as in the first design. The S22 and S12 parameters show a satisfactory behavior.
 84

19
14
9
4
−1

Magnitude (dB)
−6
−11
−16
−21
−26
−31
−36
−41
−46 S11 S21
−51
−56 S12 S22
−61
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
Frequency (GH )

Figure 39: S-Parameter result for the schematic simulation of the second LNA circuit.

Source: Author

Following the simulations, Figure 40 shows the results for the noise figure simulation of
the LNA. The result shows a satisfactory noise figure result, below 4 dB for the frequency
range of interest.

10 Noise Figure

9
Magnitude (dB)

8
7
6
5
4
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
Frequency (GHz)

Figure 40: Noise Figure result for the schematic simulation of the second LNA circuit.

Source: Author

The linearity measures are performed using a two-tone test simulation [26]. The simu-
lation results in the 1-dB Compression Point and IP3 curves. Figure 41 shows the results
for the 1-dB compression point simulation of the LNA circuit. The 1-dB compression
 85

point result is satisfactory comparing to the expected results.

8
3 Linear -1dB
Output Power
2

Output Power (dBm)

7
12
17
22
27
32 P1dB = 33.85 dBm
37
42
47
−60 −55 −50 −45 −40 −35 −30 −25 −20 −15 −10

Input Power (dBm)

Figure 41: 1-dB compression point result for the schematic of LNA circuit.

Source: Author

Figure 18 shows the results for two-tone test simulation of the LNA showing third-
order intercept point (IP3 ) results. The IIP3 result is satisfactory comparing to the
expected results.

20
0 IIP3 = − 20.23 dBm
Output Power (dBm)

−20
−40
−60
−80 Linear 1st order
−100 Linear 3rd order
1st Order
−120 3rd Order
−60 −55 −50 −45 −40 −35 −30 −25 −20 −15 −10
Input Power (dBm)

Figure 42: IIP3 result for the schematic simulation of the LNA circuit.

Source: Author

Table 21 shows the performance specifications achieved after schematic simulations.

 86

Table 21: Performance obtained after schematic simulations.

Parameter Value
Power Gain (S21) (dB) 18.6
Input Return Loss (S11) (dB) -16
Noise Figure (dB) 3.2
1-dB Compression Point (dBm) -33.85
IIP3 (dBm) -20.23
IDC (mA) 0.73
PDC (mW) 0.37
Re{Zin } (Ω) 47.6
Im{Zin } (Ω) -21

After assuring that the results obtained match with the required specifications, the
layout of the circuits is performed.

3.2.2 Layout

Figure 43 shows the layout for the LNA and the Buffer circuit, describing the specific
blocks and the total size.

The layout comprises the integrated components shown during the design steps, where
the drain (LD ) and gate (LG ) inductors are integrated. The resulting layout shows a
dominance of the inductors in the area occupation.

To save area, no ESD protections are included, demanding careful handling during
experimental tests.

Guardring protections are added in the RF transistors to reduce noise. Also, plenty
of substrate connections are used, with the same objective.

Metal crossing is avoided to reduce cross coupling noise among metal levels. Each
metal level is used either for vertical or horizontal connections, helping to reduce crossing
area.

The layout was improved in this second implementation to increase the width of the
ground and supply routing metal, reducing the parasitic resistance in the interconnections.
 87

Figure 43: Layout for the second LNA and the Buffer circuit in 180nm CMOS technology.

Source: Author

3.2.3 Post layout simulations

After layout and parasitic extraction, the same tests were applied and the results
adjusted and compared.

Figure 44 shows the results for scattering parameters (S-Parameters) simulation of

the second LNA and Buffer circuit.

It is possible to observe that the post-layout of the second implementation is better

comparing to the first one, and has a better proximity to the schematic simulations.
 88

16
11
6
1
4

Magnitude (dB)
9
14
19
24
29 S11
34 S12
39 S21
44 S22
49
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
Frequency (GHz)

Figure 44: S-Parameter results for post-layout simulation of the second LNA and buffer
circuit.

Source: Author

Figure 45 shows the results for noise figure simulation of the LNA and Buffer circuit.
The degradation comparing to the schematic simulation was reduced, comparing to the
first design.

12 Noise Figure
11
10
Magnitude (dB)

9
8
7
6
5
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
Frequency (GHz)

Figure 45: Noise Figure results for post-layout simulation of the second LNA and Buffer
circuit.

Source: Author

Figure 46 shows the results for 1-dB compression point simulations of the LNA and
 89

Buffer circuit.

3
−2 Linear -1dB
Output Power
−7

Output Power (dBm)

−12
−17
−22
−27
−32 P1dB = − 32.24 dBm
−37
−42
−47
−52
−60 −55 −50 −45 −40 −35 −30 −25 −20 −15 −10
Input Power (dBm)

Figure 46: 1-dB compression point result for post-layout simulation of the second LNA
and Buffer circuit.

Source: Author

Figure 47 shows the results for two-tone simulations of the LNA and Buffer circuit
showing third-order intercept point (IP3) results.

20
0 IIP3 = 17.8 dBm
Output Power (dBm)

20
40
60
80
Linear 1st order
100 Linear 3rd order
120 1st Order
3rd Order
140
−60 −55 −50 −45 −40 −35 −30 −25 −20 −15 −10

Input Power (dBm)

Figure 47: IIP3 result for post-layout simulation of the second LNA and buffer circuit.

Source: Author

Table 22 shows the performance specifications achieved after post-layout simulations.

 90

Table 22: Summary of results obtained in post-layout simulations.

Parameter Value
Power Gain (S21) (dB) 14
Input Return Loss (S11) (dB) -23
Noise Figure (dB) 4
1-dB Compression Point (dBm) -32.24
IIP3 (dBm) -17.8
IDC (mA) 0.69
PDC (mW) 0.34
Re{Zin } (Ω) 40.3
Im{Zin } (Ω) 2.27

After comparing the obtained results with the required specifications, the LNA and
the Buffer circuit was fabricated using a 180nm CMOS technology.

3.2.4 Experimental results

Figure 48 shows the die micrograph after fabrication of the LNA and the Buffer circuit
in TSMC 180nm technology.

Figure 48: Die micrograph for the second LNA and Buffer circuit.

Source: Author

Figure 49 shows the resulting PCB for the tests with this second design. This time,
the die is placed in a standard QFP44 package.
 91

Figure 49: Fabricated test PCB for the second LNA and Buffer circuit.

Source: Author

The experimental data was obtained using the Vector Network Analyzer (VNA) model
HP8510B [21], which was calibrated for the ISM band, from 1.5 GHz to 3.5 GHz. S-
parameter data were obtained using VNA equipment and passed to Keysight ADS through
S2P file for analysis and visualization.

Figure 50 shows the Smith Chart plot for the input reflection ratio (S11) obtained
with the data extracted from the measurement with the VNA. It shows that the matching
results are better than in the first design, due to the integrated LG used in this second
design. However, the input impedance is still distant from the optimal 50 Ω value.
 92

Figure 50: Smith Chart plot for S11 of experimental measurement of the second LNA
and Buffer circuit.

Source: Author

Figure 51 shows the S-Parameter results with data extracted from the measurements
in the VNA. The input reflection results shows a matching at the frequency os inter-
[Link], it is not very selective, which may be due imperfections on the transmission
line calculations performed during the PCB design.

The power gain (S21) shows a tuning behavior and a higher gain than the experimental
data for the first design. However the tuning is displaced from the frequency of interest.
Unfortunately, in this design the LC tank capacitor CD is not variable, not allowing the
adjustment of the resonating frequency of the S21.
 93

13
8
3
−2

Magnitude (dB)
−7
−12
−17
−22
−27
−32 S11
−37 S12
S21
−42
S22
−47
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
Frequency (GHz)

Figure 51: S-parameter results for experimental measurement of the second LNA and
Buffer circuit.

Source: Author

The VNA data was imported in the Keysight ADS software to analyze how the re-
sponse would get enhanced applying an input matching circuit. A procedure similar to
the performed with the first design was realized. Figure 52 shows the procedure of using
a LC network to drive the input impedance towards the optimal 50 Ω value.
 94

Figure 52: Impedance transformation performed by the Smith Chart Tool in the Keysight
ADS software using the data extracted from the measurements of the second LNA and
Buffer circuit.

Source: Author

Figure 53 shows the resulting ideal input matching circuit, and Table 23 the device
values.

L1

C1

Figure 53: Designed ideal input matching circuit for the second LNA and Buffer circuit.

Source: Author
 95

Table 23: Sizing values for ideal input matching circuit for the measured second LNA and
Buffer circuit.
Parameter Value
L1 3.67 nH
C1 0.85 pF

Figure 54 shows the Smith Chart simulation for the input reflection ratio, S11, using
the designed ideal matching network and the experimental data extracted from the second
LNA and Buffer circuit.

Figure 54: Smith chart plot for the simulation of experimental circuit data with designed
input matching.

Source: Author

Figure 55 shows de S-Parameters results using the same configuration of ideal input
matching and data from measurements of the second LNA and Buffer.
 96

12
7
2
−3
−8

Magnitude (dB)
−13
−18
−23
−28
−33
−38 S11
−43 S12
−48 S21
−53 S22
−58
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
Frequency (GHz)

Figure 55: S-parameter simulation of experimental circuit data with designed input
matching.

Source: Author

The results show that the input matching circuit would help to adjust the input
matching response, reducing the effect of the PCB imperfections. Unfortunately, the
PCB for the second design does not include the pad connections for the implementation
of the input matching circuit, making it difficult to implement the real matching circuit.

Table 24 shows the performance specifications achieved in experimental circuit.

Despite the higher power consumption, it has a better band tuning and higher gain
than the first tapeout. As the capacitor at the drain terminal could not be controlled, the
resonating frequency could not be adjusted and showed a center frequency higher than
the desired of 2.44 GHz.

Table 24: Summary of results obtained in experimental circuit.

Parameter Value
Power Gain (S21) (dB) 11
Input Return Loss (S11) (dB) -58
IDC (mA) 0.7
PDC (mW) 0.35
 97

3.3 RF Front-end design in 130nm BiCMOS technol-

ogy

The third implementation extends the previous fabricated designs by including the
complete RF Front-End structure. This design uses a 130nm BiCMOS technology from
GlobalFoundries. The first two LNA designs contributed with information regarding
the LNA behavior at Low Voltage operation, and also showed the possible parameter
variations in the experimental results.

helped to learn the behavior of the LNA, and the divergence of the experimental
results compared to the simulations.

This design includes the cascode common-source LNA with inductive degeneration, a
single-balanced passive sampling mixer, a simple common-source IF amplifier with resis-
tive load, and a common-source buffer with resistive load.

The common-source buffer has been chosen to try to avoid the attenuation experienced
when using a source follower. Different from the first one used, now a resistor load is used
to help defining the output common-mode voltage.

In this technology, the lower VT H values allowed the implementation without the need
of VT H reducing techniques like the FBB implemented in the previous designs.

Table 25 shows the simulated fT response as a function of the channel length for a
nMOS transistor, the same used for the input stage of the amplifiers in this design. The
results show that the fT holds satisfactory values in the presented channel length range,
therefore making unnecessary the use of FBB.

Table 26 shows the simulated threshold voltage response as a function of the channel
length for a nMOS transistor. Again, the results show VT H values matching the design
needs.

Table 25: Transfer frequency response as a function of the nMOS transistor channel
length.
L(nm) 120 150 200 250 300 400
fT (GHz) 125 90 50 30 20 11

Table 26: Threshold voltage response as a function of the nMOS transistor channel length.
L(nm) 120 150 200 250 300 400
VT H (V ) 0.4 0.37 0.33 0.31 0.3 0.29
 98

Figure 56 shows the RF Front-End circuit along with the IF amplifier and Buffer.

The parasitic passive devices considered come from the bondwire, internal pad and
PCB or package pins. Rbw and Lbw stand for the bondwire resistance and inductance,
respectively. Cpin and Cpad represent the capacitance from off-chip connection and in-
tegrated pad, respectively. Cpin may receive capacitive contributions from package pins,
when the die has a package, or solely PCB connection when chip-on-board connection
is used. The parasitic devices from bondwires, pads and pins are present in connections
between the integrated circuits and off-chip components. Those parasitic components are
represented in the circuit by the impedance values Zpar in and Zpar out . The resistors Rbias
adjust the reference current Ibias biasing the LNA and Buffer circuits. Cc and Cc int ca-
pacitors perform the ac coupling between input source and LNA input pin, and between
LNA output and Buffer input, respectively. The input matching network, responsible for
controlling the LNA input impedance Zin is realized using inductor Lmatch and capacitor
Cmatch .

Apart from the devices represented inside the rectangle with label ”Integrated” and
Cpad , all elements in the figure represent off-chip devices or parasitic entities.

Rbw Lbw Rbw Lbw

Cpin Cpad Cpad Cpin

Zpar_in
LO+ Zpar_out
Zpar_in Vcap
LO- Vdd_buffer
Vdd Vdd
Zpar_in
Vbias Zpar_in Zpar_in
Integrated

Rs Cc Lmatch Cc_int Cc

Zpar_in LNA IF_Amp Buffer Zpar_out

Mixer
Vsource Cmatch RL

Lbw Lbw Lbw

Input Match
Rbw Rbw Rbw
Zbw Zbw Zbw

Figure 56: The implemented RF Front-End, common-source IF amplifier with resistive

load and common-source Buffer with resistive load circuits in 130nm BiCMOS technology.

Source: Author

Table 27 describe the values of the devices included in this design.

 99

Table 27: Device dimensions for the Front-End, IF Amplifier and Buffer circuit in 130nm
CMOS technology.
Parameter Value
Rs 50 Ω
Lmatch 6.55 nH
Cmatch 2.5 pF
Rbw 1Ω
Lbw 1 nH
Cpin 100 fF
Cpad 100 fF
Cc 100 nF
Cc int 10 pF
RL 50 Ω
VDD 0.5 V
VDD buf f er 1.2 V

Figure 57 shows the LNA circuit, implementing the cascode common-source with
inductive source degeneration topology, along with parasitic and external components.

As with the first design in the 180nm CMOS technology, this implementation includes
a variable capacitor device for the capacitor CD in the LC tank, making possible to adjust
its resonating frequency. The source inductor is not included in the integrated design,
instead being represented by the bondwire inductance in the source, Lbw . The gate
inductor have also been removed from the integrated circuit and is rather implemented
off-chip by the matching network inductor Lmatch .

The elements in the input match circuit and the parasitic devices in Zpar in are the
same described for the RF Front-End, IF Amplifier and Buffer circuit.

Transistor M3 drain voltage is defined by the sizing of M3 and the incoming Ibias , and
set the input common-mode voltage of M1 . The resistor Rbias combined with M3 gate
capacitance perform a low-pass filtering, avoiding signal leakage from the input node.

Cc and Cc int capacitors perform the ac coupling between input source and LNA input
pin, and between LNA output and Buffer input, respectively. The input matching net-
work, responsible for controlling the LNA input impedance Zin is realized using inductor
Lmatch and capacitor Cmatch .
 100

As with the RF Front-End, IF Amplifier and Buffer circuit, the input match, Zpar in
and Zbw represent off-chip devices or parasitic entities.

CL represents the load capacitance, in this case coming from the input of the Buffer
stage.

LD act as a tuned load for the amplifier, and is designed to give the required gain,
based on its embedded parallel resistance.

CD capacitor is part the output matching of the circuit with LD and CL . It adjusts
the value to give resonance in the center frequency of the band of interest.

Zpar_in
Vbias Zpar_in
VDD
R1 Zpar_in
Vcap
M3 R2 LD CD

Cc_int
Zbw Vout
M2

CL
Cc Lmatch Rbw Lbw M1
Pin

Cmatch Cpin Cpad

Lbw
Zbw
Zpar_in
Input Match Rbw

Figure 57: The implemented circuit of the cascode common-source LNA with inductive
source degeneration block in 130nm BiCMOS technology.

Source: Author

Table 28 describe the values of the devices included in this design.

 101

Table 28: Device dimensions for the cascode common-source LNA with inductive source
degeneration in 130nm BiCMOS technology.
Parameter Value
M1 , M2 100 µm/ 0.32 µm
LD 2 nH
CD 0.14 - 0.69 pF
R1 10 kΩ
R2 10 kΩ
Cc int 10 pF

Figure 58 shows only the single-balanced passive sampling Mixer circuit along with
parasitic and external components.

The parasitic devices in Zpar in are the same described for the Front-End, IF Amplifier
and Buffer circuit.

The M3 drain voltage acts as the input common-mode voltage VCM of the Mixer. Its
W
drain voltage is defined by the relation of its aspect ratio, L
, R1 and VDD buf f er at the
desired DC current. The voltage VCM will also represent the input common-mode voltage
of the IF Amplifier stage, at the Vout+ and Vout− pins seen in the Figure 58

The design procedure for the Mixer, accounting for the VCM definition, bandwidth
and noise considerations, follows the strategy proposed in the methodology chapter of this
work.

Cc and Cc int capacitors perform the AC coupling between Buffer output and output
pin, and between LNA output and the Buffer input, respectively.

As with the Front-End, IF Amplifier and Buffer circuit, the input match, Zpar in and
Zbw represent off-chip devices or parasitic entities.

Transistor M1 and M2 are designed to give a gain near to 0 dB with a 50 Ω load

within the BLE frequency band.
 102

Rbw Lbw
Lbw
Zbw
Cpin Cpad
Rbw
Zpar_in
LO+
Zpar_in CL
Vout+
Cc_int M1
Vout_LNA M2
Vout-
R1
VDD CL
M3 R2 LO-
Zpar_in

Zbw

Figure 58: The implemented single-balanced passive sampling Mixer circuit in 130nm
BiCMOS technology.

Source: Author

The values for the device dimensions implemented in the Mixer design are shown in
Table 29.

Table 29: Device dimensions the single-balanced passive sampling Mixer in 130nm BiC-
MOS technolgy.
Parameter Value
M1 , M2 192 µm/ 0.32 µm
R1 11 kΩ
R2 11 kΩ
CL 300 fF

Figure 59 shows the common-source IF Amplifier with resistive load circuit. This sim-
ple amplifier topology is included to help increasing the circuit conversion gain, serving as
an IF baseband amplifier. It uses resistive load to ease the design, relaxing the procedure
for definition of the output common-mode voltage.

The parasitic devices in Zpar in are the same described for the RF Front-End, IF
Amplifier and Buffer circuit.

The RD resistors represent the load of the common-source IF Amplifier.

Cc and Cc int capacitors perform the ac coupling between Buffer output and output
 103

pin, and between LNA output and Buffer input, respectively.

As with the RF Front-End, IF Amplicier and Buffer circuit, input match, Zpar in and
Zbw represent off-chip devices or parasitic entities.

Transistor M1 and M2 are the input MOSFETs of the IF Amplifier, and are designed
to have a input common-mode voltage equal to the used in the Mixer circuit.

Rbw Lbw
Lbw
Zbw
Zpar_in Cpin Cpad
Rbw
VDD

Zpar_in
RD RD
Vout_IF
+ -
M1 M2 Vout_mixer+
Vout_mixer-

Zbw Zbw

Figure 59: The implemented common-source IF Amplifier with resistive load circuit in
130nm BiCMOS technology.

Source: Author

The resulting dimensions for the IF Amplifier circuit are shown in Table 30.

Table 30: Device dimensions for the common-source IF amplifier with resistive load in
130nm BiCMOS technology.
Parameter Value
M1 , M2 40 µm/ 1 µm
RD 2.4 kΩ

Figure 60 shows the common-source Buffer with resistive load circuit, along with
parasitic and external components.

The parasitic devices in Zpar in are the same described for the RF Front-End, IF
Amplifier and Buffer circuit.

Cc and Cc int capacitors perform the ac coupling between Buffer output and output
pin, and between LNA output and Buffer input, respectively.
 104

As with the LNA and Buffer circuit, input match, Zpar in and Zbw represent off-chip
devices or parasitic entities.

Transistor M1 and M2 are designed to have gain near 0 dB with a 50 Ω load within
the BLE frequency band. Resistors RD are designed to show an optimal matching with
external 50 Ω resistance, representing the input impedance of the test equipment.

Rbw Lbw
Lbw
Zbw
Zpar_in Cpin Cpad
Rbw
VDD

Zpar_in
RD RD CC
Zpar_out

M1 M2 Zpar_out
Vout_IF- Vout_IF+ CC
RL RL

Zbw Zbw

Rbw Lbw

Cpad Cpin

Zpar_out

Figure 60: The implemented common-source Buffer with resistive load circuit in 130nm
BiCMOS technology.

Source: Author

The resulting dimensions for the common-source Buffer with resistive load circuit are
shown in Table 31.

Table 31: Device dimensions for the common-source Buffer with resistive load in 130nm
BiCMOS technology.
Parameter Value
M1 , M2 960 µm/ 1 µm
RD 50 Ω
 105

3.3.1 Schematic simulations

After circuit sizing, following the described design procedures, the schematic simula-
tions were used to adjust the results. Figure 61 shows the results for scattering parameters
(S-Parameters) simulation of the common-source LNA with inductive source degenera-
tion.

The S21 parameter represents the power gain of the circuit, and shows that it meets
the specifications for gain magnitude and frequency tuning. S11 parameter shows the
input insertion loss, and shows a value below -15 dB for the frequencies of interest.

17
S11
12 S21
7
2
Magnitude (dB)

−3
−8
−13
−18
−23
−28
−33
−38
−43
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
Frequency (GHz)

Figure 61: S-Parameter results for the schematic simulation of the common-source LNA
with inductive source degeneration in 130nm BiCMOS technology.

Source: Author

Following the simulations, Figure 62 shows the results for the Noise Figure simula-
tion of the common-source LNA with inductive source degeneration. The result shows a
satisfactory noise figure result, below 4 dB for the frequency range of interest.
 106

16
Noise Figure
14

12

Magnitude (dB)
10

1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50

Frequency (GHz)

Figure 62: Noise Figure result for the schematic simulation of the common-source LNA
with inductive source degeneration in 130nm BiCMOS technology.

Source: Author

Table 32 shows the performance specifications achieved after schematic simulations.

IDC stands for the DC current from VDD terminal to ground, and PDC the power achieved
multiplying it by the supply VDD .

Table 32: Summary of performance obtained in the LNA after schematic simulations.
Parameter Value
Power Gain (S21) (dB) 17
Input Return Loss (S11) (dB) -43
Noise Figure (dB) 3
IDC (mA) 0.38
PDC (mW) 0.19

3.3.2 Post-Layout simulations of the LNA circuit

After assuring that the results obtained match with the required specifications, the
layout of the LNA circuit was performed, intending to realize the parasitic extractions,

After layout and parasitic extraction, the same tests were applied and the results
adjusted and compared.

Figure 63 shows the results for scattering parameters (S-Parameters) simulation of

 107

the LNA circuit.

15
S11
10
S21
5
0

Magnitude (dB)
−5
−10
−15
−20
−25
−30
−35
−40
−45
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
Frequency (GHz)

Figure 63: S-Parameter result for the post-layout simulation of the common-source LNA
with inductive source degeneration in 130nm BiCMOS technology.

Source: Author

Figure 64 shows the results for noise figure simulation of the LNA and Buffer circuit.

22.5
Noise Figure
20.0
17.5
Magnitude (dB)

15.0
12.5
10.0
7.5
5.0
2.5
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
Frequency (GHz)

Figure 64: Noise Figure result for the post-layout simulation of common-source LNA with
inductive source degeneration in 130nm BiCMOS technology.

Source: Author

Figure 65 shows the results for 1-dB compression point simulations of the LNA circuit.
 108

8
3 Linear -1dB
2 Output Power
7

Output Power (dBm)

12
17
22
27 P1dB = 31.3 dBm
32
37
42
47
52
57
−70−65−60−55−50−45−40−35−30−25−20−15−10

Input Power (dBm)

Figure 65: 1-dB compression point result for the post-layout simulation of the common-
source LNA with inductive source degeneration in 130nm BiCMOS technology.

Source: Author

Figure 66 shows the results for two-tone simulations of the LNA circuit showing third-
order intercept point (IP3) results.

25
0 IIP3 = − 21.15 dBm
Output Power (dBm)

−25
−50
−75
−100 Linear 1st order
Linear 3rd order
−125
1st Order
−150 3rd Order
−70−65−60−55−50−45−40−35−30−25−20−15−10
Input Power (dBm)

Figure 66: IIP3 result for the post-layout simulation of the common-source LNA with
inductive degeneration in 130nm BiCMOS technology.

Source: Author
 109

3.4 Front-end

Because of the impact of the interface impedance, rather than performing the Mixer
design alone, after the LNA design, the complete RF Front-End design was performed.

3.4.1 Layout

The fact of being a BiCMOS technology instead of a conventional CMOS make the
MOSFETs more susceptible to latch-up errors. Therefore, the layout implementation
is hardened with more carefully designed substrate connections, also including reverse
biased diodes to avoid latch-up.

Figure 67 shows the layout for the RF Front-End, IF Amplifier and Buffer circuit,
describing the specific blocks and the total size. Despite of having more implemented
blocks, the fact of using a technology with shorter minimum channel length resulted in a
layout with less area.
 110

Figure 67: Layout for the RF Front-End, IF Amplifier and Buffer circuit in 130nm BiC-
MOS technology.

Source: Author

3.4.2 Post layout simulations

The following results present the post-layout simulation performance of the RF Front-
End, IF Amplifier and Buffer circuit.

Figure 68 shows the conversion gain result for a RF signal with 2.44 GHz at the input,
and IF in the range of zero to 5 MHz at the output of the Buffer.

The result shows that the circuit presents a satisfactory conversion gain for the re-
quired IF of 2 MHz, even if it is in the presence of attenuation from the Buffer circuit.
 111

18.0 Conversion Gain

17.5

Magnitude (dB)
17.0
16.5
16.0
15.5
15.0
14.5
0 1 2 3 4 5
IF Frequency (MHz)

Figure 68: Conversion gain result for the post-layout simulation of the RF Front-End, IF
Amplifier and Buffer circuit for a 2.44 GHz input in 130nm BiCMOS technology.

Source: Author

Figure 69 shows the results for noise figure simulation of the RF Front-End, IF Am-
plifier and Buffer circuit. The result show a high noise value, near the maximum 20 dB
value considered. Thus, implying that the noise figure should be reduced in the blocks
after the LNA. Moreover, the LNA gain can be increased as an approach to reduce the
overall noise figure.

19.477
Noise Figure
19.377
Magnitude (dB)

19.277

19.177

19.077

18.977

18.877
0 2 4 6 8 10
Frequency (MHz)

Figure 69: Noise Figure post-layout simulation of LNA and Mixer for a 2.44 GHz input
in 130nm technology.

Source: Author
 112

Figure 70 shows the results for 1-dB compression point simulations of the RF Front-
End, IF Amplifier and Buffer circuit. The result matches with the required linearity
response for the implemented circuit.

−49
Linear -1dB
−54 Output Po er
−59
Output Po er (dBm)
−64
−69
−74
P1dB = − 31.3 dBm
−79
−84
−89
−94
−60 −55 −50 −45 −40 −35 −30 −25 −20
Input Po er (dBm)

Figure 70: 1-dB compression point result for the post-layout simulation of the RF Front-
End, IF Amplifier and Buffer in 130nm BiCMOS technology.

Source: Author

Figures 71, 72 and 73 show the results for the signal feedthrough analysis, standing for
the RF to IF port leakage, LO to IF port leakage, and LO to RF port leakage, respectively.
The results indicate a low leakage level among the ports.
 113

−43.5 RF-IF Leakage

−44.0
−44.5

Magnitude (dB)
−45.0
−45.5
−46.0
−46.5
−47.0

2.438 2.439 2.440 2.441 2.442 2.443

LO Fre uency (GHz)

Figure 71: Leakage signal result from RF to IF port for the post-layout simulation of RF
Front-End, IF Amplifier and Buffer circuit in 130nm BiCMOS technology.

Source: Author

−37.0675
LO-IF Leakage
−37.0975
Magnitude (dB)

−37.1275

−37.1575

−37.1875

−37.2175

−37.2475
2.438 2.439 2.440 2.441 2.442 2.443
LO F equency (GHz) 1e−9

Figure 72: Leakage signal result from LO to IF port for the post-layout simulation of RF
Front-End, IF Amplifier and Buffer circuit in 130nm BiCMOS technology.

Source: Author
 114

−88.453
LO-RF Leakage
−88.753

Magnitude (dB)
−89.053

−89.353

−89.653

−89.953

−90.253
2.438 2.439 2.440 2.441 2.442 2.443
LO F equency (GHz)

Figure 73: Leakage signal result from LO to RF port for the post-layout simulation of RF
Front-End, IF Amplifier and Buffer circuit in 130nm BiCMOS technology.

Source: Author

Table 33 shows the performance specifications achieved after the post-layout simula-
tions of the RF Front-End, IF Amplifier and Buffer circuit in 130nm BiCMOS technology.

Table 33: Summary of results obtained in post-layout simulations.

Parameter Value
Power Gain (S21) (dB) 14
Input Return Loss (S11) (dB) -23
Noise Figure (dB) 4
1-dB Compression Point (dBm) -32.24
IIP3 (dBm) -17.8
IDC (mA) 0.69
PDC (mW) 0.34
Re{Zin } (Ω) 40.3
Im{Zin } (Ω) 2.27

3.4.3 Experimental results

Figure 74 shows the die micrograph after fabrication of the RF Front-End, IF Ampli-
fier and Buffer circuit in GlobalFoundries 130nm BiCMOS technology.
 115

Figure 74: Die micrograph for the RF Front-End, IF Amplifier and Buffer circuit, fabri-
cated in GlobalFoundries 130nm BiCMOS technology.

Source: Author

The design of the PCB for testing the fabricated circuit followed the strategy describes
at the beginning of this chapter. Figure 75 shows the schematic capture of the PCB design
realized using Autodesk EAGLE software.

Figure 75: Schematic capture of the designed test PCB for the RF Front-End, IF Amplifier
and Buffer circuit in Autodesk EAGLE software.

Source: Author

Figure 76 shows the fabricated test PCB. The placement of the die used a conventional
 116

QFP packaging technology.

Figure 76: Fabricated test PCB for the RF Front-End, IF Amplifier and Buffer circuit.

Source: Author

After the test PCB fabrication, the experimental measurement of the fabricated cir-
cuits were performed. First, the S-Parameter measure with the Vector Network Analyzer
(VNA) was performed, analyzing the unmatched circuit input to support the design of the
passive input matching network design. After the input matching network realization in
the PCB, the tests using Specturm Analyzer and Oscilloscope were performed to observe
the output characteristics of the downconverted signal, and the resulting conversion gain.

The S-Parameter data was obtained using the Vector Network Analyzer (VNA) model
HP8510B [21], which was calibrated for the ISM band, from 1.5 GHz to 3.5 GHz.

Figure 77 shows the Smith Chart plot for the input reflection ratio (S11) obtained with
the data extracted from the measurement with the VNA. It shows that before applying
the matching circuit, the impedance was distant of the desired 50 ohm for 2.44 GHz.
 117

Figure 77: Smith Chart plot for S11 of experimental RF Front-End, IF Amplifier and
Buffer circuit.

Source: Author

Figure 78 shows the S-Parameters measurement results with data extracted from the
measurements in the VNA. It is possible to see that the input reflection (S11) is fairly
high for all the band, showing no match, therefore no input selectivity.
 118

3
−2
−7

Magnitude (dB)
−12
−17 S11
S12
−22 S21
−27 S22
−32
−37
−42
−47
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
Frequency (GHz)

Figure 78: S-Parameter analysis of the experimental RF Front-End, IF Amplifier and

Buffer circuit.

Source: Author

The extracted data was imported in the Keysight ADS software, as a way to design
a proper input matching circuit. Figure 79 describe the matching procedure using LC
elements. The procedure was performed using the Smith Chart Tool of Keysight ADS
software. Starting from the impedance seen on the previous figure for the measured
unmatched S11, the components were sized such that the final network could drive the
input impedance seen at its input to 50 Ω.
 119

Figure 79: Impedance transformation performed by the Smith Chart Tool in the Keysight
ADS software using the data extracted from the measurements of the unmatched RF
Front-End, IF Amplifier and Buffer circuit.

Source: Author

Figure 80 describes the obtained LC network, in which the component values are
described in the Table 34.

L1

C1

Figure 80: Designed ideal input matching circuit for the RF Front-End, IF Amplifier and
Buffer circuit.

Source: Author
 120

Table 34: Device dimensions for LC network input matching for the RF Front-End, IF
Amplifier and Buffer circuit in 130nm BiCMOS technology.
Parameter Ideal
L1 1.8 nH
C1 4.14 pF

Figure 81 shows the Smith Chart simulation for the input reflection ratio, S11, us-
ing the designed ideal matching network and the experimental data extracted from the
unmatched RF Front-End, IF Amplifier and Buffer circuit.

Figure 81: Smith Chart plot simulation for S11 of experimental RF Front-End circuit
with designed LC matching.

Source: Author

Figure 82 shows de S-Parameters results using the ideal input matching and un-
matched data from measurements of the RF Front-End, IF Amplifier and Buffer circuit.
 121

6
1
4
9
14

Magnitude (dB)
19 S11
24 S12
29 S21
34 S22
39
44
49
54
59
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
Frequency (GHz)

Figure 82: S-parameter simulation of experimental RF Front-End circuit with designed

LC matching.

Source: Author

After the simulations using Keysight ADS, the values were rounded to a near comercial
component value. With the adjusted component value, the input matching network was
realized in the PCB. After adjustments in the PCB, the matching network elements were
resized to better approximate the 50 Ω input impedance. The VNA was used to verify
the input impedance. The final result of the measured RF Front-End, IF Amplifier and
Buffer circuit using the real input matching is shown in figure 83.
 122

Figure 83: Smith Chart plot showing the measured S11 of the RF Front-End, IF Amplifier
and Buffer circuit with the real input matching circuit realized in the PCB.

Source: Author

Figure 84 shows the result for the S-Parameter measurement performed by the VNA
in the RF Front-End, IF Amplifier and Buffer circuit using the realized input matching
circuit.
 123

6
1
4
9
14
19

Magnitude (dB)
24
29
34
39
44
49
54 S11
59 S12
64 S21
69 S22
74
1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
Frequency (GHz)

Figure 84: S-parameter measurement of experimental RF Front-End circuit with imple-

mented LC matching.

Source: Author

Table 35 shows the values of the commercial components used to implement the real
input matching network in the PCB.

Table 35: Device dimensions for the experimental LC network input matching for the RF
Front-End, IF Amplifier and Buffer circuit in 130nm BiCMOS technology.
Parameter Implemented
L1 1.8 nH
C1 1.1 pF

After the input matching measurements using the VNA, the Keysight Infiniivision
DSOX6004A oscilloscope at 6 GSPS, was used to analyze the transient response of the
circuits. The results include a low-pass filering with 20 MHz passband, to allow the
evaluation of the downconverted IF signal at 2 MHz. Figure 85 shows the resulting IF
signal for a 2.44 GHz input. The figure includes the voltages at each output node, and
the resulting differential output voltage.
 124

37
32
27
22
17
12

Voltage (mV)
7
2
−3
−8
−13
−18
−23
−28
−33 Vout, 1 Vout, 2 Vout, diff
−38
1.6 1.8 2.0 2.2 2.4
Time (μs)

Figure 85: Differential and single-ended output signals for 0.5V supply.

Source: Author

Figure 86 shows the resulting IF signal for a 2.44 GHz input, at different supply
voltage values.

37
34
31
28
25
22
19
16
13
Voltage (mV)

10
7
4
1
−2
−5
−8
−11
−14
−17
−20
−23
−26 0.3 V 0.4 V 0.5 V
−29
−32 0.35 V 0.45 V
−35
−38
1.6 1.8 2.0 2.2 2.4
Time (μs)

Figure 86: Transient output IF signal for different supply voltages.

Source: Author

Figure 87 shows a comparison between the output rms voltage Vout as a function of
the supply voltage, and the input rms voltage Vin .
 125

18 Vout
Vin
16

Voltage (mVrms)
14
12
10
8
6
4
0.30 0.35 0.40 0.45 0.50
VDD (V)

Figure 87: Input and output rms signals as a function of VDD .

Source: Author

Table 36 shows the performance specifications achieved in experimental circuit.

Considering that power gain has suffered decrements from the buffer and from board
unmatched transmission line parts.

Despite the higher power, it has a better band tuning and higher gain than the first
fabricated circuit.

Table 36: Summary of results obtained in experimental circuit.

Parameter Value
Power Gain (S21) (dB) 11
Input Return Loss (S11) (dB) -58
IDC (mA) 0.7
PDC (mW) 0.35
 126

4 CONCLUSION

In this chapter the main obtained results will be discussed, and also compared with
the expected theoretical values.

4.1 Results Discussion

During the implementation phase of this work, three designs were performed. All the
circuits are focused on low voltage and low power operation. First a LNA circuit was
implemented in 180nm CMOS technology. Then, the LNA received improvements and
was fabricated in the same technology node. Finally, the third design implemented a
Front-End and IF amplifier system in a 130nm BiCMOS technology.

The circuits passed through post-layout simulations and experimental measurements

to verify their proximity to the expected performance. In the case of 180nm technology,
the area obtained was bigger, for the same performance specifications. Moreover, due
to the use of low voltage, forward body biasing techniques were necessary to obtain a
sufficient Vth reduction for proper device biasing, without it, the devices would operate in
weak inversion region, thus needing prohibitively large area to achieve the required speed
and transconductance, and in some cases even not having the required maximum transfer
frequency for proper operation.

The noise analysis of the post-layout simulations showed good results, within the
expected values, and since the BLE standard does not require very low values, the achieved
performance was sufficient.

The linearity of the circuits proven to be very tied to the requirements in the post-
layout simulations. The reduction on the supply voltage value imposed severe reduction
on the maximum input voltage allowed. If the theoretical commonly used value of 0
dBm [26, 27] was considered in the input, the gain compression and third intercept point
at the input would be insufficient.
 127

4.2 Future Works

For future works it would be of good contribution also include the design of the full
Front-End system in a technology that impose the same Vth critical values as the 180nm
technology used for the first two designs in this work. The study of the forward body
biasing could be extend to the other blocks and evaluated from their point of view.

Linearity improvement techniques could be analyzed and applied to overcome the

restrictions seen on the results of this work. In [56] linearization techniques using parallel
PMOS devices would be applied to help. Also, differential implementations would be
studied, however with added power and area.

A better analysis on the test boards could be applied to identify and solve transmission
line problems that brought degradations to the matching on the experimental settings of
this work. A design with help of a software capable of performing electromagnetic (EM)
simulations would help to evaluate the influence of parasitic devices and transmission line
nonlinearities.

It was observed that the sampling mixer impose a serious restriction due to necessity
of using an input common mode voltage. With low supply voltage, this common mode
voltage critically approaches the VDD − Vth which limits the input voltage of the MOS
switches and add nonlinearity behavior.
 128

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