CD4049UB, CD4050B
Data sheet acquired from Harris Semiconductor August 1998 - Revised May 2004
SCHS046I
CMOS Hex Buffer/Converters Applications
The CD4049UB and CD4050B devices are inverting and • CMOS to DTL/TTL Hex Converter
non-inverting hex buffers, respectively, and feature logic- • CMOS Current “Sink” or “Source” Driver
level conversion using only one supply voltage (VCC). The
• CMOS High-To-Low Logic Level Converter
input-signal high level (VIH) can exceed the VCC supply
[ /Title voltage when these devices are used for logic-level
conversions. These devices are intended for use as CMOS
Ordering Information
(CD40 to DTL/TTL converters and can drive directly two DTL/TTL TEMP.
49UB, loads. (VCC = 5V, VOL ≤ 0.4V, and IOL ≥ 3.3mA.) PART NUMBER RANGE (oC) PACKAGE
CD405 The CD4049UB and CD4050B are designated as CD4049UBF3A -55 to 125 16 Ld CERDIP
0B) replacements for CD4009UB and CD4010B, respectively. CD4050BF3A -55 to 125 16 Ld CERDIP
/Sub- Because the CD4049UB and CD4050B require only one
power supply, they are preferred over the CD4009UB and CD4049UBD -55 to 125 16 Ld SOIC
ject CD4010B and should be used in place of the CD4009UB CD4049UBDR -55 to 125 16 Ld SOIC
(CMO and CD4010B in all inverter, current driver, or logic-level
S Hex conversion applications. In these applications the CD4049UBDT -55 to 125 16 Ld SOIC
Buffer/ CD4049UB and CD4050B are pin compatible with the CD4049UBDW -55 to 125 16 Ld SOIC
CD4009UB and CD4010B respectively, and can be
Con- substituted for these devices in existing as well as in new CD4049UBDWR -55 to 125 16 Ld SOIC
verters) designs. Terminal No. 16 is not connected internally on the CD4049UBE -55 to 125 16 Ld PDIP
/Autho CD4049UB or CD4050B, therefore, connection to this CD4049UBNSR -55 to 125 16 Ld SOP
r () terminal is of no consequence to circuit operation. For
applications not requiring high sink-current or voltage CD4049UBPW -55 to 125 16 Ld TSSOP
/Key- conversion, the CD4069UB Hex Inverter is recommended.
CD4049UBPWR -55 to 125 16 Ld TSSOP
words
(Harris Features CD4050BD -55 to 125 16 Ld SOIC
Semi- • CD4049UB Inverting CD4050BDR -55 to 125 16 Ld SOIC
con- • CD4050B Non-Inverting CD4050UBDT -55 to 125 16 Ld SOIC
ductor, • High Sink Current for Driving 2 TTL Loads CD4050BDW -55 to 125 16 Ld SOIC
CD400 • High-To-Low Level Logic Conversion CD4050BDWR -55 to 125 16 Ld SOIC
0, • 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package CD4050BE -55 to 125 16 Ld PDIP
metal Temperature Range; 100nA at 18V and 25oC CD4050NSR -55 to 125 16 Ld SOP
gate, • 5V, 10V and 15V Parametric Ratings
CMOS CD4050BPW -55 to 125 16 Ld TSSOP
CD4050BPWR -55 to 125 16 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffix R denotes tape
and reel. The suffix T denotes a small-quantity reel of 250.
Pinouts
CD4049UB (PDIP, CERDIP, SOIC, SOP, TSSOP) CD4050B (PDIP, CERDIP, SOIC, SOP)
TOP VIEW TOP VIEW
VCC 1 16 NC VCC 1 16 NC
G=A 2 15 L = F G=A 2 15 L = F
A 3 14 F A 3 14 F
H=B 4 13 NC H=B 4 13 NC
B 5 12 K = E B 5 12 K = E
I=C 6 11 E I=C 6 11 E
C 7 10 J = D C 7 10 J = D
VSS 8 9 D VSS 8 9 D
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
CD4049UB, CD4050B
Functional Block Diagrams
CD4049UB CD4050B
3 2 3 2
A G=A A G=A
5 4 5 4
B H=B B H=B
7 6 7 6
C I=C C I=C
9 10 9 10
D J=D D J=D
11 12 11 12
E K=E E K=E
14 15 14 15
F L=F F L=F
1 1
VCC VCC
8 8
VSS VSS
NC = 13 NC = 13
NC = 16 NC = 16
Schematic Diagrams
VCC VCC
P P P
R OUT R
IN IN OUT
N N N
VSS VSS
FIGURE 1A. SCHEMATIC DIAGRAM OF CD4049UB, 1 OF 6 FIGURE 1B. SCHEMATIC DIAGRAM OF CD4050B, 1 OF 6
IDENTICAL UNITS IDENTICAL UNITS
