Data Sheet

AD45335
32-Channel, 14-Bit DAC with Full-Scale Output
Voltage Programmable from 50 V to 200 V
FEATURES APPLICATIONS
► High integration ► Optical microelectromechanical systems (MEMS)
► 32-channel, 14-bit denseDAC® with integrated high voltage out- ► Optical crosspoint switches
put amplifier ► Micropositioning applications using piezoelectric actuators
► Guaranteed monotonic ► Level setting in automotive test and measurement
► Housed in a 15 mm × 15 mm CSP_BGA package
► Full-scale output voltage programmable from 50 V to 200 V GENERAL DESCRIPTION
through reference input The AD45335 is a 32-channel, 14-bit denseDAC® with an on-chip
► 150/40 µA source/sink drive capability high voltage output amplifier. The AD45335 is targeted for optical
► Integrated silicon diode for temperature monitoring micro-electromechanical systems. The output voltage range is pro-
► SPI grammable through the REF_IN pin. The output range is 0 V to
► 1.2 MHz channel update rate 50 V when REF_IN = 1 V, and 0 V to 200 V when REF_IN = 4 V.
REF_IN is buffered internally on the AD45335 and must be driven
► Asynchronous RESET facility
from a stable reference source.
► –10°C to +85°C temperature range
The selected digital-to-analog converter (DAC) register is written
to using the 3-wire interface. The serial peripheral interface (SPI)
operates at clock rates of up to 30 MHz.
FUNCTIONAL BLOCK DIAGRAM

Figure 1. Functional Block Diagram

Rev. 0
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Data Sheet AD45335
TABLE OF CONTENTS

Features................................................................ 1 Theory of Operation.............................................12

Applications........................................................... 1 DAC Section.....................................................12
General Description...............................................1 Reset Function................................................. 12
Functional Block Diagram......................................1 Serial Interface................................................. 12
Specifications........................................................ 3 Applications Information...................................... 13
Timing Characteristics........................................5 MEMS Mirror Control Application..................... 13
Absolute Maximum Ratings...................................6 IPC-221-Compliant Board Layout.................... 14
Thermal Resistance........................................... 6 Power Supply Decoupling
Electrostatic Discharge (ESD) Ratings...............6 Recommendations......................................... 15
ESD Caution.......................................................6 Guidelines for PCB Layout............................... 15
Pin Configuration and Function Descriptions........ 7 Outline Dimensions............................................. 16
Typical Performance Characteristics..................... 9 Ordering Guide.................................................16
Terminology......................................................... 11 Evaluation Board.............................................. 16

REVISION HISTORY

10/2023—Revision 0: Initial Version

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Data Sheet AD45335
SPECIFICATIONS

VPP = 55 V to 225 V, 4.75 ≤ V+ ≤ 5.25 V, 4.75 V ≤ AVCC ≤ 5.25 V, 2.7 V ≤ DVCC ≤ 5.25 V, PGND = AGND = DGND = DAC_GND = 0 V, AVCC
and V+ must exceed REF_IN by 1.15 V minimum, 1 V ≤ REF_IN ≤ 4.096 V, –10°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 1. Specifications
Parameter1 Min Typ Max Unit Test Conditions/Comments
DC PERFORMANCE2, 3
Resolution 14 Bits
Integral Nonlinearity (INL) ±0.1 % of full-scale
range (FSR)
Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic
Zero Code Voltage +1 V
Output Offset Error –1 +1 V
Offset Drift 0.5 mV/°C
Voltage Gain 49 50 51 V/V Per channel
Gain Temperature Coefficient –20 ppm/°C
OUTPUT CHARACTERISTICS
Output Voltage Range2
No Load 1 VPP – 1.5 V
4 MΩ Load to Ground (GND) 1 VPP – 2.5 V
Output Impedance 50 Ω
Resistive Load4 4 MΩ To GND
Capacitive Load 200 pF
Short-Circuit Current5
Sourcing 0.15 mA
Sinking 0.04 mA
DC Crosstalk –4 +4 LSB
DC Power Supply Rejection Ratio (PSRR), VPP −70 dB
Long-Term Drift 0.25 LSB Outputs at midscale, measured over 30
days at 25°C
AC CHARACTERISTICS
Settling Time
Falling Edge
¾ to ¼ Scale Step 70 µs No load
470 µs 200 pF load
1 LSB Step 20 µs
Rising Edge
¼ to ¾ Scale Step 70 µs No load
190 µs 200 pF load
1 LSB Step 10 µs
Slew Rate
Falling Edge 1.2 V/µs No load
0.2 V/µs 200 pF load
Rising Edge 1.6 V/µs No load
0.6 V/µs 200 pF load
–3 dB Bandwidth 30 kHz
Output Noise Spectral Density 4.5 µV/√Hz Measured at 10 kHz
0.1 Hz to 10 Hz Output Noise Voltage 1 mV p-p
Digital-to-Analog Glitch Impulse 1 LSB change around major carry
Positive Transition 15 nV-sec
Negative Transition 8 nV-sec
Analog Crosstalk 1 µV-sec

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Data Sheet AD45335
SPECIFICATIONS

Table 1. Specifications (Continued)

Parameter1 Min Typ Max Unit Test Conditions/Comments
Digital Feedthrough 2 nV-sec
VOLTAGE REFERENCE, REF_IN6
Input Voltage Range 1 4.096 V
Input Impedance 60 kΩ
TEMPERATURE MEASUREMENT DIODE
Peak Inverse Voltage (PIV) 5 V Cathode to anode
Forward Diode Drop, Forward Voltage (VF) 0.65 0.8 V IF = 100 µA, anode to cathode
Forward Diode Current, Forward Current (IF) 150 µA Anode to cathode
VF Temperature Coefficient (TC) −2.20 mV/°C Anode to cathode
DIGITAL INPUTS
Input Current ±5 ±10 µA
Input Low Voltage 0.2 × DVCC V
Input High Voltage 0.8 × DVCC V
Input Hysteresis (SCLK and SYNC Only) 200 mV
Input Capacitance 10 pF
POWER SUPPLY VOLTAGES
VPP (51 × REF_IN) + 2.5 225 V
V+ 4.75 5.25 V
AVCC 4.75 5.25 V
DVCC 2.7 5.25 V
POWER SUPPLY CURRENTS3
IVPP
All Channels at Full-Scale 80 92 µA/channel
All Channels at Zero-Scale 45 55 µA/channel
IV+ 0.75 0.9 mA
IAVCC 17.5 20 mA
IDVCC 0.25 0.6 mA
1 See the Terminology section.
2 Linear output voltage range: 7 V to VPP – 1.5 V or 51 x REF_IN (whichever is less).
3 Outputs unloaded.
4 Ensure that maximum TJ is not exceeded. See the Absolute Maximum Ratings section.
5 Output shorts to ground increase the on-chip power dissipation and therefore the chip junction temperature. Operation at or above the specified maximum operation
junction temperature may impair device reliability.
6 Reference input determines the output voltage range. The linear output voltage range is restricted from 7 V to VPP – 1.5 V, or 51 x REF_IN (whichever is less).

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Data Sheet AD45335
SPECIFICATIONS

TIMING CHARACTERISTICS
VPP = 55 V to 225 V; 4.75 ≤ V+ ≤ 5.25 V; 4.75 V ≤ AVCC ≤ 5.25 V; 2.7 V ≤ DVCC ≤ 5.25 V; PGND = AGND = DGND = DAC_GND = 0 V;
AVCC and V+ must exceed REF_IN by 1.15 V minimum; 1 V ≤ REF_IN ≤ 4.096 V; –10°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 2. Timing Characteristics
Parameter1, 2, 3 Max Min Unit Test Conditions/Comments
fUPDATE 1.2 MHz Channel update rate
fCLKIN 30 MHz SCLK frequency
t1 13 ns SCLK high pulse width
t2 13 ns SCLK low pulse width
t3 15 ns SYNC falling edge to SCLK falling edge setup time
t4 50 ns SYNC low time
t5 10 ns SYNC high time
t6 10 ns DIN setup time
t7 5 ns DIN hold time
t8 200 ns 19th SCLK falling edge to SYNC falling edge for next write
t9 20 ns RESET pulse width
1 See Figure 2.
2 Guaranteed by design and characterization, not production tested.
3 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.

Figure 2. Serial Interface Timing Diagram

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Data Sheet AD45335
ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to 100 ELECTROSTATIC DISCHARGE (ESD) RATINGS
mA do not cause (silicon-controlled rectifier) SCR latch-up.
The following ESD information is provided for handling of ESD-sen-
Table 3. Absolute Maximum Ratings sitive devices in and ESD-protected area only.
Parameter Rating
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
VPP to AGND −0.3 V to +240 V
V+ to AGND −0.3 V to +7 V Field induced charged-device model (FICDM) per ANSI/ESDA/JE-
AVCC to AGND, DAC_GND −0.3 V to +7 V DEC JS-002.
DVCC to DGND −0.3 V to +7 V
Digital Inputs to DGND −0.3 V to DVCC + 0.3 V or ESD Ratings for the AD45335
+7 V (whichever is less) Table 5. AD45335, 124-Lead CSP_BGA
REF_IN to AGND, DAC_GND −0.3 V to AVCC + 0.3 V or +7 V ESD Model Withstand Threshold (V) Class
(whichever is less)
HBM 2500 2
VOUT0 to VOUT31 to AGND –0.3 V to VPP + 0.3 V
FICDM 400 C1
ANODE/CATHODE to AGND, DAC_GND −0.3 V to +7 V
AGND to DGND −0.3 V to +0.3 V ESD CAUTION
Operating Temperature Range
ESD (electrostatic discharge) sensitive device. Charged devi-
Industrial −10°C to +85°C
ces and circuit boards can discharge without detection. Although
Storage Temperature Range −65°C to +150°C this product features patented or proprietary protection circuitry,
Junction Temperature (Maximum TJ) 150°C damage may occur on devices subjected to high energy ESD.
Lead Temperature JEDEC industry standard Therefore, proper ESD precautions should be taken to avoid
Soldering J-STD-020 performance degradation or loss of functionality.
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operat-
ing conditions for extended periods may affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to PCB
thermal design is required.
θJA is the natural convection junction-to-ambient thermal resistance
measured in a one cubic foot sealed enclosure.
Table 4. Thermal Resistance
Package Type θJA Unit
BC-124-4 40 °C/W

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Data Sheet AD45335
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description
A1 NC No Connect. Do not connect to these pins.
A2 VOUT1 Analog Output Voltages from the 32 Channels.
A4 VOUT7 Analog Output Voltages from the 32 Channels.
A6 VOUT11 Analog Output Voltages from the 32 Channels.
A8 VOUT16 Analog Output Voltages from the 32 Channels.
A10 VOUT20 Analog Output Voltages from the 32 Channels.
A12 VOUT25 Analog Output Voltages from the 32 Channels.
A14 NC No Connect. Do not connect to these pins.
B1 VOUT0 Analog Output Voltages from the 32 Channels.
B3 VOUT4 Analog Output Voltages from the 32 Channels.
B5 VOUT9 Analog Output Voltages from the 32 Channels.
B7 VOUT13 Analog Output Voltages from the 32 Channels.
B9 VOUT17 Analog Output Voltages from the 32 Channels.
B11 VOUT21 Analog Output Voltages from the 32 Channels.
B13 VOUT26 Analog Output Voltages from the 32 Channels.
C2 VOUT3 Analog Output Voltages from the 32 Channels.
C12 VOUT22 Analog Output Voltages from the 32 Channels.
C14 VOUT29 Analog Output Voltages from the 32 Channels.
D1 VOUT2 Analog Output Voltages from the 32 Channels.
D13 VOUT23 Analog Output Voltages from the 32 Channels.
E2 VOUT5 Analog Output Voltages from the 32 Channels.
E4 VOUT8 Analog Output Voltages from the 32 Channels.
E6 VOUT12 Analog Output Voltages from the 32 Channels.
E8 VOUT15 Analog Output Voltages from the 32 Channels.
E10 VOUT19 Analog Output Voltages from the 32 Channels.
E12 VOUT24 Analog Output Voltages from the 32 Channels.
E14 VOUT31 Analog Output Voltages from the 32 Channels.
F3 VOUT6 Analog Output Voltages from the 32 Channels.
F5 VOUT10 Analog Output Voltages from the 32 Channels.
F7 VOUT14 Analog Output Voltages from the 32 Channels.
F9 VOUT18 Analog Output Voltages from the 32 Channels.
F13 VOUT30 Analog Output Voltages from the 32 Channels.
G14 VOUT28 Analog Output Voltages from the 32 Channels.
H1, H2 VPP Output Amplifier High Voltage Supply.
H4 to H11 AGND Analog GND Pins.
H13 VOUT27 Analog Output Voltages from the 32 Channels.
J3 to J12 AGND Analog GND Pins.

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Data Sheet AD45335
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 6. Pin Function Descriptions (Continued)

Pin No. Mnemonic Description
K1, K2 V+ V+ Amplifier Supply Pins.
K3 to K14 AGND Analog GND Pins.
L1, L2 NC No Connect. Do not connect to these pins.
L3 to L13 AGND Analog GND Pins.
L14 DAC_GND Reference GND Supply for All DACs.
M1 to M12 AGND Analog GND Pins.
M13, M14 AVCC Analog Supply Pins.
N1, N2 PGND Output Amplifier Ground Reference Pins.
N3 CATHODE Cathode of Internal Diode for Diode Temperature Measurement.
N4 ANODE Anode of Internal Diode for Diode Temperature Measurement.
N5 to N14 AGND Analog GND Pins.
P1 NC No Connect. Do not connect to these pins.
P2 REF_IN Reference Voltage for Channel 0 to Channel 31.
P3 DAC_GND Reference GND Supply for All DACs.
P4 RESET Active Low Input. This pin can also be used to reset the complete device to its power-on reset conditions.
Zero code is loaded to the DACs.
P5 DVCC Digital Supply Pins.
P6 DGND Digital GND Pins.
P7 TEST For normal operation, tie this pin low.
P8 DIN Serial Data Input. Data must be valid upon the falling edge of SCLK.
P9 SCLK Serial Clock Input. Data is clocked into the shift register upon the falling edge of SCLK. The pin operates
at clock speeds of up to 30 MHz. Internal pull-up device on logic input. Therefore, it can be left floating
and defaults to a logic high condition.
P10 SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data
is transferred in upon the falling edge of SCLK.
P11 to P13 AGND Analog GND Pins.
P14 NC No Connect. Do not connect to these pins.

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Data Sheet AD45335
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. INL with Full-Scale Range = 50 V Figure 7. DNL with Full-Scale Range = 200 V

Figure 5. DNL with Full-Scale Range = 50 V Figure 8. Short-Circuit Current Limit Timing

Figure 6. INL with Full-Scale Range = 200 V Figure 9. Worst-Case Adjacent Channel Crosstalk

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Data Sheet AD45335
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 13. Cumulative DC Crosstalk Effects on a Single-Channel Output,

Figure 10. Output Amplifier Source and Sink Capability
Switching All Other Channels in Sequence

Figure 11. Offset Error vs. Temperature

Figure 14. Settling Time Rising Edge at Various Capacitive Loads

Figure 12. Gain Error vs. Temperature

Figure 15. Settling Time Falling Edge at Various Capacitive Loads

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Data Sheet AD45335
TERMINOLOGY

Integral Nonlinearity (INL) DC Crosstalk

A measure of the maximum deviation from a straight line passing The DC change in the output level of one DAC at midscale in
through the endpoints of the DAC transfer function. response to a full-scale code change (all 0s to all 1s and vice versa)
It is expressed as a percentage of full-scale range. and the output change of all other DACs. It is expressed in LSB.
Differential Nonlinearity (DNL) Output Voltage Settling Time
The difference between the measured change and the ideal 1 LSB The time taken from when the last data bit is clocked into the DAC
change between any two adjacent codes. A specified until the output has settled to within ±0.5 LSB of its final value.
DNL of ±1 LSB maximum ensures monotonicity. Measured for a step change of ¼ to ¾ full scale.
Zero Code Voltage Digital-to-Analog Glitch Impulse
A measure of the output voltage present at the device output with The area of the glitch injected into the analog output when
all 0s loaded to the DAC. It includes the offset of the the code in the DAC register changes state. It is specified as
DAC and the output amplifier and is expressed in V. the area of the glitch in nV-sec when the digital code is changed
by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or
Offset Error 100 . . . 00 to 011 . . . 11).
Calculated by taking two points in the linear region of the transfer Analog Crosstalk
function, drawing a line through these points, and extrapolating
back to the y-axis. It is expressed in V. The area of the glitch transferred to the output (VOUT) of one DAC
due to a full-scale change in the output (VOUT) of another DAC. The
Voltage Gain area of the glitch is expressed in nV-sec.
Calculated from the change in output voltage for a change in code, Digital Feedthrough
multiplied by 16,384, and divided by the REF_IN voltage. This is
calculated between two points in the linear section of the transfer A measure of the impulse injected into the analog outputs from the
function. digital control inputs when the part is not being written to (SYNC
is high). It is specified in nV-sec and measured with a worst-case
Gain Error change on the digital input pins, for example, from all 0s to all 1s
A measure of the output error with all 1s loaded to the DAC, and and vice versa.
the difference between the ideal and actual analog output range. Output Noise Spectral Density
Ideally, the output should be 50 × REF_IN. It is expressed as a
percentage of full-scale range. A measure of internally generated random noise. Random noise
is characterized as a spectral density (voltage per √Hz). It is
DC Power Supply Rejection Ratio (PSRR) measured by loading all DACs to midscale and measuring noise at
A measure of the change in analog output for a change in VPP the output. It is measured in μV/√Hz.
supply voltage. It is expressed in dB, and VPP is varied ±5%.

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Data Sheet AD45335
THEORY OF OPERATION

The AD45335 consists of a 32-channel, 14-bit DAC with 200 V SERIAL INTERFACE
high voltage amplifiers in a single 15 mm × 15 mm chip scale
package ball grid array (CSP_BGA). The output voltage range is The serial interface is controlled by the following pins:
programmable through the REF_IN pin. The output range is 0 V to ► SYNC, which is the frame synchronization pin for the serial
50 V when REF_IN = 1 V, and 0 V to 200 V when REF_IN = 4 V. interface.
Communication to the device is through a serial interface operating
at clock rates of up to 30 MHz, which is compatible with digital ► SCLK, which is the serial clock input that operates at clock
signal processing (DSP) and microcontroller interface standards. A speeds of up to 30 MHz.
5-bit address and a 14-bit data-word are loaded into the AD45335 ► DIN, which is the serial data input, and data must be valid upon
input register through the serial interface. The channel address is the falling edge of SCLK.
decoded, and the data-word is converted into an analog output
voltage for this channel. To update a single DAC channel, a 19-bit data-word is written to the
AD45335 input register, as shown in Figure 16.
At power-on, all the DAC registers are loaded with 0s.
DAC SECTION A4 to A0 Bits

The architecture of each DAC channel consists of a resistor The A4 to A0 bits can address any one of the 32 channels. A4 is
string DAC, followed by an output buffer amplifier operating with the MSB of the address, while A0 is the LSB.
a nominal gain of 50. The voltage at the REF_IN pin provides the
reference voltage for the corresponding DAC. The input coding to DB13 to DB0 Bits
the DAC is straight binary, and the ideal DAC output voltage is The DB13 to DB0 bits are used to write a 14-bit data-word into the
given by addressed DAC register.
50 × VREF_IN × D
VOUT = Figure 2 is the timing diagram for a serial write to the AD45335. The
214
serial interface works with both a continuous and a discontinuous
where D is the decimal equivalent (0 to 16,383) of the binary code, serial clock. The first falling edge of SYNC resets the serial clock
which is loaded to the DAC register. counter to ensure that the correct number of bits are shifted into the
serial shift register. Any further edges on SYNC are ignored until
The output buffer amplifier is specified to drive a load of 4 MΩ and the correct number of bits are shifted in. After 19 bits are shifted in,
200 pF. The linear output voltage range for the output amplifier is the SCLK is ignored. For another serial transfer to take place, the
from 7 V to VPP – 1.5 V. The amplifier output bandwidth is typically counter must be reset by the falling edge of SYNC. The user must
30 kHz, and is capable of sourcing 150 µA and sinking 40 µA. allow 200 ns (minimum) between successive writes.
RESET FUNCTION
The reset function on the AD45335 can be used to reset all nodes
on the device to their power-on reset condition. All the DACs are Figure 16. Serial Data Format
loaded with 0s, and all registers are cleared. Take the RESET pin
low to implement the reset function.

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Data Sheet AD45335
APPLICATIONS INFORMATION

The AD45335 is generally used in a closed-loop feedback system,

MEMS MIRROR CONTROL APPLICATION as shown in Figure 17, with a high resolution analog-to-digital
The AD45335 is targeted to all optical switching control systems converter (ADC) and DSP. The exact position of each mirror is
based on MEMS technology. The AD45335 is a 32-channel, 14-bit measured using capacitive sensors. The sensor outputs are multi-
DAC with integrated high voltage amplifiers. The output amplifiers plexed using an ADG739 4-to-1 multiplexer (MUX) to an 8-channel,
are capable of generating an output range of 0 V to 200 V when us- 14-bit ADC (AD7856). An alternative solution is to multiplex using a
ing a 4 V reference. The full-scale output voltage is programmable 32-to-1 multiplexer (ADG732) into a single-channel ADC (AD7671).
from 50 V to 200 V using reference voltages from 1 V to 4 V. Each With 14-bit monotonic behavior and a 0 V to 200 V output range,
amplifier can output 150 µA sourcing current and directly drives the coupled with its fast serial interface, the AD45335 is ideally suited
control actuators, which determine the position of MEMS mirrors in for controlling a cluster of MEMS-based mirrors.
optical switch applications.

Figure 17. AD45335 in a MEMS-Based Optical Switch

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Data Sheet AD45335
APPLICATIONS INFORMATION

IPC-221-COMPLIANT BOARD LAYOUT The routing shown in Figure 18 shows the feasibility of connecting
to the high voltage balls while complying with the spacing require-
The diagram in Figure 18 is a typical 2-layer PCB layout for the ments of IPC-221. Figure 18 also shows the physical distances that
AD45335 that complies with the specifications outlined in IPC-221. are available.
Do not connect to the four corner balls labeled as original no con-
nects. Connect balls labeled as additional no connects to AGND.

Figure 18. Layout Guidelines to Comply with IPC-221

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Data Sheet AD45335
APPLICATIONS INFORMATION

POWER SUPPLY DECOUPLING Keep traces for analog inputs as wide and short as possible and
RECOMMENDATIONS shield with analog ground if possible. Run traces on opposite sides
of the 2-layer PCB at right angles to each other to reduce the
On the AD45335, it is recommended to tie all grounds together as effects of feedthrough through the board.
close to the device as possible. If the number of supplies must be
reduced, bring all supplies back separately and make a provision A microstrip technique is by far the best, but it is not always
on the PCB through a link option to drive the AVCC and V+ pins from possible to use with a double-sided board. In this technique,
the same supply. Decouple all power supplies adequately with 10 the component side of the board is dedicated to ground planes,
µF tantalum capacitors and 0.1 µF ceramic capacitors. and signals are placed on the solder side. Multilayer PCBs with
dedicated ground, power, and tracking layers offer the optimum
GUIDELINES FOR PCB LAYOUT solution in terms of obtaining analog performance, but at increased
Design PCBs such that the analog and digital sections are separat- manufacturing costs.
ed and confined to the designated analog and digital sections of Good decoupling is vitally important when using high resolution
the board. This facilitates the use of ground planes that can be converters. Decouple all analog supplies with 10 µF tantalum ca-
separated easily. A minimum etch technique is generally the best pacitors in parallel with 0.1 µF ceramic capacitors to analog ground.
for ground planes because it optimizes shielding of sensitive signal To achieve the best results from the decoupling components, place
lines. Join digital and analog ground planes in one place only, at them as close to the device as possible, ideally right up against the
the AGND and DGND pins of the high resolution converter. To IC or the IC socket. The main aim of a bypassing element is to
isolate the high frequency bus of the processor from the bus of maximize the charge stored in the bypass loop while simultaneous-
the high resolution converters, buffer or latch data and address ly minimizing the inductance of this loop. Inductance in the loop
buses on the board. These act as a Faraday shield and increase acts as an impedance to high frequency transients and results in
the signal-to-noise performance of the converters by reducing the power supply spiking. By keeping the decoupling as close to the
amount of high frequency digital coupling. Avoid running digital lines device as possible, the loop area is kept as small as possible,
under the device because they couple noise onto the die. Allow the thereby reducing the possibility of power supply spikes. Decouple
ground plane to run under the IC to avoid noise coupling. digital supplies of high resolution converters with 10 µF tantalum
Use as large a trace as possible for the supply lines of the device capacitors and 0.1 µF ceramic capacitors to the digital ground
to provide low impedance paths and reduce the effects of glitches plane. Decouple the V+ supply with a 10 µF tantalum capacitor and
on the power supply line. Shield components, such as clocks with a 0.1 µF ceramic capacitor to AGND.
fast-switching signals, with digital ground to avoid radiating noise to Decouple all logic chips with 0.1 µF ceramic capacitors to digital
other sections of the board. Never run clock signals near the analog ground to decouple high frequency effects associated with digital
inputs of the device. Avoid crossovers of digital and analog signals. circuitry.

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Data Sheet AD45335
OUTLINE DIMENSIONS

Figure 19. 124-Lead Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-124-4)
Dimensions shown in millimeters

Updated: September 05, 2023

ORDERING GUIDE
Package
Model1 Temperature Range Package Description Packing Quantity Option
AD45335KBCZ -10°C to +85°C 124-Ball CSP-BGA (15mm x 15mm x 1.29mm) Tray, 126 BC-124-4
1 Z = RoHS Compliant Part.

EVALUATION BOARD
Model1 Description
EVAL-AD45335SDZ AD45335 Evaluation Board
1 Z = RoHS Compliant Part.

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registered trademarks are the property of their respective owners.
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