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PD Trained Esaku 2k23

Pinni Esaku is a recent B.Tech graduate in Electronics and Communication Engineering with a CGPA of 7.2, seeking a position as a VLSI Design Engineer. He has 10 months of training in VLSI Physical Design, hands-on experience with 28nm technology, and has completed multiple projects involving ASIC physical design flow. Esaku is certified in Static Timing Analysis by Cadence and is proficient in various technical skills related to physical design implementation.

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44 views3 pages

PD Trained Esaku 2k23

Pinni Esaku is a recent B.Tech graduate in Electronics and Communication Engineering with a CGPA of 7.2, seeking a position as a VLSI Design Engineer. He has 10 months of training in VLSI Physical Design, hands-on experience with 28nm technology, and has completed multiple projects involving ASIC physical design flow. Esaku is certified in Static Timing Analysis by Cadence and is proficient in various technical skills related to physical design implementation.

Uploaded by

kollasunnykumar123
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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RESUME

Name : PINNI ESAKU


Mobile No : 9347155483
Email ID : [email protected]

CAREER OBJECTIVE

To become part of our team by taking up the role of a VLSI Design Engineer Where I can use my skills in
Physical design for developing high-performance integrated circuits.

PROFESSIONAL QUALIFICATION
 Trained in VLSI Physical Design at Sumedha IT Institute for 10 months.
 Worked on technology node 28nm.
 Hands on experience in ASIC physical Design Flow

ACADEMICS

Graduation Details

Degree : Bachelor of Technology (B. Tech)


College : Vignan's Lara Institute of Tech and Science
Year of passing : 2023
CGPA : 7.2
Course : Electronics and Communication Engineering

Higher Secondary

College : Sri Chaitanya College


Year of passing : 2019
CGPA : 9.1 CGPA
Course : MPC

School : Loyola High School


Year of passing : 2017
CGPA : 9.3 CGPA
TECHNICAL SKILLS

● Knowledge in synthesis and STA tools.

● CMOS technology fundamentals.

● Ability to perform floor planning, placement and routing.

● Clock Tree Synthesis (CTS).

● Comprehensive knowledge of Physical Design Implementation, Physical Design Strategies.

PROJECTS

PROJECT 1: ALU

Technology : TSMC 28nm

Tools : DC_Shell-Synthesis & ICC2_Shell-PNR flow


Frequency : 200 MHZ
No. of Clocks : 2

Description : Completed with Sanity checks and fixed Setup violations.

Challenges : Faced difficulty in fixing setup timing paths for different path groups. Initially
can’t able to list out the generated clocks in the design. Felt tough in clearing timing violations during
routing stage.

PROJECT 2: RPTOP_TOP

Technology : TSMC 28nm


Layers : 9 layers
Tools : ICC2_Shell, DC_Shell

Frequency : 400 MHZ


No. of Clocks : 1
Macros Count : 6

Challenges : Faced trouble while fixing the congestion issues after placement stage.
Overcame the timing issues during routing.
PROJECT 3: REG2REG

Technology : TSMC 28nm

Tools : DC_Shell, ICC2_Shell


Frequency : 100 MHZ
No. of Clocks : 1

Description : Completed with Sanity checks and fixed Setup violations.

Challenges : Performed synthesis flow by resolving issues during check timing, report
timing and check design.

ACHIEVEMENTS

 Certified by CADENCE - Basic Static Timing Analysis

 Certified by CADENCE - Received a badge by Cadence Design

PERSONAL DETAILS
● Date of birth : 17/02/2001

● Permanent Address : 4-133, Pallepalem (Mutthayapalem ) Bapatla Disct.


Andhra Pradhesh , 522101
● Hobbies : Listening music, Travelling
● Nationality : Indian

● Languages known : English, Hindi, Telugu


● Any disability : No

● Willingness to relocate : Yes

DECLARATION

I hereby declare that all the above-mentioned information is true and correct to the best of my knowledge.

PLACE : Bangalore
DATE :
SIGNATURE:

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