Scribd
Upload
37 views3 pages

Week 1 Application Assignment

The document outlines a digital design assignment focusing on a 2-bit full adder and its implementation using logic gates. It provides equations for calculating the sum and carry outputs, along with a schematic explanation of how the full adders are constructed. Additionally, it discusses the implementation of a specific logical equation using a Programmable Logic Array (PLA).

Uploaded by

Zayne Monib
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
37 views3 pages

Week 1 Application Assignment

The document outlines a digital design assignment focusing on a 2-bit full adder and its implementation using logic gates. It provides equations for calculating the sum and carry outputs, along with a schematic explanation of how the full adders are constructed. Additionally, it discusses the implementation of a specific logical equation using a Programmable Logic Array (PLA).

Uploaded by

Zayne Monib
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

Mission 001: Week 1 Application Assignement

Proposé et réalisé par Mounib Esghayri

Digital Design Assignment Solutions

1. 2-Bit Full Adder with Carry

For a 2-bit full adder, we need to compute:

 S0 (sum of least significant bits)

 S1 (sum of most significant bits with carry from S0)

 Co (final carry out)

The equations are:

S0 = A0 ⊕ B0 ⊕ Ci

C1 (carry from first bit) = (A0 AND B0) OR (A0 AND Ci) OR (B0 AND Ci)

S1 = A1 ⊕ B1 ⊕ C1

Co = (A1 AND B1) OR (A1 AND C1) OR (B1 AND C1)

Schematic Explanation

The schematic would consist of:


 A full adder for the LSB (A0, B0, Ci) producing S0 and C1

 A full adder for the MSB (A1, B1, C1) producing S1 and Co

Each full adder would be constructed from:

3 XOR gates for the sum output

3 AND gates and 1 OR gate for the carry output

PLA Implementation of (A AND NOT(B)) OR (C AND NOT(D)

Design Explanation

The given equation F = (A & ¬B) | (C & ¬D) can be implemented in a PLA by:

Creating product terms for (A AND ¬B) and (C AND ¬D)

OR-ing these product terms together

PLA Fuse Pattern

For a PLA with inputs A, B, C, D and their complements:

AND Plane:

Product term 1: (A AND ¬B) - connect to A and ¬B

Product term 2: (C AND ¬D) - connect to C and ¬D

OR Plane:

Connect both product terms to the output F


LUT Contents

For a 4-input LUT (A, B, C, D), the truth table would be:

You might also like