MMU/F/ENG/007
MULTIMEDIA UNIVERSITY OF KENYA
FACULTY OF ENGINEERING & TECHNOLOGY
DEPARTMENT OF ELECTRICAL & COMMUNICATIONS
ENGINEERING
COURSE OUTLINE
Part I: General Information
Name of Lecturer: Kipyegon Edwin Koech
Office Location: Chairman of ECE, office
Consultation Time: Mondays (1000 hrs – 1300hrs)
Mobile Number: 0722-109886 E-mail:
[email protected] or
[email protected]Programme Name: Bsc in Electrical and Telecommunication Engineering
Academic year: 2024/2025 Semester: Feb. - May 2024
Part II: Course Information
Course Name: ECE 2223 DIGITAL ELECTRONICS I
Prerequisite
ECE 2215 Electrical Circuit Analysis I
Purpose
To enable the student to understand the fundamental principles of digital circuits and
analysis.
Learning Outcomes
At the end of this course, the student should be able to: -
1. Explain the different types of number systems, codes and their applications.
2. Optimize logic functions using Boolean algebra, K-maps and the Quine-McCluskey
algorithm.
3. Draw and describe the implementation of logic gates using electronic components
4. Design the basic combinational and sequential logic circuits
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MMU/F/ENG/007
Course Outline/Schedule
Week 1-2: Number systems and Codes
▪ decimal and binary and their conversions to each other
▪ hexadecimal and octal: conversion between the four number systems
▪ binary arithmetic
Week 3 Number systems and Codes
▪ Codes: BCD, Excess-3 and gray codes, alphanumeric.
▪ Application of various codes.
▪ ASSIGNMENT I
Week 4 -5: Elements of logic circuits (Logic gates):
▪ basic and derived gates (AND, OR, NOT, NOR, NAND, EX-OR and EX-NOR),
▪ logic symbols, truth table, logic functions and operations.
▪ Electronic realization of logic values and gates.
▪ CAT 1
Week 6 -7: Combinational logic circuits
▪ Boolean algebra: Boolean expressions, axioms and postulates of Boolean algebra.
▪ Minimization of Boolean expressions: Venn diagrams, laws and theorems, Karnaugh
maps, and application of Boolean algebra to logic circuits.
▪ Lab session 1: Verification of logic gates and properties
▪ ASSIGNMENT 2
Week 8 -10: Combinational logic circuit design
▪ Practical design and implementation of combinational logic circuits using selected
standard integrated circuits (adders, subtractors, encoders, decoders, multiplexers and
demultiplexers).
▪ Lab session 2: Sum of products method logic design and Combination Logic (SOP
and POS
▪ CAT 2
▪ ASSIGNMENT II
Week 11-12: Sequential circuits
▪ S-R latch and Flip-Flops such as S-R, J-K, D and T and their electronic realization.
▪ Lab session 3: Circuit Minimization Using K-maps and the RS Flip Flops
▪ CAT 3
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MMU/F/ENG/007
Prescribed Textbooks:
1. M. Morris Mano, Michael D. Ciletti, (2023), Digital Design: With an Introduction to the
Verilog HDL, VHDL, and SystemVerilog, Pearson, 6th edition. ISBN-13: 978-
0138223190.
2. R. P. Jain, (2019), Modern Digital Electronics, McGraw-Hill Education, 4th edition.
ISBN-13: 978-9353165275.
3. Arijit Saha, N. Manna, (2022), Digital Principles and Logic Design, Jones & Bartlett
Learning, 2nd edition. ISBN-13: 978-1284270902
References:
1. Ronald J. Tocci, Neal S. Widmer, Gregory L. Moss, (2021), Digital Systems: Principles
and Applications, Pearson, 12th edition. ISBN-13: 978-0134220130.
2. Thomas L. Floyd, (2022), Digital Fundamentals, Pearson, 12th edition. ISBN-13: 978-
0137584545
3. Roger L. Tokheim, (2021), Digital Electronics: Principles and Applications, McGraw-
Hill, 9th edition. ISBN-13: 978-1260597815
Teaching Methodology
▪ The course will be conducted through lectures and tutorials for 6 hours per week for the
first four weeks of the semester. From the fifth to fourteenth week, three hours will be
allocated to laboratory sessions on a rotational basis and the other three hours per week
will be for lectures and tutorials.
▪ The lectures and tutorials will be conducted in LR 2, and laboratory exercises will be
conducted in Digital Electronics Lab.
CoD Signature: Date: 04/02/2024
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