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SIPO Shift Register VHDL

This document details the VHDL implementation of a Serial Input Parallel Output (SIPO) shift register, which converts serial data input into parallel data output. It includes the VHDL code for the SIPO entity, its behavioral architecture, and a testbench for simulation. The shift register utilizes a clock input for data shifting and an asynchronous reset for clearing the register.

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Diaa Abossrie
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96 views3 pages

SIPO Shift Register VHDL

This document details the VHDL implementation of a Serial Input Parallel Output (SIPO) shift register, which converts serial data input into parallel data output. It includes the VHDL code for the SIPO entity, its behavioral architecture, and a testbench for simulation. The shift register utilizes a clock input for data shifting and an asynchronous reset for clearing the register.

Uploaded by

Diaa Abossrie
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Serial Input Parallel Output Shift Register (SIPO) - VHDL Implementation

Introduction
A Serial Input Parallel Output (SIPO) shift register is a sequential circuit that accepts serial
data input and converts it into parallel data output.
This document provides the VHDL implementation of an n-bit SIPO shift register along with
a brief explanation of its working.

VHDL Code

-- VHDL Code for Serial Input Parallel Output Shift Register


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SIPO is
Generic ( N : integer := 8 ); -- Number of bits
Port ( CLK : in STD_LOGIC; -- Clock input
RST : in STD_LOGIC; -- Reset input (active high)
SI : in STD_LOGIC; -- Serial input
PO : out STD_LOGIC_VECTOR (N-1 downto 0) -- Parallel output
);
end SIPO;

architecture Behavioral of SIPO is


signal shift_reg : STD_LOGIC_VECTOR (N-1 downto 0) := (others => '0');
begin

process(CLK, RST)
begin
if RST = '1' then
shift_reg <= (others => '0');
elsif rising_edge(CLK) then
shift_reg <= SI & shift_reg(N-1 downto 1);
end if;
end process;

PO <= shift_reg;

end Behavioral;
Explanation
1. The shift register is implemented using an N-bit signal `shift_reg`.
2. The input serial data (`SI`) is shifted into the register on each rising edge of the clock
(`CLK`).
3. The parallel output (`PO`) reflects the contents of the register.
4. An asynchronous reset (`RST`) is used to clear the register when active.

Testbench

-- Testbench for SIPO


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SIPO_TB is
end SIPO_TB;

architecture Behavioral of SIPO_TB is


constant N : integer := 8;
signal CLK : STD_LOGIC := '0';
signal RST : STD_LOGIC := '0';
signal SI : STD_LOGIC := '0';
signal PO : STD_LOGIC_VECTOR (N-1 downto 0);

component SIPO is
Generic ( N : integer );
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
SI : in STD_LOGIC;
PO : out STD_LOGIC_VECTOR (N-1 downto 0)
);
end component;

begin
uut: SIPO
Generic map ( N => N )
Port map ( CLK => CLK, RST => RST, SI => SI, PO => PO );

-- Clock generation
process
begin
while True loop
CLK <= '0';
wait for 10 ns;
CLK <= '1';
wait for 10 ns;
end loop;
end process;

-- Test process
process
begin
-- Reset
RST <= '1';
wait for 20 ns;
RST <= '0';

-- Apply serial input


for i in 0 to N-1 loop
SI <= '1';
wait for 20 ns;
end loop;
SI <= '0';
wait;
end process;

end Behavioral;

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