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Two-Stage Amplifier Design Analysis

The assignment involves designing a two-stage amplifier using a 180nm CMOS process with specific performance specifications, including a DC Gain of 60 dB and a unity gain bandwidth of 1 GHz. It requires deriving the transfer function, estimating compensation capacitors, and verifying results through simulation. Additionally, a closed loop amplifier design is to be created, with similar analysis and simulation verification required for its performance metrics.

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44 views2 pages

Two-Stage Amplifier Design Analysis

The assignment involves designing a two-stage amplifier using a 180nm CMOS process with specific performance specifications, including a DC Gain of 60 dB and a unity gain bandwidth of 1 GHz. It requires deriving the transfer function, estimating compensation capacitors, and verifying results through simulation. Additionally, a closed loop amplifier design is to be created, with similar analysis and simulation verification required for its performance metrics.

Uploaded by

itzabhay
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

Assignment: #5

PROBLEM 1. Two-Stage Amplifier and Compensation

Using the database generated in Assignment #2 for 180nm CMOS process, design a two-stage
amplifier with the following specifications: DC Gain = 60 dB, open loop unity gain bandwidth
= 1 GHz, CL = 5 pF, and Phase margin ≥ 70◦ . Schematic diagram of the amplifier with Miller
and Ahuja compensations are shown in Figure 1 and Figure 2, respectively. Bias MOSFETs with
overdrive voltage (∆) for optimum speed and power gain i.e., for maximum gm/Id × fT .

(a) Derive the transfer function υ out (s)/υ in (s) and evaluate DC Gain, poles, and zeroes using
dominant parasitic capacitors for MOSFETs.

(b) Estimate minimum capacitor required for both Miller and Ahuja compensation schemes
to achieve the desired performance.

(c) Verify the results in simulation. Plot the input-to-output AC response and clearly indicate
the DC Gain, unity gain bandwidth and phase margin.

(d) Sweep DC input across bias voltage and plot DC output voltage. Check for DC gain across
the input voltage.

EE5320: Analog Integrated Circuit Design 1 May-Aug. 2022


PROBLEM 2. Closed loop analysis
Make use of the amplifier in Figure 2 to design the closed loop amplifier as shown in Figure
3. You can either use a VCVS in the feedback loop to enforce negative feedback or a differential
input with single ended output if required. Use appropriate common mode bias voltages. Cin is
the parasitic capacitance due to input MOSFET. Use CL = 5pF, CS = 1pF, CF = 1pF. Ignore
the CL in Figure 2.

(a) Derive the closed loop transfer function υ out(s)/υ in (s) and evaluate DC Gain, poles, and
zeroes using dominant parasitic capacitors for MOSFETs.

(b) Verify the results in simulation. Plot the AC response of the closed loop amplifier and
clearly indicate the DC Gain and -3dB bandwidth.

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