I/O Architecture

I/O interfacing

Interconnection between the CPU and the I/O Devices is known as I/O Interfacing

Address space of CPU 0000 − 1111

Address range calculation

RAM ROM I/O 1 I/O 2

𝐴3 𝐴2 𝐴1 𝐴0 𝐴3 𝐴2 𝐴1 𝐴0 𝐴3 𝐴2 𝐴1 𝐴0 𝐴3 𝐴2 𝐴1 𝐴0
0 0 0 0 0 1 0 0 1 0 X X 1 1 X X
0 0 0 1 0 1 0 1
0 0 1 0 0 1 1 0
0 0 1 1 0 1 1 1

0000 − 0011 {0100 − 0111} 1000 − 1011 1100 − 1111

Memory mapped I/O

When the memory and I/O devices are connected with the CPU
such that the address space for memory and address space for
I/O are disjoint then it is referred as Memory mapped I/O.
An address cannot be simultaneously be memory address as well
as I/O address.

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Address space of CPU {0000 − 1111}

Address range calculation

RAM ROM I/O 1 I/O 2

𝐴3 𝐴2 𝐴1 𝐴0 𝐴3 𝐴2 𝐴1 𝐴0 𝐴3 𝐴2 𝐴1 𝐴0 𝐴3 𝐴2 𝐴1 𝐴0
0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1
0 0 0 1 1 0 0 1
0 ... ... ... 1 ... ... ...
0 1 1 1 1 1 1 1

0000 − 0011 {0100 − 0111} 0000 1111

Note: Since, a 4 × 16 Decoder output determines the I/O device therefore the maximum number of I/O devices
that can be interfaced to the system 24

Since, an address can be both a memory address as well as an I/O address therefore if both are selected then
whenever CPU wants to perform a read operation then data from RAM and I/O both will come to data bus
resulting in data collision.

To resolve data collision problem another control line 𝐼𝑂/𝑀is connected with the CPU.

If 𝐼𝑂/𝑀 =1 then it is a I/O address, If 𝐼𝑂/𝑀 = 0 then it is an memory address

I/O mapped I/O

When the memory and I/O devices are connected with the CPU
such that the same address space can be used both for memory
and for I/O then it is referred as I/O mapped I/O.

An address can be simultaneously be memory address as well as

I/O address.

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Data Transfer between CPU and I/O

Data transfer between the CPU and I/O devices can be done in two ways: Programmed I/O and Interrupt driven I/O

1. Programmed I/O
Here, CPU periodically will knock the I/O devices to check whether an I/O device has to send data or not. Data
transfer through this mode requires constant monitoring of the peripheral device by the CPU and also monitor
the possibility of new transfer once the transfer has been initiated. Thus CPU stays in a loop until the I/O device
indicates that it is ready for data transfer. Thus programmed I/O is a time consuming process that keeps
the processor busy needlessly and leads to wastage of the CPU cycles.
Advantage:
o Provides simple and easy interfaces to programs.
o Direct access to interact with the CPU without involving any peripheral devices in the process.
Disadvantage:
o Synchronization is not efficient in terms of the CPU time as it will need to loop waiting for the device to
be ready.
o The CPU is idle and cannot handle any other task at the time it waits for the I/O device to complete
processing.

2. Interrupt driven I/O

Here, CPU will not periodically check for data from any I/O device. This mode uses an interrupt facility and
special commands to inform the interface to issue the interrupt command when data becomes available and
interface is ready for the data transfer. CPU keeps on executing processes and need not check for data from
I/O. When the flag is set, the interface is informed and an interrupt is initiated. This interrupt causes the CPU
to suspend from what it is doing so that it can respond to the I/O transfer. The CPU responds to the signal by
storing the return address from the program counter (PC) into the memory stack and then branches to
service that processes the I/O request. After the transfer is complete, CPU returns to the previous task it was
executing.
Advantage:
o Reduced overhead on the CPU as the same CPU waits for an interrupt while doing other tasks at the
same instance.
o There is also no need for monitoring the status of a specific device.
o Reduces CPU time wastage, hence enhancing the performance of the system.
Disadvantage:
o Difficult to implement and program in contrast to sequential file processing or compared to it when
it is implemented in low-level languages.
o Needs interrupt handling routines, which can be time-consuming.
o When multiple I/O devices sends interrupt simultaneously, CPU has to schedule / order the way in
which I/O devices are going be services. This is done a set of mechanisms known as Bus arbitration.

Programmed I/O Interrupt Initiated I/O

Data transfer is initiated by the means of instructions The I/O transfer is initiated by the interrupt
stored in the computer program. Whenever there is command issued to the CPU.
a request for I/O transfer the instructions are
executed from the program.
The CPU stays in the loop to know if the device is There is no need for the CPU to stay in the loop as
ready for transfer and has to continuously monitor the interrupt command interrupts the CPU when
the peripheral device. the device is ready for data transfer.
This leads to the wastage of CPU cycles as CPU The CPU cycles are not wasted as CPU continues
remains busy needlessly and thus the efficiency of with other work during this time and hence this
system gets reduced. method is more efficient.
CPU cannot do any work until the transfer is CPU can do any other work until it is interrupted
complete as it has to stay in the loop to continuously by the command indicating the readiness of
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 monitor the peripheral device. device for data transfer
Its module is treated as a slow module. Its module is faster than programmed I/O module.
It is quite easy to program and understand. It can be tricky and complicated to understand if
one uses low level language.
The performance of the system is severely degraded. The performance of the system is enhanced to
some extent.

Bus Arbitration
It is a set of procedures through which CPU schedules the I/O devices for data transfer. It can done as follows:
1. Daisy chaining
Here whenever an I/O device has to send data it will check whether the BUSY line is set or not. If the BUSY line
is not set then it will send the signal to the CPU by setting REQUEST line 1. If the CPU is communicating with any
I/O device then BUSY line will be set to 1 else 0. Upon receiving a signal from an I/O device CPU will grant
permission to the device by setting GRANT line 1.

How does it work?

Consider, data has arrived at I/O 2 and it has to send data to CPU. It will first check whether BUSY is set to 1 or
0. If BUSY is 1 it will wait. If BUSY is 0 then it will send a signal to CPU by making REQUEST = 1. When CPU
received the signal it will stop executing the current process, set BUSY to 1 and issue grant permission by
making GRANT = 1. GRANT will first be issued to I/O 1. As I/O 1 does not have any data to send it will pass
GRANT to I/O 2. I/O 2 will block GRANT, send data to CPU. Once data transmission gets over, I/O 2 release
GRANT to I/O 3, I/O 3 will pass to I/O 4 and so on. When no other I/O device sends data BUSY, REQUEST,
GRANT all are reset.
The same procedure will take place when multiple I/O device is willing to send data to CPU.
Advantage:
Interconnection is easy. only three extra line (GRANT, BUSY, REQUEST) are needed.
Disadvantage:
When an intermediate I/O device breaks down the next I/O devices will not be able to send data (as GRANT
will not be passed). We won't be able to set priorities to I/O devices.

2. Polling
Here, GRANT line is not cascaded, rather for N I/O devices log 2 𝑁 GRANT lines are used and all are connected
to all the I/O devices. Each of the I/O devices are numbered in some way. CPU will issue those numbers in some
arbitrary sequence through the GRANT lines. The I/O device with the number equal with the number generated
by the CPU (through the GRANT lines) will be selected.
How does it work?
Consider there are 8 I/O devices marked as I/O 0, I/O 1, ..., I/O 7. If the sequence generated by the CPU is 0, 5,
7, 2, 1, 3, 6, 4 then first GRANT lines will be 000 and I/O 0 will be able to send data, then GRANT will be 101 and

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 I/O 5 will be able to send data and so on. The pre-defined sequence used by the CPU is known as Polling
sequence. This sequence can be changed through program.

Advantage:
o Polling resolved the disadvantages of Daisy chaining.
Disadvantages:
o Interconnection is difficult as it would require 2 + log 2 𝑁 additional lines.

3. Independent Request
As there was only one REQUEST line in both daisy chaining and polling therefore CPU could not make out which
I/O device has sent a request. Thus CPU tries to GRANT access to all the devices.
For this separate REQUEST lines and GRANT lines are used for the different I/O devices. For setting priorities
priority encoders are used.

Although it resolves all the issues with the earlier methods but here interconnection is too complex as it would
require (2N + 1) additional connections are used.

Data Transfer between Memory and I/O

Direct Memory Access (DMA)

Consider the case where I/O device is willing to send/ receive data to/ from memory. In case of programmed I/O or
interrupt driven I/O, I/O device has to send data to CPU then CPU has to send data to memory. As I/O and memory
are connected with Address bus, Data bus and Control bus therefore if we can transfer data between I/O and
memory without passing through CPU then it would be referred to as Direct Memory Access (DMA). As CPU is not
involved therefore to control and coordinate the buses we need to have an extra circuit for this. This is known as
DMA controller.

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There are many variations of DMA. We will consider two of them: block transfer DMA and cycle stealing DMA.

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