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VHDL ROM Implementation Details

The document describes two hardware components: a RAM and a ROM implemented in VHDL. The RAM allows for data input and output based on control signals and an address range of 0 to 15, while the ROM outputs predefined data based on the same address range. Both components utilize standard logic libraries for their operations.

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0% found this document useful (0 votes)

35 views3 pages

VHDL ROM Implementation Details

Uploaded by

ravi434

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as DOCX, PDF, TXT or read online on Scribd

RAM

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity RAM_G is

Port ( Address : in Integer range 0 to 15;

CE,WE,OE : in STD_LOGIC;

datain : in STD_LOGIC_VECTOR (7 downto 0);

dataout : out STD_LOGIC_VECTOR (7 downto 0));

end entity RAM_G;

architecture Behavioral of RAM_G is

begin

PROCESS(Address,CE,WE,OE)

TYPE Ram_Array IS ARRAY (0 to 15) OF STD_LOGIC_VECTOR(7 downto 0);

VARIABLE Mem: Ram_Array;

BEGIN

dataout(7 downto 0) <= (others => 'Z');

IF (CE='0') THEN

IF (WE = '0') THEN

Mem(Address) := datain(7 downto 0);

ELSIF(OE='0') THEN
dataout(7 downto 0) <= Mem(Address);

END IF;

END PROCESS;

end Behavioral;

ROM

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

ENTITY ROM is

Port ( Address : IN INTEGER Range 0 to 15;

Data : OUT STD_LOGIC_VECTOR(7 downto 0));

END ENTITY ROM;

ARCHITECTURE Behavioural of ROM is

TYPE Rom_Array IS Array (0 to 15) of STD_LOGIC_VECTOR(7 downto 0);

CONSTANT ROM: Rom_Array := (

"11000000",

"00010011",

"00100000",

"00110000",

"01000000",

"01010000",

"01100000",
"01110000",

"10000000",

"10011000",

"10100000",

"10110000",

"11000000",

"11010000",

"11100011",

"11111111");

BEGIN

Data <= Rom(Address);

END ARCHITECTURE Behavioural;

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VHDL ROM Implementation Details

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VHDL ROM Implementation Details

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RAM

Port ( Address : in Integer range 0 to 15;

datain : in STD_LOGIC_VECTOR (7 downto 0);

dataout : out STD_LOGIC_VECTOR (7 downto 0));

end entity RAM_G;

architecture Behavioral of RAM_G is

TYPE Ram_Array IS ARRAY (0 to 15) OF STD_LOGIC_VECTOR(7 downto 0);

VARIABLE Mem: Ram_Array;

dataout(7 downto 0) <= (others => 'Z');

IF (WE = '0') THEN

Mem(Address) := datain(7 downto 0);

Port ( Address : IN INTEGER Range 0 to 15;

Data : OUT STD_LOGIC_VECTOR(7 downto 0));

END ENTITY ROM;

ARCHITECTURE Behavioural of ROM is

TYPE Rom_Array IS Array (0 to 15) of STD_LOGIC_VECTOR(7 downto 0);

CONSTANT ROM: Rom_Array := (

Data <= Rom(Address);

END ARCHITECTURE Behavioural;

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