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 DATA SHEET
www.onsemi.com

Wired M-BUS Slave

Transceiver
NCN5150 QFN20
MN SUFFIX
SOIC−16
D SUFFIX
CASE 485E CASE 751B
Description
The NCN5150 is a single-chip integrated slave transceiver for use in
MARKING DIAGRAMS
two-wire Meter Bus (M-BUS) slave devices and repeaters. The
transceiver provides all of the functions needed to satisfy the 20
European Standards EN 13757−2 and EN 1434−3 describing the 1
NCN
physical layer requirements for M-BUS. It includes a programmable 5150
power level of up to 2 (SOIC version) or 6 (QFN version) unit loads, ALYW
G
which are available for use in external circuits through a 3.3 V LDO
regulator. QFN20, 4x4
The NCN5150 can provide communication up to the maximum
16
M-BUS communication speed of 38,400 baud (half-duplex).
NCN5150
Features AWLYWWG
• Single-chip MBUS Transceiver 1
• UART Communication Speeds Up to 38,400 baud SOIC−16
• Integrated 3.3 V VDD LDO Regulator with Extended Peak Current
Capability of 15 mA A = Assembly Location
L, WL = Wafer Lot (optional)
• Supports Powering Slave Device from the Bus or from External Y = Year
Power Supply W, WW = Work Week
• Adjustable I/O Levels G or G = Pb-free Package

• Adjustable Constant Current Sink up to 2 or 6 Unit Loads Depending

on the Package
ORDERING INFORMATION
• Low Bus Voltage Operation See detailed ordering and shipping information in the package
• Extended Current Budget for External Circuits: at least 0.88 mA dimensions section on page 11 of this data sheet.

• Polarity Independent NOTE: Some of the devices on this data sheet have been
DISCONTINUED. Please refer to the table on page 11.
• Power-Fail Function
• Fast Startup − No External Transistor Required on STC Pin
• Industrial Ambient Temperature Range of −40°C to +85°C
• Available in:
♦ 16-pin SOIC (Pin-to-Pin Compatible with TSS721A)
♦ 20-pin QFN
• These are Pb-free Devices

Typical Applications
• Multi-energy Utility Meters
♦ Water
♦ Gas
♦ Electricity
♦ Heating systems

Related Standards − European Standard

EN 13757−2, EN 1434−3
For more information visit www.m-bus.com

© Semiconductor Components Industries, LLC, 2015 1 Publication Order Number:

August, 2024 − Rev. 6 NCN5150/D
 NCN5150

BUSL2 1 16 BUSL1

VDD
RIS

RXI

RX
20 19 18 17 16 VB 2 15 GND

GND 1 15 STC 3 14 RIS

BUSL1 2 14 VS
RIDD 4 13 RXI
NCN5150 NCN5150
BUSL2 3 13 VIO
QFN20 SOIC16
PFb 5 12 RX
VB 4 12 TX

5 11 TXI SC 6 11 VDD

6 7 8 9 10 TXI 7 10 VS
STC

RIDD

PFb

SC
TX 8 9 VIO

Figure 1. Pin Out NCN5150 in 20-pin NQFP and 16 Pin SOIC (Top View)

Table 1. NCN5150 PINOUT

Pin Number
Signal Name Type NCN5150 SOIC NCN5150 QFN Pin Description
BUSL1 Bus 16 2 MBUS line. Connect to bus through 220 W series resistors.
Connections are polarity independent
BUSL2 Bus 1 3
VB Power 2 4 Rectified bus voltage
STC Output 3 6 Storage capacitor pin. Connect to bulk storage capacitor
(minimum 10 mF, maximum 330 mF−2,700 mF − see Table 9)
RIDD Input 4 7 Mark current adjustment pin.
Connect to programming resistor
PFb Output 5 8 Power Fail, active low
SC Output 6 9 Mark bus voltage level storage capacitor pin.
Connect to ceramic capacitor (typically 220 nF)
TXI Output 7 11 UART Data output (inverted)
TX Output 8 12 UART Data output
VIO Input 9 13 I/O pins (RX, RXI, TX, TXI, PFb) high level voltage
VS Output 10 14 Gate driver for PMOS switch between bus powered operation
and external power supply
VDD Power 11 16 Voltage regulator output.
Connect to minimum 1 mF decoupling capacitor
RX Input 12 17 UART Data input
RXI Input 13 18 UART Data input (inverted)
RIS Input 14 20 Modulation current adjustment pin
GND Ground 15 1 Ground
NC NC − 5, 10, 15, 19 Not connected pins. Tie to GND
EP Ground − EP Exposed Pad. Tie to GND

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 NCN5150

PFb

VIO_BUF Power VB_INT

VIO
VIO Fail BUSL1
Buffer
Detect

VB
CS1

BUSL2
RIDD
SC
VIO_BUF
STC

Receiver TX
STC
VS
VS Voltage
Driver
Monitor TXI
ECHO

RXI

3.3 V STC
VDD Transmitter RX
LDO Clamp
CS_TX

Thermal
POR
Shutdown

NCN5150 RIS

GND

Figure 2. NCN5150 Block Diagram

Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1)

Symbol Parameter Min Max Unit
TJ Junction Temperature −40 +150 °C
TS Storage Temperature −55 +150 °C
VBUS Bus Voltage (|BUSL1 − BUSL2|) −50 50 V
VTX, VTXI Voltage on Pin TX, TXI −0.3 7.5 V
VRX, VRXI, VIO Voltage on Pin RX, RXI, VIO −0.3 5.5 V
ESDHBM ESD Rating − Human Body Model 4.0 − kV
ESDMM ESD Rating − Machine Model 250 − V
ESDCDM ESD Rating − Charged Device Model 750 − V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All voltages are referenced to GND.

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 NCN5150

Table 3. THERMAL CHARACTERISTICS

Rating Symbol Typical Value Unit
Thermal Characteristics, SOIC−16 − Thermal Resistance, Junction-to-Air RθJA 125 °C/W
Thermal Characteristics, QFN20 − Thermal Resistance, Junction-to-Air RθJA 42 °C/W
NOTE: RqJA obtained with 1S0P (SOIC) or 2S2P (QFN) test boards according to JEDEC JESD51 standard.

Table 4. RECOMMENDED OPERATING CONDITIONS (Notes 2 and 3)

Symbol Parameter Min Max Unit
TA Ambient Temperature −40 +85 °C
VBUS Bus Voltage (|VBUSL1 − VBUS2|) 1−2 Unit Loads 9.2 42 V
3−6 Unit Loads 9.7 42 V
VIO VIO Pin Voltage (Note 4) 2.5 3.8 V
2. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
3. All voltages are referenced to GND.
4. VSTC must be at least 1V higher than VIO for proper operation.

Table 5. ELECTRICAL CHARACTERISTICS (Note 5)

Symbol Parameter Min Typ Max Unit
DVBR Voltage drop over bus rectifier (VBUS − VB) (RIDD (Note 6) = 4.02 kW) − − 1.25 V
DVCS Voltage drop over CS1 RIDD (Note 6) ≥ 13 kW 1.30 − − V
(VB − VSTC)
RIDD (Note 6) ≤ 4.02 kW 1.70 − −
IBUS Total Current Drawn from the Bus, Mark RIDD (Note 6) = 30 kW − 1.32 1.50 mA
State
RIDD (Note 6) = 13 kW − 2.71 3.00
RIDD (Note 6, 7) = 8.45 kW − 4.10 4.50
RIDD (Note 6, 7) = 6.19 kW − 5.50 6.00
RIDD (Note 6, 7) = 4.87 kW − 6.80 7.50
RIDD (Note 6, 7) = 4.02 kW − 8.22 9.00
DIBUS Bus Current Stability (over DVBUS = 10 V, RX/RXI = mark) − 0.2 2 %
ISTC Idle Current Available for the Application RIDD (Note 6) = 30 kW 0.88 1.05 1.20 mA
to Draw from STC and VDD (Including
Current Drawn from IO Pins) RIDD (Note 6) = 13 kW 2.10 2.35 2.60
RIDD (Note 6, 7) = 8.45 kW 3.10 3.60 4.00
RIDD (Note 6, 7) = 6.19 kW 4.20 4.80 5.40
RIDD (Note 6, 7) = 4.87 kW 5.30 6.10 6.90
RIDD (Note 6, 7) = 4.02 kW 6.50 7.45 8.40
DISTC, space Additional Current Available for the Application when Transmitting a − 200 − mA
Space
ICC Internal Supply Current (RIDD (Note 6) = 13 kW, RX/RXI = mark) − 359 500 mA
IIO Current Drawn by the VIO Pin −0.5 − 0.5 mA
VSTC, clamp Clamp Voltage on Pin STC (IDD < ISTC) 6.0 6.5 7.0 V
VB, PFb Threshold Voltage on VB to Trigger PFb (Note 8) VSTC + 0.3 − VSTC + 0.8 V
VPFb, OH PFb Voltage High (IPFb = −100 mA) VIO − 0.6 − VIO V
VPFb, OL PFb Voltage Low (Note 9) (IPFb = 50 mA) 0 − 0.6 V
VRIDD Voltage on RIDD Pin 1.15 1.20 1.25 V
VVS, OH Voltage on VS during High State VSTC − 0.4 − VSTC V
(VSTC > VSTC, VDD ON, IVS = −5 mA)
RVS, PD Pull-down Resistor on VS during Low State 50 100 150 kW
(VDD > 2 V, VSTC > VS)
5. All voltages are referenced to GND.
6. Resistor with 1% accuracy.
7. Only possible in NQFP variant.
8. PFb comparator has a 70 mV hysteresis.
9. PFb pin is pulled down with an on-chip resistor of typically 2 MW.

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 NCN5150

Table 6. VDD REGULATOR ELECTRICAL CHARACTERISTICS (Note 10)

Symbol Parameter Min Typ Max Unit
VDD Voltage on VDD (Note 11 ) (IDD < 15 mA) 3.1 3.3 3.6 V
IDD Peak Current that can be Supplied by VDD (Note 12) 15 − − mA
IDD, OFF VBUS = 0 V, VSTC = 0 V −0.5 − 0.5 mA
VPOR, ON Power-on Reset Threshold, Release 2.65 2.85 3.15 V
VPOR, OFF Power-on Reset Threshold, Reset 2.55 2.75 3.00 V
VSTC, VDD ON Threshold Voltage on Pin STC to Turn On VDD Regulator, Pull 5.6 6.0 6.4 V
the VS Pin High and Enable the PF Function
VSTC, VDD OFF Threshold Voltage on Pin STC to Turn Off VDD Regulator and 3.7 4.0 4.3 V
Pull the PFb and VS Pins Low
10. All voltages are referenced to GND.
11. Including output resistance of VDD.
12. Average current draw limited by ISTC.

Table 7. RECEIVER ELECTRICAL CHARACTERISTICS (Note 13)

Symbol Parameter Min Typ Max Unit
VT Receiver Threshold Voltage VSC − 8.2 − VSC − 5.7 V
VSC Mark Level Storage Capacitor Voltage − − VB V
ISC, charge Mark Level Storage Capacitor Charge Current −40 −25 −15 mA
ISC, discharge Mark Level Storage Capacitor Discharge Current 0.3 0.6 −0.033 × mA
ISC, charge
CDR Charge/Discharge Current Ratio 30 40 −
VTX, OH, TX/TXI High-level Voltage (ITX/ITXI = −100 mA) (Note 14) VIO − 0.6 − VIO V
VTXI, OH
VTX, OL, TX/TXI Low-level Voltage (ITX/ITXI = 100 mA) 0 − 0.35 V
VTXI, OL
(ITX = 1.1 mA) 0 − 1.5 V
ITX, ITXI VTX = 7.5 V, VSTC = 6 V 0 − 16 mA
13. All voltages are referenced to GND.
14. VSTC must be at least 1 V higher than VIO for proper operation.

Table 8. TRANSMITTER ELECTRICAL CHARACTERISTICS (Note 15)

Symbol Parameter Min Typ Max Unit
IMC Space Level Modulating Current (RRIS = 100 W (Note 16)) 12.5 15.0 18.0 mA
VRIS Voltage on RIS Pin 1.2 1.4 1.6 V
VRX, IH, VRXI, IH RX/RXI Input High VIO − 0.8 − 5.5 V
VRX, IL, VRXI, IL RX/RXI Input Low 0 − 0.8 V
IRX, IRXI Current Drawn or Sourced from RX/RXI Pins (Note 17) ±6 − ±30 mA
(VIO = 3 V)
15. All voltages are referenced to GND.
16. Resistor with 1% accuracy.
17. Including internal pull-up resistor on RX and internal pull-down resistor on RXI.

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 NCN5150

APPLICATION SCHEMATICS

VS
VIO
VDD
RBUS1
CVDD BUSL2
U1
TXI NCN5150 VB TVS1 MBUS
TX
BUSL1
RX RBUS2
mC RXI
PFb

RIS SC GND RIDD STC

RIS CSC RIDD CSTC

Figure 3. General Application Schematic

VS
VIO
VDD
CVDD RBUS1
BUSL2
U1
TXI NCN5150 VB TVS1 MBUS
TX
BUSL1
RX
mC RXI
RBUS2

PFb

RIS SC GND RIDD STC

RIS CSC RIDD CSTC

Figure 4. Application Schematic with External Power Supply (Battery)

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 NCN5150

APPLICATION SCHEMATICS

Q1 VS
VIO
VDD
RBUS1
CVDD
BUSL2
U1
TXI NCN5150 VB TVS1 MBUS
TX
BUSL1
RX
mC RXI
RBUS2

PFb

RIS SC GND RIDD STC

RIS CSC RIDD CSTC

Figure 5. Application Schematic with Backup External Power Supply

VSTC VS
VIO
15 kW 2.2 kW
VDD
RBUS1
CVDD
15 kW BUSL2
U1
TXI NCN5150 VB TVS1 MBUS
U3 TX
BUSL1
RX
RBUS2
RXI
PFb
U2
mC 620 W
RIS SC GND RIDD STC

V STC
RIS CSC RIDD CSTC

Figure 6. Optically Isolated Application Schematic

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 NCN5150

Table 9. TYPICAL BILL OF MATERIALS

Reference Designator Value (Typical) Tolerance Manufacturer Part Number
U1 − − ON Semiconductor NCN5150
TVS1 40 V − ON Semiconductor 1SMA40CAT3G
CVDD > 1 mF −20%, +80%
RIS 100 W 1%
CSC 220 nF −20%, +80%
RBUS1, RBUS2 220 W 10%
RIDD 1 UL 30 kW 1%
2 UL 13 kW 1%
3 UL (Note 18) 8.45 kW 1%
4 UL (Note 18) 6.19 kW 1%
5 UL (Note 18) 4.87 kW 1%
6 UL (Note 18) 4.02 kW 1%
CSTC 1 UL ≤ 330 mF 10%
2 UL ≤ 820 mF 10%
3 UL (Note 18) ≤ 1,200 mF 10%
4 UL (Note 18) ≤ 1,500 mF 10%
5 UL (Note 18) ≤ 2,200 mF 10%
6 UL (Note 18) ≤ 2,700 mF 10%
18. 3−6 UL configurations are only possible for the NQFP variant.

APPLICATION INFORMATION

The NCN5150 is a slave transceiver for use in the meter bit, 8 data bits, 1 even parity bit, and a stop bit.
bus (M-BUS) protocol. The bus connection is fully polarity Communication speeds allowed by the M-BUS standard are
independent. The transceiver will translate the bus voltage 300, 600, 2400, 4800, 9600, 19200 and 38400 baud, all of
modulation from master-to-slave communication to TTL which are supported by the NCN5150.
UART communication, and in the other direction translate
UART voltage levels to bus current modulation. The Bus Connection and Rectification
transceiver also integrates a voltage regulator for utilizing The bus should be connected to the pins BUSL1 and
the current drawn in this way from the bus, and an early BUSL2 through series resistors to limit the current drawn
power fail warning. The transceiver also supports an from the bus in case of failure (according to the M-BUS
external power supply and the I/O high level can be set to standard). Typically, two 220 W resistors are used for this
match the slave sensor circuit. A complete block diagram is purpose.
shown in Figure 2. Each section will be explained in more Since the M-BUS connection is polarity independent, the
detail below. NCN5150 will first rectify the bus voltage through an active
diode bridge.
Meter Bus Protocol
M-BUS is a European standard for communication and Slave Power Supply (Bus Powered)
powering of utility meters and other sensors. A slave device can be powered by the M-BUS or from an
Communication from master to slave is achieved by external supply. The M-BUS standard requires the slave to
voltage-level signaling. The master will apply a nominal draw a fixed current from the bus. This is accomplished by
+36 V to the bus in idle state, or when transmitting a logical the constant current source CS1. This current is used to
1 (“mark”). When transmitting a logical 0 (“space”), the charge the external storage capacitor CSTC. The current
master will drop the bus voltage to a nominal +24 V. drawn from the bus is defined by the programming resistor
Communication from the slave to the master is achieved RIDD. The bus current can be chosen in increments of
by current modulation. In idle mode or when transmitting a 1.5 mA called unit loads. Table 5 list the different values of
logical 1 (“mark”), the slave will draw a fixed current from programming resistors needed for different unit loads, as
the bus. When transmitting a logical 0 (“space”), the slave well as the current drawn from the bus (IBUS) and the current
will draw an extra nominal 15 mA from the bus. M-BUS that can be drawn from the STC pin (ISTC). ISTC is slightly
uses a half-duplex 11-bit UART frame format, with 1 start less than IBUS to account for the internal power consumption

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 NCN5150

of the NCN5150. The RIDD resistor used must be at least 1% VBUS VMARK = [21 V, 42 V]
accurate. Note that using 5 and 6 Unit Loads is not covered VT = VMARK − 6 V
by the M-BUS standard.
VSPACE = VMARK − 12 V
When the voltage on the STC pin reaches VSTC, VDD ON t
the LDO is turned on, and will regulate the voltage on the
VTX VIO
VDD pin to 3.3 V, drawing current from the storage
capacitor. A decoupling capacitor of minimum 1 mF is
required on the VDD pin for stability of the regulator. On the t
STC pin, a minimum capacitance of 10 mF is required.
VTXI VIO
Furthermore, the ratio CSTC/CVDD must be larger than 9.
The voltage on the STC pin is clamped to VSTC, clamp by a
shunt regulator, which will dissipate any excess current that t
is not used by the NCN5150 or external circuits.
Figure 7. Communication, Master to Slave
Slave Power Supply (External)
In case the external sensor circuit consumes more than the VB
allowed bus current or the sensor should be kept operational
when the bus is not present, an external power supply, such ICHARGE
as a battery, is required. SC
When the external circuitry uses different logical voltage
levels, simply connect the power supply of that voltage level
IDISCHARGE
to VIO, so that the RX, RXI, TX, TXI and PFb pins will +
respond to the correct voltage levels. The NCN5150 will still −
be powered from the bus, but all communication will be
translated to the voltage level of VIO.
If the external power supply should be used only as a
backup when the bus power supply fails, a PMOS transistor TX
can be inserted between the external power supply and VDD Encoding
as shown in Figure 5. The gate is connected to VS, and will Echo
TXI
be driven high when the voltage on STC goes above the
turn-on threshold of the LDO, nl. VSTC, VDD ON. For more Figure 8. Communication, Master to Slave
information see the paragraph on the power on sequence and
corresponding Figure 12 on page 10. Communication, Slave to Master
M-BUS communication from slave to master uses bus
Communication, Master to Slave current modulation while the voltage remains constant. This
M-BUS communication from master to slave is based on current modulation can be controlled from either the RX or
voltage level signaling. To differentiate between master RXI pin as shown in Figure 10. When transmitting a space
signaling and voltage drop caused by the signaling of (“0”), the current modulator will draw an additional current
another slave over cabling resistance, etc., the mark level from the bus. This current can be set with a programming
VBUS, MARK is stored, and only when the bus voltage drops resistor RRIS. To achieve the space current required the
to less than VT will the NCN5150 detect communication. A M-BUS standard, RRIS should be 100 W. A simplified
simplified schematic of the receiver is shown in Figure 8. schematic of the transmitter is shown in Figure 11.
The received data is transmitted on the pins TX and TXI, as
shown in the waveforms of Figure 7.
An external capacitor must be connected to the SC pin to
store the mark voltage level. This capacitor is charged to VB.
Discharging of this capacitor is typically 40x slower, so that
the voltage on SC drops only a little during the time the
master is transmitting a space. The value of CSC must be
chosen it the range of 100 nF−330 nF.

Figure 9. Typical Relationship between RIS and

Current Modulation Level

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 NCN5150

Because the M-BUS protocol is specified as half-duplex, shut down gracefully. The times ton and toff can be
an echo function will cause the transmitted signal on RX or approximated by the following formulas:
RXI to appear on the receiver outputs TX and TXI. Should C STC
the master attempt to send at the same time, the bitwise t on + V STC, VDD ON (eq. 1)
added signal of both sources will appear on these pins, I STC
resulting in invalid data. C STC
t off + ǒVSTC, Clamp * VSTC, VDD OFFǓ (eq. 2)
VRX I CC ) I DD
VIO
Where ICC is the internal current consumption of the
t
NCN5150 and IDD is the current consumed by external
circuits drawn from either VDD or STC.
VRXI VIO These formulas can be used to dimension the value of the
bulk CSTC needed, taking into account that the M-BUS
t standard requires ton to be less than 3 s.
IBUS
For certain applications where the power drawn from the
ISPACE = IMARK + 15 mA bus is not used in external circuits, the storage capacitor
value can be much lower. The NCN5150 requires a
IMARK = N unit loads minimum STC capacitance of 10 mF to ensure that the bus
t current regulation is stable under all conditions.

Figure 10. Communication, Slave to Master VBUS

VB = VSTC + 0.6

VB = VB, MIN
VIO_BUF
t
VSTC ton VSTC, CLAMP
Echo VSTC, VDD ON
RX VSTC, VDD OFF
Decoding
VB t
RXI
VVS VSTC, CLAMP
Enable

+ t
−
VDD
3.3 V

RIS
t
VPFb
VIO

toff t
Figure 11. Communication, Slave to Master
Figure 12. Power-on and Power-off
Power On/Off Sequence
The power-on and power-off sequence of the NCN5150 Thermal Shutdown
is shown in Figure 12. Shown also in Figure 12 is the The NCN5150 includes a thermal shutdown function that
operation of the PFb pin. This pin is used to give an early will disable the transmitter when the junction temperature of
warning to the microcontroller that the bus power is the IC becomes too hot. The thermal protection is only active
collapsing, allowing the microcontroller to save its data and when the slave is transmitting a space to the master.

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 NCN5150

Table 10. ORDERING INFORMATION

Device Package Shipping†
NCN5150MNTWG QFN20, 4x4 2,500 / Tape & Reel
(Pb-free)

DISCONTINUED (Note 19)

NCN5150DG SOIC16 48 Units / Tube
(Pb-free)
NCN5150DR2G 3,000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
19. DISCONTINUED: These devices are not recommended for new design. Please contact your onsemi representative for information. The
most current information on these devices may be available on www.onsemi.com.

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 MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

QFN20, 4x4, 0.5P

CASE 485E
ISSUE C
DATE 13 FEB 2018
SCALE 2:1
NOTES:
D A EXPOSED 1. DIMENSIONING AND TOLERANCING PER ASME

ÉÉ ÉÉ ÉÉÉ
COPPER Y14.5M, 1994.
B A3 A3 2. CONTROLLING DIMENSION: MILLIMETERS.

ÉÉ ÇÇ ÉÉÉ
ÇÇÇ
3. DIMENSION b APPLIES TO PLATED TERMINAL
MOLD AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
COMPOUND
PIN ONE

ÉÉ
FROM THE TERMINAL TIP.
REFERENCE 4. COPLANARITY APPLIES TO THE EXPOSED PAD
A1 PLATING A1 AS WELL AS THE TERMINALS.
E
2X DETAIL B MILLIMETERS
0.15 C ALTERNATE DIM MIN MAX
CONSTRUCTIONS A 0.80 1.00
2X A1 --- 0.05
A3 0.20 REF
0.15 C
TOP VIEW L L b 0.20 0.30
D 4.00 BSC
D2 2.60 2.90
DETAIL B (A3) A L1 E 4.00 BSC
E2 2.60 2.90
0.10 C e 0.50 BSC
K 0.20 REF
DETAIL A L 0.35 0.45
0.08 C OPTIONAL CONSTRUCTIONS L1 0.00 0.15
A1 C
SEATING
GENERIC
SIDE VIEW PLANE
MARKING DIAGRAM*
0.10 C A B 20
D2 1
DETAIL A XXXXXX
20X L
6
XXXXXX
0.10 C A B ALLYWG
11 G
E2
XXXXXX= Specific Device Code
1
A = Assembly Location
20 LL = Wafer Lot
K 20X b Y = Year
e 0.10 C A B W = Work Week
0.05 C NOTE 3 G = Pb−Free Package
BOTTOM VIEW (Note: Microdot may be in either location)
SOLDERING FOOTPRINT* *This information is generic. Please refer to
device data sheet for actual part marking.
4.30 Pb−Free indicator, “G” or microdot “ G”,
20X
0.58 may or may not be present. Some products
2.88 may not follow the Generic Marking.

2.88 4.30

PKG
OUTLINE
20X
0.35
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON03163D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: QFN20, 4X4, 0.5P PAGE 1 OF 1

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

SOIC−16 9.90x3.90x1.37 1.27P

CASE 751B
ISSUE M
DATE 18 OCT 2024

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42566B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−16 9.90X3.90X1.37 1.27P PAGE 1 OF 2

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 SOIC−16 9.90x3.90x1.37 1.27P
CASE 751B
ISSUE M
DATE 18 OCT 2024

GENERIC
MARKING DIAGRAM*
16
XXXXXXXXXXXXG
XXXXXXXXXXXXX
AWLYWW
1
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.

STYLE 1: STYLE 2: STYLE 3: STYLE 4:

PIN 1. COLLECTOR PIN 1. CATHODE PIN 1. COLLECTOR, DYE #1 PIN 1. COLLECTOR, DYE #1
2. BASE 2. ANODE 2. BASE, #1 2. COLLECTOR, #1
3. EMITTER 3. NO CONNECTION 3. EMITTER, #1 3. COLLECTOR, #2
4. NO CONNECTION 4. CATHODE 4. COLLECTOR, #1 4. COLLECTOR, #2
5. EMITTER 5. CATHODE 5. COLLECTOR, #2 5. COLLECTOR, #3
6. BASE 6. NO CONNECTION 6. BASE, #2 6. COLLECTOR, #3
7. COLLECTOR 7. ANODE 7. EMITTER, #2 7. COLLECTOR, #4
8. COLLECTOR 8. CATHODE 8. COLLECTOR, #2 8. COLLECTOR, #4
9. BASE 9. CATHODE 9. COLLECTOR, #3 9. BASE, #4
10. EMITTER 10. ANODE 10. BASE, #3 10. EMITTER, #4
11. NO CONNECTION 11. NO CONNECTION 11. EMITTER, #3 11. BASE, #3
12. EMITTER 12. CATHODE 12. COLLECTOR, #3 12. EMITTER, #3
13. BASE 13. CATHODE 13. COLLECTOR, #4 13. BASE, #2
14. COLLECTOR 14. NO CONNECTION 14. BASE, #4 14. EMITTER, #2
15. EMITTER 15. ANODE 15. EMITTER, #4 15. BASE, #1
16. COLLECTOR 16. CATHODE 16. COLLECTOR, #4 16. EMITTER, #1

STYLE 5: STYLE 6: STYLE 7:

PIN 1. DRAIN, DYE #1 PIN 1. CATHODE PIN 1. SOURCE N‐CH
2. DRAIN, #1 2. CATHODE 2. COMMON DRAIN (OUTPUT)
3. DRAIN, #2 3. CATHODE 3. COMMON DRAIN (OUTPUT)
4. DRAIN, #2 4. CATHODE 4. GATE P‐CH
5. DRAIN, #3 5. CATHODE 5. COMMON DRAIN (OUTPUT)
6. DRAIN, #3 6. CATHODE 6. COMMON DRAIN (OUTPUT)
7. DRAIN, #4 7. CATHODE 7. COMMON DRAIN (OUTPUT)
8. DRAIN, #4 8. CATHODE 8. SOURCE P‐CH
9. GATE, #4 9. ANODE 9. SOURCE P‐CH
10. SOURCE, #4 10. ANODE 10. COMMON DRAIN (OUTPUT)
11. GATE, #3 11. ANODE 11. COMMON DRAIN (OUTPUT)
12. SOURCE, #3 12. ANODE 12. COMMON DRAIN (OUTPUT)
13. GATE, #2 13. ANODE 13. GATE N‐CH
14. SOURCE, #2 14. ANODE 14. COMMON DRAIN (OUTPUT)
15. GATE, #1 15. ANODE 15. COMMON DRAIN (OUTPUT)
16. SOURCE, #1 16. ANODE 16. SOURCE N‐CH

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42566B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−16 9.90X3.90X1.37 1.27P PAGE 2 OF 2

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com
2
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
 onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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