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The document describes a 4-bit Arithmetic Logic Unit (ALU) implemented in Verilog, detailing its functionality for various operations such as addition, subtraction, and bitwise operations based on a control signal. It includes a testbench to validate the ALU's operations through a series of test cases. Additionally, it mentions synthesis constraints and settings for the design in Vivado, including clock period and input/output delays.

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Adithyan J
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36 views5 pages

Assignmnt Code

The document describes a 4-bit Arithmetic Logic Unit (ALU) implemented in Verilog, detailing its functionality for various operations such as addition, subtraction, and bitwise operations based on a control signal. It includes a testbench to validate the ALU's operations through a series of test cases. Additionally, it mentions synthesis constraints and settings for the design in Vivado, including clock period and input/output delays.

Uploaded by

Adithyan J
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

CODE

module ALU_4bit (
input [3:0] A, // 4-bit input A
input [3:0] B, // 4-bit input B
input [2:0] ALU_Control, // 3-bit ALU control signal
output reg [3:0] ALU_Result, // 4-bit result
output reg Zero // Zero flag
);

// ALU_Control[2:0] -> 000: ADD, 001: SUB, 010: AND, 011: OR, 100: XOR, 101: LSHIFT, 110: RSHIFT
always @ (A, B, ALU_Control)
begin
case (ALU_Control)
3'b000: ALU_Result = A + B; // Addition
3'b001: ALU_Result = A - B; // Subtraction
3'b010: ALU_Result = A & B; // AND
3'b011: ALU_Result = A | B; // OR
3'b100: ALU_Result = A ^ B; // XOR
3'b101: ALU_Result = A << 1; // Left Shift
3'b110: ALU_Result = A >> 1; // Right Shift
default: ALU_Result = 4'b0000; // Default case
endcase

// Set Zero flag


if (ALU_Result == 4'b0000)
Zero = 1'b1; // Set the Zero flag if result is zero
else
Zero = 1'b0; // Reset the Zero flag if result is non-zero
end

endmodule

TESTBENCH
module ALU_4bit_tb;

// Inputs
reg [3:0] A;
reg [3:0] B;
reg [2:0] ALU_Control;

// Outputs
wire [3:0] ALU_Result;
wire Zero;

// Instantiate the ALU


ALU_4bit uut (
.A(A),
.B(B),
.ALU_Control(ALU_Control),
.ALU_Result(ALU_Result),
.Zero(Zero)
);

// Test procedure
initial begin
// Test Addition
A = 4'b0011; B = 4'b0001; ALU_Control = 3'b000; #10;
// Test Subtraction
A = 4'b1010; B = 4'b0100; ALU_Control = 3'b001; #10;
// Test AND
A = 4'b1100; B = 4'b1010; ALU_Control = 3'b010; #10;
// Test OR
A = 4'b1100; B = 4'b1010; ALU_Control = 3'b011; #10;
// Test XOR
A = 4'b1100; B = 4'b1010; ALU_Control = 3'b100; #10;
// Test Left Shift
A = 4'b0110; B = 4'b0000; ALU_Control = 3'b101; #10;
// Test Right Shift
A = 4'b0110; B = 4'b0000; ALU_Control = 3'b110; #10;

// Finish simulation
$finish;
end
endmodule

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SYNTHESIS
SCHEMATIC

The constraints of clock of 10ns clock period is being added.


Input delay and output delay of IO ports have been set as 1ns.
IO ports have been placed and DRC have been corrected.
Generated Bit streanthe output in Vivado.

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