HMS

Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

1. Design Process for Integrated Circuits (ICs)

and Printed Circuit Boards (PCBs)
1.1 Design and Realization Alternatives
1.2 Design Methods
1.3 Use of Hardware Description Languages (HDLs)
 Basic Functions of Electronic Systems
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Real Environment
Electronic System

Signal
Processing
System Actuators
Sensors
Analog/ control
Digital

Communication with
other micro systems
2
 Smart Systems - Principal Structure
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Power electronics
Signal-Carrying

Actuators
Forms of Energy
Analog
Optical signal
processing
Real environment

Mechanical

System Control
Biological, Chemical, Physical
Thermal Microcontroller
Special interfaces
DSP

Power Supply
Electrical Real Time Operating System

Magnetic Electrical Digital

Chemical Magnetic Signal
Optical Processing
Sensors

Mechanical
Thermal
Communication with
other Systems

3
 “Embedded” Electronic Systems
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

There are more embedded electronic systems

around us than we think
Audio
Video
Television
Medical Equipment
House keeping
Office
In an automobile

4
 Automotive Electronic Control Units
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Characteristics: distributed system

In a premium class car up to:
• 80 computers (Electronic Control Units ECU)
• > 100 Electrical Motors
• > 2 km wiring
• millions of lines of code

5
 Automotive Electronic Control Units
Characteristics: distributed, mechatronic
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Mechatronic Example:
Hydraulic
Brake System

Mit freundlicher Genehmigung

der Daimler AG

ECU’s are part of

mechatronic systems
for
measurement and Software
control is part of
ECU
6
Benz
 Electronic Control Units – ECU in a car
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Control unit for electronic stability program

Combined Control six speed

control unit for diesel automatic gearbox
engine
Control unit for hydraulic brake
By courtesy of Robert Bosch GmbH

7
 Typical Design Flow
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Idea System-Analysis
Executable Specs
System Design
ASR
ASR

Rad 1
Kontrolle
control

Rad 1
Customer Requirements
Wheel 1 Wheel 2
Technical Requirements
HW/SW-Requirements Analysis
Frei Frei
free free

Bremsen
brake
Bremsen
brake System Architecture
Preliminary HW/SW-Design Interfaces
HW-Architecture, SW-Architecture Modeling and Simulation
Interface Description PROCESS (slippage, state)
BEGIN
Real-Time Requirements
CASE state IS
WHEN free =>
IF slippage > 0 THEN

Rapid Prototyping
next_state <= brake;
ELSE
next_state <= chk;
Hardware Platform
Code Generation
& Detailed HW/SW-Design
Real Time Operating System
& SW-Design, Data Dictionary
Configurable Interfaces
& & HW-Drawings
HW-Analysis Report

HW/SW-Implementation
Integration
SW-Modules, Data Dictionary,
SW-Component, HW-Component,
System Integration
HW-Module, HW-Realization, Documents Calibration, Application
Transition to Utilization
8
 Implementation Alternatives
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Implementation of Electronic Systems

Software Integrated Circuits Other Components

µP, µC, DSP Passive

Components
RAM, ROM ASICs Standard-ICs
Discrete
Source Code Semiconductors
TTL
Power
ECL Electronics
Manufacturer User
configured configured CMOS Power Supply

Sensors

Actuators
Mask One-Time Re-
Custom ICs
Programmable Programmable programmable Interconnecting
Technology
Standard Cells Gate Arrays PLDs LCAs

Generic Cells Sea of Gates FPGAs EEPROMs

Full Custom ROM FPGAs 9

 RAM-based FPGA
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Xilinx VIRTEX
XCV2000 E Properties:
 ca. 2.500.000 gates
 80*120 CLB-Array
 43.200 “Logic Cells”
 Board system clock: 33MHz
 0.18 µm 6- Layer CMOS-Process
 Can be reprogrammed infinitely
CLB times
-> thanks to SRAM memory
Block-RAM
 1 MB internal SRAM memory
 130 MHz internal CLB clock
frequency
IOB
 I/O Performance: 622 Mb/s
 404 In-/outputs 10
 Xilinx Virtex: Architecture
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

CLB PLL
Segmented routing

66 MHz PCI SSTL3

Select I/O
Vector Based
Pins
Interconnect
delay=f(vector)

Block
SelectRAM Distributed
Memory SelectRAM
Memory

11
 FPGA - Structure
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

FPGA-Architectures:
 SRAM-based Look-up Tables (LUTs)
 Problems:
• Interconnection: reduces performance
• Relation: active / passive elements

Rekonfigurable Interconnections (Switching Boxes)

Configurable Logic
Block (CLB)

LUT

Source: R. Hartenstein 12
 RAM-based FPGAs: Logic Realization
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Set of programmable “Logic Gates”, is integrated into a flexible interconnection

network -> a “user-programmable” alternative to dedicated ciruits

?
Programmable Gate

Solution:
Look-up-Table (LUT)
In1 With 2 inputs 0
In Out
00 0 Out 1 Out

MUX
In2
01 1 1
10 1 0
11 0 MEM (Select)
(LUT) 13
In1 In2
 FPGA – Example Xilinx Virtex-II Pro
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Virtex-II FPGA: integrated PowerPC ® 405 RISC CPUs (PPC405)

Rocket
IO

Metal 9
Metal 8
Metal 7
Metal 6
Power PC Metal 5
Metal 4 Metal 4
Core Metal 3 Hard Metal 3
Metal 2 Metal 2
Metal 1 IP-block Metal 1
Poly (Power PC) Poly
On-Chip Substrate
Memory
Controller

Fastest DSP Virtex-II

Embedded 8x8 MAC 4.8 Billion MAC/s 0.5 Tera MAC/s
RAM
256-FIR 9.3 MSPS 180 MSPS
1024-FFT 10 µs 1 µs

Quelle: Ivo Bolsens, Xilinx, USA

14
 FPGA Architectures

Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Interconnection
Matrix (IM) Configurable
Logic Block
(CLB)

Digital Signal
Processing (DSP)

Block Random
Access Memory
(BRAM)

 Major FPGA (Xilinx) blocks are CLBs, DSPs and BRAMs connected by an IM
 CLBs contain Multiplexer (Mux), Look-Up-Tables (LUTs) and Flip-Flops (FFs)
providing a configurable logic:
 DSPs are optimized for multiply and add operations

Mux
 BRAMs are optimized for memory operations LUT FF
15
 FPGA – Design and Implementation
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

VHDL Synthesis Logic

Verilog Netlist
Technology
Mapping
Schematic
Entry
Placement

Configuration Routing
File (Bitstream)

FPGA 16
 Overview
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

All Xilinx FPGAs contain the same basic resources

−Logic Resources
−Slices (grouped into configurable logic blocks (CLB))
Containing combinatorial logic and register resources
−Memory
−Multipliers
−Interconnect Resources
−Programmable interconnect
−IOBs
Interfaces between the FPGA and the outside world
−Other resources
−Global clock buffers
−Boundary scan logic

Through various generations, Xilinx added new architectural

resources to target various markets and application areas

17
 Overview
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

18
 Overview
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

19
 Overview
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Artix-7 Architecture Overview

20
 Configurable Logic Block (CLB) in 7-
Series FPGAs
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• Primary resource for

design in Xilinx
FPGAs
• Combinatorial functions
• Flip-flops

• CLB contains two

slices
• Connected to switch
matrix for routing to
other FPGA resources
• Carry chain runs
vertically in a column
from
one slice to the one
above

21
 Two Types of CLB Slices
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Two types of CLB slices

−SLICEM: Full slice

−LUT can be used for logic and
memory/SRL
−Has wide multiplexers and carry
chain
−SLICEL: Logic and arithmetic only
−LUT can only be used for logic
(not memory)
−Has wide multiplexers and carry
chain

22
 Slice Resources
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

23
 7-Series Block RAM and FIFO
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• All members of the 7-

series families have the
same Block RAM/FIFO
• Fully synchronous
operation
 All operations are
synchronous; all outputs are
latched
 Optional internal pipeline
register for higher
frequency operation
 Two independent ports
access common data
 Individual address, clock,
write enable, clock enable
 Independent data widths for
each port
24
 7-Series DSP48E1 Slice
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

25
 Literature

Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• E. Mohsen: “Balancing Performance, Power, and Cost with Kintex-7 FPGAs”;

Xilinx WP432, pp. 1-13, 2013

• https://docs.xilinx.com/v/u/en-US/7-series-product-selection-guide

• UG474 (v1.8): 7 Series FPGAs Configurable Logic Block“; Xilinx , pp. 1-74,
2016.

• UG479 (v1.10): “7 Series DSP48E1 Slice”; Xilinx, pp. 1-58, 2018.

• UG473 (v1.14): „7 Series FPGAs Memory Resources”; Xilinx, pp. 1-88, 2019.

• Xilinx Tutorial: “FPGA Design Flow using Vivado 2018.2”; 2018 (Slides are
partially based on this tutorial)

26
 Design Constraints
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• Increasing Complexity
− Structure size decreases
− Chip dimensions increase
 Number of transistors per chip quadruples every three years

• Higher Performance (clock, speed, power dissipation)

• Pressure of Competition
− Almost no monopolies: extreme price pressure
− Continually decreasing time for development
à “Time to market” decides about success or failure of a product

• “Design Reuse” for Productivity and Quality Improvement

à Requires complete and understandable documentation
(IP - Intellectual Property)

27
 Trend: Transistors Per Die
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

28
 Intel‘s High-End Processor Solutions:
Itanium
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Quelle: Jason Stinson (Intel), DAC 2003 29

 Intel Processors
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Dunnington:

6 Penryn cores
on one chip

3 MByte L2-Cache
per dual-core

16 MByte L3-Cache

1,8 billion transistors

Publication:
Intel Developer Forum
Spring 2008

30
 Intel Processors
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Westmere-EX:

10 cores, 20 logical cores

30 MByte L3-Cache

2,9 billion transistors

32 nm structures

Publication: 31
Spring 2011
 NVIDIAs Fermi GPU
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

General Purpose
Graphics Processing
Unit (GPGPU)

Spring 2011
largest chip ever built

3 billion transistors

512 cores

32
 NVIDIAs Fermi GPU
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• 32 cores form a
SM Streaming
Multiprocessor

• 16 SIMD units

• ECC support
Error Detection
and Correction

• Unified Level 2
Cache

• Six 64-bit
memory
partitions
(384 bit memory
interface)

33
 NVIDIAs Fermi GPU
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• 512 CUDA Cores

(Compute Unified
Device Architecture)

• Parallel computing
architecture developed by
NVIDIA

• Executes one floating point

and one integer instruction
per clock

• 16 Load / Store Units per

SM

• SFU special function unit

handles sine, cosine,
square root, interpolation
etc.

• 64KB Level 1 Cache 34

 NVIDIAs GPU Development
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

35
 How to design such complex Electronic
Systems?
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Principles for mastering complexity:

1. Modularization

2. Hierarchy

3. Abstraction

(Divide and Conquer)

36
 Modularization
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Modularization = subdivide a system into several smaller, logically

related parts (subsystems, modules), based on several criteria*:

• Black Box Concept

• Completeness
• Fully defined interfaces
• Manageability
• Testability
• Limited access
(information hiding, access only through well defined interfaces)
• Minimum (no) mutual interference

* according to E. Denert: "Software Modularisierung", Informatik Spektrum, Volume 2,

Magazine 4, 1979

37
 Modularization supported in VHDL
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Entity concept in VHDL

VHDL = VHSIC Hardware Description Language
VHSIC = Very High Speed Integrated Circuits
Entity A Entity B

Fully defined
Interface Interface
Interface

Testability
Body1 Body1
Limited access
(Separation of Interface
and Implementation)
Body2 Body2

minimum mutual Interference

Complete Unit
Manageability
38
 Hierarchy
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• Hierarchy = Principle of order (formally: partial order) for

the components of a system. Different relations between
the components are considered for the creation of
hierarchies.

• Example: “Uses” hierarchy

Module A uses module B, if the correct operation
of module A depends on the correct operation
of module B, but not the other way round.

39
 Hierarchy: supported in VHDL
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

“Uses” hierarchy in VHDL via instances

entity ALU

uses uses

instance A1 of instance S1 of
entity ADD entity SHIFT

uses uses

instance AN1 of instance AN2 of

entity AND entity AND

40
 Partial Order
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• A partial order ≤ on a set X is a binary relation that is reflexive,

antisymmetric and transitive, i.e., it holds for all a, b and c in X
that:

− a≤a (reflexivity)
− a≤b ∧ b≤c → a≤c (transitivity)
− a≤b ∧ b≤a → a=b (antisymmetry)

• Example:
a
Set X := {a, b, c, d, e, f, g, h}
Relation: ≤ (Hierarchy)
b c d

Hierarchy ≤ on X is a partial order:

e f g/h
a) ∀ x ∈ X: x ≤ x (a ≤ a, b ≤ b, ...)
b) From d ≤ a and e ≤ d results e ≤ a
c) From h ≤ g and g ≤ h results g = h

41
 Modularization and Hierarchy
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

System S
M1

M2 Gate

Mi

n: Number of Gates
m: Number of Modules

Without Modularization With Modularization and Hierarchy

S S

G1 G2 G3 G4 G5 ..... Gn M1 M2 M3 ..... Mm

G1 G2 G3
....

42
 Abstraction
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• Abstraction is hiding of details:

Important and unimportant objects are determined.

• Creation of abstraction levels:

Only those features of an object that are important on a
certain level are considered on that level; unimportant
details are not considered.

• Important basis for the creation of abstraction levels is the

evenness of abstraction:
All data selected for the description on a certain abstraction
level should have the same degree of abstraction.

• Abstraction supported in VHDL:

Algorithmic Level, Register Transfer Level, Logic Level 43
 Design Process
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Y-Diagram according to Gajski and Walker

System Level

Algorithmic Level
Behavior Structure
Register-
Transfer Level
System-
specification Logic Level Systems, Subsystems, Busses, I/O
Algorithms CPU, ALU, Busses, I/O
Circuit
Register Transfers Level Modules, Wires
Boolean Equations Gates, Flip-Flops, Wires
Differential Equations Transistors

Masks, Polygons

Cells

Floorplan

Clusters
Views &
Partitioning
Abstraction Levels
Geometry
44
 Design Views
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• Geometrical view
− Polygons
− Cells
− Floor plan

• Structural view
B
− Transistors, Wires A D OUT

− Gates, Flip-Flops A
CTL D
− Modules, Subsystems B

• Behavioral view
A := 3*B+C
− Differential Equations IF (D=TRUE) THEN
− Boolean Equations A := A + 1
− Register Transfers, ELSE A := A - 1
Algorithms ENDIF
45
 Bluetooth Chip - Geometrical View
(Floorplan)
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

46
 Analog Circuit - Structural View
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

R2 C1 V+

in R1 R3
- out
1 2
Vein + Vout
C2

V-

47
 Digital Circuit - Structural View
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

48
 Finite State Machine - Behavioral View
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

-- Mealy Machine z <= '1';

ENTITY mealy IS next_state <= s2;
PORT (x, clock : IN bit; END IF;
z : OUT bit); WHEN s1 =>
END mealy; IF x='0' THEN
z <= '0';
next_state <= s0;
ARCHITECTURE behavioral OF mealy IS
ELSE
TYPE state_type IS (s0, s1, s2, s3); z <= '0';
SIGNAL current_state, next_state: next_state <= s2;
state_type; END IF;
BEGIN WHEN s2 =>
-- process to hold synchronous elements IF x='0' THEN
sync: PROCESS z <= '1';
BEGIN next_state <= s2;
WAIT UNTIL clock'EVENT AND clock='1'; ELSE
z <= '0';
current_state <= next_state;
next_state <= s3;
END PROCESS; END IF;
WHEN s3 =>
-- process to hold combinational logic IF x='0' THEN
comb: PROCESS (current_state, x) z <= '0';
BEGIN next_state <= s3;
CASE current_state IS ELSE
WHEN s0 => z <= '1';
IF x='0' THEN next_state <= s1;
END IF;
z <= '0';
END CASE;
next_state <= s0; END PROCESS;
ELSE END behavioral;
49
 Abstraction Levels
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• System Level Structural View

− Basic Characteristics
compute performance RAM CPU I/O
and communication
bandwidth
− Simplified Functionality Control
− No Timing

−Description Methods:
− Behavior: System/Block Specification
− Structure: CPUs, Memory, Interface Units
− Geometry: Partitioning of Chip/Board Area

50
 Abstraction Levels
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• Algorithmic Level Behavioral View

− Small kernel algorithms A := 3*B+C

− No consideration of IF (D=TRUE) THEN
target architectures A := A + 1
(floating point, word length) ELSE A := A - 1
− No Timing Details ENDIF
− No System Clock

−Description Methods:
− Behavior: Functions and Procedures
− Structure: Subsystems, Busses
− Geometry: Cluster

51
 Abstraction Levels
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• Register-Transfer Level Structural View

− Basic Operations 4
(e.g. Addition, bit_vectors) Register
RAM
− Transfers between Registers
− Timing via Clock/Reset Signals ROM ALU MUX
− discrete values, discrete time
Two- (multi-) valued logic signals

− Description Methods:
− Behavior: Arithmetic Operations,
Finite State Machines
− Structure: Modules (Registers, Encoder, ...)
− Geometry: Floor Plan

52
 Abstraction Levels
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• Logic Level Structural View

− Multi-valued logic signals

still discrete time 1
D
− Single wires and busses Q
=1
− Timing (Delays) &

− Description Methods:
− Behavior: Boolean Equations
− Structure: Gates, Flip-Flops (Net List)
− Geometry: Cells

53
 Abstraction Levels
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• Circuit Level Structural View

− Value- and Time- B

A D OUT
Continuous Signals
(Voltages and Currents) A
CTL D
− Actual Components B
(transistors, diodes, resistors,
capacitors, inductors)
− Detailed Component Models

− Description Methods:
− Behavior: Ordinary Nonlinear
Differential Equations
− Structure: Transistors, Resistors,
Capacitors, Wires,
Current/Voltage Sources
− Geometry: Polygons
54
 Model of the Design Process
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Level i Level i

Level i+1 Level i+1

55
 Model of the Design Process
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

System Level

Algorithmic Level

RT Level

Gate Level

Switch Level

Electrical Level

Design Design
Languages Documents
56
 Design Process
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Behavioral Verification Structural

Description Description
Synthesis

Refinement
Optimization
Verification

Layout
Transformation

Physical / Geometrical
Description
57
 Design Complexity
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Verification 100 million

polygons
10 million
transistors
2 million
logic gates
20000
lines code
5000
lines code
100 VHDL &
lines code 1

D:=3*X; ≥1
&
Speci- IF D=TRUE
System THEN
fication Y <= B;
Require-
END IF;
ments

Requirements Behavioral Structural Logic Schematic Mask

Description Description Diagram Level
58
 Strategies for Design
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Specification

System Design and

Bottom-up Design
Partitioning

Top-down Design

Yo-Yo Design
Refinement
Gradual

Component
Design

Implementation

59
 Phase Model for System Design
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Phase Subjects Result

Brainstorming, Market analysis, Definition of the requirements
Study Realization analysis, General description
Check for principle realization Rough cost / time estimate

Behavior oriented description, Task manual

Concept Defining the function as a goal,
Behavioral specification
Defining test strategy

Architecture development, Target specification

Hardware /Software tradeoff, Architecture specification
Design
Technical description of the development,
Test specification
Detail specification, test methods

Refinement Verified components

Encoding, Implementation documentation
Implementation
Manual design and synthesis,
Module Test Integration specification

Integration of modules Verified prototype

Integration and Test Verification of subsystems
Verification of system Integration documentation

Production Transfer to product management Cleared product

Commissioning Production

Maintenance and Service Changes, Improvements, Upgrades Maintenance / error protocols

Field Service Recycling , Disposal Lifecycle documentation

60
 Computer Support for IC and PCB Design
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Specification

Logic Design

Schematic Entry

Pattern for Logic Verification

Logic Simulation

AC & DC Transient Analysis

Central Testability Analysis
Database
Layout Generation (Optimizing)

Layout Verification

Realtime Behavioral simulation

Generation of Test Program

Generation of Production Data

IC Masks PCB PCB PCB, IC Tester 61

Placement Drill Information
 Motivation: Typical ASIC Design Flow
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Independent of
Technology

Dependent on
Technology
62
 Design Methods for Current Technologies
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Hardware Description Levels of Abstraction

Net List
architecture structural of first_tap is

signal x_q,red : std_logic_vector(bitwidth-1

downto 0);
signal mult : std_logic_vector(2*bitwidth-1
downto 0);

begin

delay_register:
process(reset,clk)
begin
if reset='1' then
x_q <= (others => '0');
elsif (clk'event and clk='1') then
x_q <= x_in;
Synthesis
end if;
end process;
(Synopsys)
mult <= signed(coef)*signed(x_q);

Place & Route

(Cadence/
Mentor)

Mask
Manufacture Layout

63
Chip Wafer
 Design Process
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Behavioral Verification Structural

Description Description
Synthesis

Refinement
Optimization
Verification

Layout
Transformation

Physical / Geometrical
Description
64
 Transformations
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Transformation

Global Local

Without With
Optimization
Change of View Change of View
Verification
(Refinement) (Logic Synthesis)

65
 Transformations
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Description Data on Level i

Description Data Description Data Description Data

T : T : T :
Verifi- Verifi- Verifi-
manual interactive Automatic
cation cation cation
Design design design

Description Data Description Data Description Data

Description Data on Level i + 1

66
 Development of Electronic Systems
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Development of Electronic Systems

=
Sequence of Design Steps
(Analysis and Synthesis, creative, manual and automatic)

and

Verification Cycles

Top-Down Bottom-Up Yo-Yo

67
 Abstraction, Hierarchy, Modularization
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

RAM CPU IO
Modulari-
1 Architecture zation
CONTROL

H
A := 3*B+C

2 Algorithm
IF (D=TRUE) THEN
A := A + 1
Modulari- I
ELSE A := A - 1 zation
ENDIF E
R
Abstraction

4
RAM Register
Modulari-
3 Register Transfer zation A
ROM ALU MUX

R
1
Modulari- C
4 Logic D Q =1
zation
& H
B Y
A D OUT
Modulari-
5 Electrical Circuit A
CTL D zation
B

68
 Abstraction, Hierarchy, Modularization
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• Abstraction is applied both Top-Down and Bottom-Up

− Example:
 Abstraction top-down:
No separate data path and control path after switching
from register-transfer level to logic level.
 Abstraction bottom-up:
Value- and time-continuous description on the
electric circuit level becomes value- and time-discrete
description on the logic level.
• Modularization is possible on every abstraction level
• Hierarchy (concept orthogonal to abstraction)
− A hierarchical description may comprise different
abstraction levels.
− A hierarchical description can be applied to one distinct
abstraction level.

69
 Hierarchy of the System Design
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Micro System
Implementation
Requirement Specification Design Integration Production
description Subsystem i &Test & Service

Acquisition / Processing Diagnosis

Implementation Integration Implementation Integration
Spec. Design Signal processing Data Acquisition Spec. Design Hardware Software
&Test &Test

Signal processing µC-Kernel

Implementation Integration
Spec. Design Spec. Selection
Component &Test Standard µC

ALU Diagnosis Software

Spec. VHDL-RTL Integration Functional Implementation Integration
Logic Spec.
VHDL description synthesis &Test Design Module k &Test

Data acquisition
Implementation Integration
Spec. Design
Component &Test

Software Module:
Sensor Fault Detection
Conceptual Detail Test Conceptual Detail Module
Spec. Design Spec. Design Test
Design Design 70
 Abstraction Levels for Modeling and
Simulation
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Abstraction-
levels Overall System
A1
Closed Loop / Reactive Control System A2
idealized Sensor/Actuator B
e/act

Register-Transfer RAM ALU ROM

CONTROL

Digital
Circuits Logic

Timing

Analog simplified
Macro models Sensor/Actuator-
Circuits
models
Process,
Physical models Sensor/Actuator-
models

1 10 102 103 104 105 106 Complexity

(# of Components)
71
 Synthesis across Abstraction Levels
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Architecture Synthesis
Architecture RAM CPU IO - Partitioning
specification - Parallel processes
CONTROL - Analysis

A := 3*B+C
IF (D=TRUE) THEN Algorithmic Synthesis
Algorithmic A := A + 1
specification ELSE A := A - 1 - Synthesis of digital circuits
ENDIF - Optimization
- Design alternatives (serial / parallel)

4
Register
Block Diagram RAM
Net list optimization
(independent of manu- ROM ALU MUX - Inclusion of Libraries
facturer and technology) - Refining the structural description

Schematic
Conventional CAD-System
Net list 1
=1
D Q
(independent of manu- &
Standard ICs Standard cells
facturer and technology) PCBs Gate Arrays

Implementation ASIC
72
 Verification Methods
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Design
Description Model Aj
Block A {Stimuli}
Level i

6 1 2 5

Formal
Expansion Design Step Expansion Simulation
Equivalence
Technique m Technique n Ai ↔ An,i+1
Ai ↔ Am, i+1

3
Design Formal Design
Description Equivalence Description Model An,i+1
Structure Am Structure An {Stimuli}
Level i+1 Am ↔ An Level i+1

Model Am Simulation Model An

{Stimuli} Am ↔ An {Stimuli}
73
 Verification Methods
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Design
Description
Block A
Level i

Expansion
Technique m T

Design
Description
Structure Am
Level i+1

74
 Verification Methods
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Design
Description
Block A
Level i

6 1

Formal
Expansion
Equivalence
Technique m T
Ai ↔ Am, i+1

Design
Description
Structure Am
Level i+1

75
 Verification Methods
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Design
Description
Block A
Level i

Expansion
T Technique n

Design
Description
Structure An
Level i+1

76
 Verification Methods
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Design
Description Model Aj
Block A {Stimuli}
Level i

2 5

Expansion Simulation
T Technique n Ai ↔ An,i+1

Design
Description Model An,i+1
Structure An {Stimuli}
Level i+1

77
 Verification Methods
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Design
Description
Block A
Level i

1 2

Expansion Expansion
Technique m T Technique n

3
Design Formal Design
Description Equivalence Description
Structure Am Structure An
Level i+1 Am ↔ An Level i+1

78
 Verification Methods
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Design
Description
Block A
Level i

1 2

Expansion Design Step Expansion

Technique m Technique n

Design Design
Description Description
Structure Am Structure An
Level i+1 Level i+1

Model Am Simulation Model An

{Stimuli} Am ↔ An {Stimuli}
79
 Verification Methods
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Design
Description Model Aj
Block A {Stimuli}
Level i

2 5

Expansion Simulation
T Technique n Ai ↔ An,i+1

Design Design
Local
Description Description Model An,i+1
Trans-
Structure Am Structure An {Stimuli}
formation
Level i+1 Level i+1

80
 Verification Methods
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Design
Description Model Aj
Block A {Stimuli}
Level i

2 5

Expansion Simulation
T Technique n Ai ↔ An,i+1

Design Formal Design

Description Equivalence Description Model An,i+1
Structure Am Structure An {Stimuli}
Level i+1 Am ↔ An Level i+1

81
 Verification Methods
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Design
Description Model Aj
Block A {Stimuli}
Level i

6 1 2 5

Formal
Expansion Design Step Expansion Simulation
Equivalence
Technique m Technique n Ai ↔ An,i+1
Ai ↔ Am, i+1

3
Design Formal Design
Description Equivalence Description Model An,i+1
Structure Am Structure An {Stimuli}
Level i+1 Am ↔ An Level i+1

Model Am Simulation Model An

{Stimuli} Am ↔ An {Stimuli}
82
 Bottom-Up Design Verification
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Requirements

System Specification
Verification

Module 2
Module 1 Alt 1 Module 3

Sub-Module 1

Primitive Primitive Primitive Primitive

83
 Top-Down Design Verification
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

Requirements

Verification (Validation)
System
Specification
Verification Behavioral Test- Verification
Description vectors

Alt 3
Module 2 Alt 2
Module 3 Alt 1 T.V.
V.def.
Alt 2 Verification
V.def. T.V. V.def. T.V.
Module 1 Alt 1
V.def. T.V. V.def. T.V.
V.def. T.V.
Alt 2
Sub-M. 1 Alt 1
V.def. T.V.
V.def. T.V.

Verif.
Primitive Primitive Primitive Primitive
Gate Register
84
 Motivation for HDL
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• Complexity

− About every three years: complexity * 4

− Today: typically >> 100 000 gates/chip
− Computer aided design necessary as
manual design is no longer possible
• Computer aided design tools in various areas:

− Specification
− Simulation
− Prototype production is too expensive and time-consuming
− Early verification is only possible through simulation

− Synthesis
− Given current design complexity, manual design is no longer possible

− Machine-readable description for specification, simulation and

synthesis is necessary
85
 Motivation for HDL
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• Data exchange

− Between customer and developer (requirements specification,

target specification)
− During development between
 Team members
 Different tools
 Different computer systems
− Between development and production (production data)
à Uniform format for data exchange is necessary
• Documentation
− Maintenance / Service / Further development
− Re-use of designs
à Human readable format necessary for documentation
86
 Motivation for HDL
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• System design without using an HDL:

− System developer defines architecture and

requirement specification for modules
− Modules are developed bottom-up by different development
teams, each team designing and verifying its own module
− All modules must have been designed and connected before
simulation of the system is possible
− Comparison of specified data and characteristic data occurs
very late in the development cycle
− Specification data is generally subject to change
during the design process

87
 Motivation for HDL
Fakultät Informatik, Institut für Technische Informatik, Professur für Adaptive Dynamische Systeme

• System design with an HDL:

− System developer defines architecture and functional

requirement specification for modules using an HDL
− HDL as functional specification can be simulated, therefore the
system’s performance can be determined at an early stage: e.g.
hardware/software-tradeoff, hardware and micro-code can be
developed in parallel
− Tools for logic synthesis can be used earlier. A specification
written in an HDL is no longer a reference document for
the design, but actually represents the design itself.
(Synthesis simplifies verification: "correct by construction")
− Regular comparison of specified data and
characteristic data is possible

88