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Tutorial 3

The document is a tutorial for CMOS VLSI Design covering various design tasks including the sketching of NAND and NOR gates, calculating propagation delays using different models, and analyzing logical efforts for different gate configurations. It also includes questions on optimizing delay in multi-stage logic paths and designing inverters for specific capacitance loads. Additionally, it addresses the design of a comparator for checking 32 bits for equality to zero, with emphasis on delay calculations.

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Yashaswini M
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101 views2 pages

Tutorial 3

The document is a tutorial for CMOS VLSI Design covering various design tasks including the sketching of NAND and NOR gates, calculating propagation delays using different models, and analyzing logical efforts for different gate configurations. It also includes questions on optimizing delay in multi-stage logic paths and designing inverters for specific capacitance loads. Additionally, it addresses the design of a comparator for checking 32 bits for equality to zero, with emphasis on delay calculations.

Uploaded by

Yashaswini M
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Tutorial – 3

CMOS VLSI Design (EC53)


2023 - 2024

1. Sketch a 3-input NAND gate with transistor widths chosen to achieve effective rise and fall
resistance equal to that of a unit inverter (R). Annotate the gate with its gate and diffusion
capacitances.
2. A 2-input NOR gate is designed such that it is equivalent to 4x of unit inverter. Show the
design with the transistor sizes.
3. Sketch a 2-input NOR gate with transistor widths chosen to achieve effective rise
and fall resistances equal to a unit inverter. Compute the rising and falling propagation
delays of the NOR gate driving 4 identical NOR gates using:
(a) RC delay model
(b) Elmore delay model
4. Using the Elmore delay model, estimate worst case tpdf and tpdr for the 3-input NAND gate,
if the output is loaded with h identical NAND gates.
5. Find the worst-case Elmore parasitic delay of an n-input NOR gate.
6. What is the logical effort of a (a) n-input NAND gate? (b) n-input NOR gate?

7. Consider four designs of a 6-input AND gate shown above. Develop an expression for the
delay of each path if the path electrical effort is H. What design is fastest for H = 1? For H =
5?
8. A three-stage logic path is designed so that the effort borne by each stage is 10, 9, and 7
delay units, respectively. Can this design be improved? Why? What is the best number of
stages for this path? What changes do you recommend to the existing design?
9. Consider a process in which pMOS transistors have three times the effective resistance as
nMOS transistors. Design a unit inverter in this process. Calculate the logical efforts of a 2-
input NAND gate and a 2-input NOR gate if they are designed with equal rising and falling
delays.
10. An output pad contains a chain of successively larger inverters to drive the large off-chip
capacitance. If the first inverter in the chain has an input capacitance of 20 fF and the off-
chip load is 10 pF, how many inverters should be used to drive the load with least delay?
Estimate this delay, expressed in FO4 inverter delays.
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11. The branch comparator in a processor requires a comparator that can check whether 32 bits
are all equal to zero. The output of the comparator is one if all inputs are zero. Assuming H =
1, design the circuit and calculate the delay in a technology with 3RC delay of 20 ps.
Equations Required
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