SEACOM ENGINEERING COLLEGE

NAME-SANJIB KOLEY

ROLL NO-20601622019

REG NO-22206011077

DEPT-ELECTRICAL

STREAM-B.TECH(EE)

SUB-VLSI & MICROELECTRONICS

TOPIC-DERIVE THE EXPRESSION FOR TRANSFER CHARACTERISTICS OF

CMOS INVERTER.

CMOS Inverter Voltage

Transfer Characteristics
To design a digital VLSI circuit one need to have a very good understanding of the basic CMOS inverter. Once you
understand the properties and operation of an inverter then we can extend the concepts to understand any other logic
gate. So it is very important to have a clear idea of CMOS inverter voltage transfer characteristics.

In this post we will concentrate on understanding the voltage transfer characteristics of CMOS inverter. Though the
inverter circuit looks so simple it cannot be overlooked because of its importance in the design of any digital circuit.
Once we design an inverter correctly i.e. fixing width and length of transistors then we can build an entire circuit just
multiplying these values by a multiplication factor(explained in later posts).
Figure-1 shows the schematic of a CMOS inverter. As we can see it have two transistors a pull-up pMOS
transistor(T1) and a pull-down nMOS transistor(T2). When the input voltage Vin is equal to Vdd we get an output
voltage of Vss(mostly equal to 0) and vice versa. Since it inverts the logic level of input this circuit is called an
inverter. Figure-2 shows the voltage transfer characteristics(VTC) or DC characteristics of an inverter.
The VTC is divided into five regions(1-5) for easy of understanding. The above shown curve is possible when both T1
and T2 are matched for optimum operation. Optimum operation is achieved when Vin = Vdd/2 we get Vout = Vdd/2 .
This can be achieved by adjusting width and length of both T1 and T2 as other parameters like mobility, oxide
capacitance vary between different technologies.

For an easy understanding of this article let us set the conditions for a transistor in cutoff,linear and saturated
regions.Note that Vtn is positive and Vtp is negative in this entire article.The below table clearly explains these
conditions.

Device Cutoff Linear Saturated

NMOS 1. Vgsn < Vtn 1. Vgsn > Vtn 1. Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn

2. Vdsn < Vgsn - Vtn 2. Vdsn > Vgsn - Vtn

Vout - Vss < Vin - Vss - Vtn Vout - Vss > Vin - Vss - Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

PMOS 1. Vgsp > Vtp 1. Vgsp < Vtp 1. Vgsp < Vtp
Vin- Vdd > Vtp Vin < Vdd + Vtp Vin < Vdd + Vtp
Vin > Vdd + Vtp
2. Vdsp > Vgsp - Vtp 2. Vdsp < Vgsp - Vtp
Vout - Vdd > Vin - Vdd - Vtp Vout - Vdd < Vin - Vdd - Vtp
Vout > Vin - Vtp Vout < Vin - Vtp
Since we have build a platform lets understand all the regions of the characteristics one by one.

Region-1
In this region the input is in the range of (0,Vtn). Since the input voltage is less than Vtn, the NMOS is in cutoff region.
No current flows from Vdd to Vss, The entire Vdd will appear at the Output terminal.
• NMOS is in cutoff as Vgs < Vtn

• PMOS is in linear as Vgsp < Vtp and Vdsp > Vgsp -Vtp.

• Zero current flows from supply voltage and the power dissipation is zero.

Region-2
In this region the input is in the range of (Vtn,Vdd/2). Since the input voltage is greater than Vtn the NMOS is
conducting and it jumps to saturation as it has large Vds across it(Vout is high). PMOS still remains in the linear
region.
• NMOS is in saturation as Vgs > Vtn and Vout >Vin - Vtn.

• PMOS is in linear region as Vdsp > Vgsp -Vtp.

• since both the transistors are conducting some amount of current flows from supply in this region.

Region-3
In this region the input voltage is Vdd/2. At this point the output voltage is also Vdd/2 as one can see in figure-2. At
this voltage both the NMOS and PMOS are in saturation and the output drops drastically from Vdd to Vdd/2. At this
point a large amount of current flows from the supply. Most of the power consumed in CMOS inverter is at this point.
So care should be taken that the Input should not stay at Vdd/2 for more amount of time.
• NMOS is in saturation as Vgs > Vtn and Vout >Vin - Vtn.

• PMOS is in saturation as Vgsp < Vtp and Vdsp < Vgsp -Vtp.

• Large amount of current is drawn from supply and hence large power dissipation.

Region-4
In this region the input voltage is in the range of (Vdd/2 , Vdd-Vtp). Here the PMOS remains in saturation as Vout <
Vin - Vtp and Vgsp < Vtp. But the NMOS moves from saturation to linear region since the drain to source voltage now
is less than Vgsn-Vtn.
• NMOS is in linear as Vgs > Vtn and Vout < Vin - Vtn.

• PMOS is in saturation as Vgsp < Vtp and Vdsp < Vgsp -Vtp.

• A medium amount of current is drawn as NMOS is in linear region and power dissipation is low.

Region-5
In this region the input voltage is in the range of (Vdd-Vtp,Vdd). Here the PMOS moves from saturation to cutoff as
the Vgsp is so high that Vgsp > Vtp. The NMOS still remains in linear as the drain to source voltage now is less than
Vgsn-Vtn.
• NMOS is in linear as Vgs > Vtn and Vout < Vin - Vtn.

• PMOS is in cutoff as Vgsp > Vtp.

• Zero current flows from the supply and so the power dissipation is zero.
 Now that we have clearly understood the voltage transfer characteristics and operation of an NMOS, we will discuss
how to alter the transfer characteristics of any CMOS gate in the next article.

Applications
The applications of CMOS inverters include the following.
• CMOS inverters are used in different ICs (integrated circuits) like microprocessors, static
RAM, microcontrollers, data converters, image sensors & transceivers.
• These are found in mobile devices, digital cameras, home computers, cell phones,
routers, network servers, modems & virtually each other electronic device that needs
logic functions.
What is the function of a CMOS inverter?
CMOS inverters are the most frequently used flexible MOSFET inverters that are used in
designing integrated circuits like CD4069UB CMOS hex inverter, CD4069UBE,
CD40106BE, etc. They function through very little power loss & high speed. These inverters
are used for generating data in small electronic circuits.

What is an inverter gate in CMOS?

In CMOS, an inverter gate is one type of logic gate, used to implement logical negation (¬).

Which gate is also called an inverter?

NOT logic gate is also called an inverter because NOT gate gives low output for high input
and provides a high output for low input.
Why do we use P substrate in CMOS?
A P-type substrate in CMOS allows constructing n-channel transistors with no additional
doping. So this is the main benefit because the doping is low, the electrons mobility is
higher, the gain is higher and the transistor’s switching speed is high.

Thus, this is all about an overview of a CMOS inverter that operates at high speed and uses
less power. These inverters have good logic buffer characteristics so, their noise margins
within both high & low conditions are large. Here is a question for you, what P-MOS
transistor?