Example: 4-bit Adder module
Design 4-bit module using 4 1-bit Adders
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2
Primitives
No declarations - can only be instantiated
Output port appears before input ports
Optionally specify: instance name and/or delay (discuss
delay later)
and N25 (Z, A, B, C); // name specified
and #10 (Z, A, B, X),
(X, C, D, E); // 2 gates, delay specified
and #10 N30 (Z, A, B); // name and delay specified
3
Review
module adder1 (s, cout, a, b, cin);
output s, cout;
input a, b, cin;
xor (t1, a, b);
xor (s, t1, cin);
and (t2, t1, cin),
(t3, a, b);
or (cout, t2, t3);
endmodule
4
5
module adder4 (sum, carry, inA, inB);
output [3:0] sum;
output carry;
input [3:0] inA, inB;
adder1 a0 (sum[0], c0, inA[0], inB[0], 1'b0);
adder1 a1 (sum[1], c1, inA[1], inB[1], c0);
adder1 a2 (sum[2], c2, inA[2], inB[2], c1);
adder1 a3 (sum[3], carry, inA[3], inB[3], c2);
endmodule
module adder1 (s, cout, a, b, cin);
output s, cout;
input a, b, cin;
xor (t1, a, b);
xor (s, t1, cin);
and (t2, t1, cin),
(t3, a, b);
or (cout, t2, t3);
endmodule
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Example: Combinational Gray code
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Example: Combinational Gray code
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Example: Combinational Gray code
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Example: Combinational Gray code
X=…., Y=…., Z=…, K=… ?
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Example: Combinational Gray code
X=…., Y=…., Z=…, K=… ?
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Example: Combinational Gray code
X=…., Y=…., Z=…, K=… ?
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Example: Combinational Gray code
X=…., Y=…., Z=…, K=… ?
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Example: Combinational Gray code
X=…., Y=…., Z=…, K=… ?
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Example: Combinational Gray code
X=A
Y
X Y Z K
HW!
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Four-Value Logic
A single bit can have one of FOUR possible values
0 Numeric 0, logical FALSE
1 Numeric 1, logical TRUE
x Unknown or ambiguous value
z No value (high impedence)
Why x?
Could be a conflict, could be lack of initialization
Why z?
Nothing driving the signal
Tri-states
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Four-Value Logic
A single bit can have one of FOUR possible values
0 Numeric 0, logical FALSE
1 Numeric 1, logical TRUE
x Unknown or ambiguous value
z No value (high impedence)
Why x?
Could be a conflict, could be lack of initialization
Why z?
Nothing driving the signal
Tri-states
17
Four-Value Logic
A single bit can have one of FOUR possible values
0 Numeric 0, logical FALSE
1 Numeric 1, logical TRUE
x Unknown or ambiguous value
z No value (high impedence)
Why x?
Could be a conflict, could be lack of initialization
Why z?
Nothing driving the signal
Tri-states
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The x and z Values
IN SIMULATION
Can detect x or z using special comparison operators
x is useful to see:
Uninitialized signals
Conflicting drivers to a wire
Undefined behavior
IN REAL HARDWARE (i.e. in synthesis) ?
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The x and z Values
IN SIMULATION
Can detect x or z using special comparison operators
x is useful to see:
Uninitialized signals
Conflicting drivers to a wire
Undefined behavior
IN REAL HARDWARE (i.e. in synthesis)
Cannot detect x or z as logical values
No actual ‘x’ – electrically just isn’t 0, 1, or z
Except for some uninitialized signals, x is bad!
Multiple strong conflicting drivers => short circuit
Weak signals => circuit can’t operate, unexpected results
z means nothing is driving a net (tri-state)
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Resolving 4-Value Logic (Boolean Algebra)
S
A A A T OUT
OUT OUT
B B B
A B OUT A B OUT S A T B OUT
0 0 0 0 0 0 0 0 z z z
0 1 1 0 1 0 0 1 z x x
1 1 1 1 1 1 0 x z 1 1
0 x x 0 x 0 0 z z 0 0
0 z x 0 z 0 1 0 0 1 x
1 x 1 1 x x 1 0 0 z 0
1 z 1 1 z x 1 1 1 z 1
1 x x z x
1 z x 0 x
OUT A 0 1 x z
A
OUT 1 0 x x
Z’s often appear in simulation when you forget to connect an input port of a module 21
Resolving 4-Value Logic (Boolean Algebra)
S
A A A T OUT
OUT OUT
B B B
A B OUT A B OUT S A T B OUT
0 0 0 0 0 0 0 0 z z z
0 1 1 0 1 0 0 1 z x x
1 1 1 1 1 1 0 x z 1 1
0 x x 0 x 0 0 z z 0 0
0 z x 0 z 0 1 0 0 1 x
1 x 1 1 x x 1 0 0 z 0
1 z 1 1 z x 1 1 1 z 1
1 x x z x
1 z x 0 x
OUT A 0 1 x z
A
OUT 1 0 x x
Z’s often appear in simulation when you forget to connect an input port of a module 22
Hierarchy
Build up a module from smaller pieces
Primitives and other modules
Can mix/match Verilog coding models (structural, etc.)
Design: typically top-down
Verification: typically bottom-up
Full Adder Hierarchy Add_full
Add_half Add_half or
xor and xor and
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Add_half Module
Add_half
xor and
module Add_half(c_out, sum, a, b);
output sum, c_out;
input a, b;
xor sum_bit(sum, a, b);
and carry_bit(c_out, a, b);
endmodule
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Add_half Module
Add_half
xor and
module Add_half(c_out, sum, a, b);
output sum, c_out;
input a, b;
xor sum_bit(sum, a, b);
and carry_bit(c_out, a, b);
endmodule
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Add_full Module
Add_full
Add_half Add_half or
module Add_full(c_out, sum, a, b, c_in) ;
output sum, c_out;
input a, b, c_in;
wire w1, w2, w3;
Add_half AH1(.sum(w1), .c_out(w2), .a(a), .b(b));
Add_half AH2(.sum(sum), .c_out(w3), .a(c_in), .b(w1));
or carry_bit(c_out, w2, w3);
endmodule
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Add_full Module
Add_full
Add_half Add_half or
module Add_full(c_out, sum, a, b, c_in) ;
output sum, c_out;
input a, b, c_in;
wire w1, w2, w3;
Add_half AH1(.sum(w1), .c_out(w2), .a(a), .b(b));
Add_half AH2(.sum(sum), .c_out(w3), .a(c_in), .b(w1));
or carry_bit(c_out, w2, w3);
endmodule
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Top module
module topadd (c_out, sum, a, b, c_in);
output sum, c_out;
input a, b, c_in;
assign a = 1, b = 0, c_in = 1;
Add_full AD(c_out, sum, a, b, c_in) ;
initial begin
$monitor($time, ,"a=%b, b=%b, c_in=%b, c_out=%b, sum=%b", a, b, c_in, c_out, sum);
end
endmodule
module Add_full(c_out, sum, a, b, c_in) ;
output sum, c_out;
input a, b, c_in;
wire w1, w2, w3;
Add_half AH1(.sum(w1), .c_out(w2), .a(a), .b(b));
Add_half AH2(.sum(sum), .c_out(w3), .a(c_in), .b(w1));
or carry_bit(c_out, w2, w3);
endmodule
module Add_half(c_out, sum, a, b);
output sum, c_out;
input a, b;
xor sum_bit(sum, a, b);
and carry_bit(c_out, a, b);
endmodule 28
