Flexible H-tree and Multi-Tap Clock Flow

in Innovus (Legacy)

Product Version 20.10

September, 2020
Copyright Statement

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registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective
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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Contents
Purpose ....................................................................................................................... 5
Audience...................................................................................................................... 5
Terminology ................................................................................................................. 5
Overview...................................................................................................................... 6
Cross corner scaling ................................................................................................ 6
Insertion delay reduction .......................................................................................... 7
Flexible H-tree .......................................................................................................... 7
Mesh ....................................................................................................................... 8
Multi-tap with H-tree ................................................................................................. 8
Multi-tap without flexible H-tree or with mesh ......................................................... 10
Tradeoffs ................................................................................................................ 10
H-tree with multi-tap CTS flow – overview ................................................................. 12
H-tree with multi-tap CTS flow – step by step ........................................................... 15
Initial pre-CTS DB .................................................................................................. 15
H-tree route type .................................................................................................... 16
H-tree DRV constraints .......................................................................................... 16
H-tree definition ...................................................................................................... 17
H-tree synthesis ..................................................................................................... 18
Multi-tap debug ...................................................................................................... 20
Multi-tap CTS ......................................................................................................... 21
H-tree setup ............................................................................................................... 22
Mandatory parameters ........................................................................................... 22
Sink grid ................................................................................................................. 22
Sinks without a grid and additional sinks................................................................ 24
Topology guide....................................................................................................... 24
Symmetry buffers ................................................................................................... 25
Distance mode ....................................................................................................... 26
Image debug output ............................................................................................... 27
Multi-tap CTS setup ................................................................................................... 29
Clock tree source groups ....................................................................................... 29
Multi-driver clock mesh nets ................................................................................... 30
Multi-tap allocation cloning control ......................................................................... 30
Overriding tap allocation ........................................................................................ 30
Multi-tap allocation reporting .................................................................................. 31
Cluster run recommendation .................................................................................. 31
Related documentation .............................................................................................. 32
Summary ................................................................................................................... 32
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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Support ...................................................................................................................... 32
Feedback ................................................................................................................... 32

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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Purpose
A structured top of tree clock distribution scheme is typically deployed to improve cross
corner scaling in combination with large drivers and top of stack low RC delay routing
layers to reduce clock latency. The most common such structures are the H-tree and an
H-tree driving a clock mesh. The Innovus Flexible H-Tree feature provides the
electrically symmetric buffering and balanced wire length benefits of an H-tree, but
relaxes the requirement to be geometrically symmetric, enabling automated synthesis
even in floorplans with placement restrictions. Multi-Tap Clock Tree Synthesis, also
known as Multi-Source Clock Tree Synthesis, is fully integrated with the Flexible H-tree
feature and extends regular clock synthesis to provide local buffering and balancing
between the structured top of tree and the clock sinks.

Audience
This document is targeted at Innovus 1 users who want to deploy flexible h-trees and
multi-tap clock tree synthesis (CTS). It is assumed that such users are experienced with
Innovus and are familiar with Innovus CTS 2 configuration. Further information on CTS
configuration can be found in the Design Implementation Capabilities – Clock Tree
Synthesis section of the Innovus User Guide.

Terminology
Acronym or term Explanation
CCOpt Clock Concurrent Optimization
CTD Clock Tree Debugger
CTS Clock Tree Synthesis
ECF Early Clock Flow
NDR Non-Default Rule
OCV On Chip Variation
QOR Quality of Result
Clock tree spec Clock tree specification consisting of clock tree and skew group definitions
and related settings
Clock tree source A set of logically equivalent physically distinct clock tree roots,
group corresponding to the output pins of multiple tap drivers
Insertion delay Clock latency
H-tree Frequently used to mean Innovus Flexible H-tree
H-tree sink A leaf cell instance in an H-tree
Tap driver / Tap A driving cell at the root of a sub-tree for multi-tap CTS. In an H-tree with
multi-tap CTS flow, these cells are also the H-tree sinks.

1 This version of the document is written using the Legacy User Interface syntax. Future versions of this
document may additionally include or switch to the Stylus User Interface syntax.
2 Unless expressly indicated otherwise, the product features and recommendations described within this

document apply to all CTS flows, namely plain CTS (ccopt_design -cts), low, medium and extreme
effort CCOpt flows (ccopt_design), and to the Early Clock Flow.
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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Overview
This section provides an overview of the potential benefits of using a flexible H-tree, the
necessity and implications of multi-tap CTS, and comments on the tradeoffs involved.

Cross corner scaling

Figure 1 depicts a clock tree synthesized with regular CTS, which has been balanced
primarily considering a slow corner. For the purposes of illustration, the tree is loosely
divided into upper and lower sections. Regular CTS achieves a balanced tree via a mix
of cell insertion, sizing and wire length adjustment that may take place in both upper
and lower sections of the tree. When timed in a fast corner, the delays of different cell
sizes or cell types (for example, buffer as against clock gate) may scale differently to
one another and differently to the RC delay of the connecting wires, leading to skew.
Depending on the locality of timing paths and the purpose of the delay corners, this can
lead to harder setup and/or hold timing closure. This effect is especially significant for
power sensitive applications that have a wide range of operating voltages.

clock
latency

Slow corner Fast corner

Figure 1 - Cross corner scaling without H-tree

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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Figure 2 depicts the same clock tree with an H-tree. The top of tree is electrically
symmetric and maintains nearly perfect skew over all delay corners and thus, the skew
at the sinks is correspondingly reduced in the fast corner.

clock
latency

Slow corner Fast corner

Figure 2 - Cross corner scaling with an H-tree

Insertion delay reduction

An H-tree is often able to use top routing layer resources (for example, M11/M12 on a
7nm process) shared with power distribution and ‘over the block’ signal pre-routes. The
availability of routing tracks is typically such that regular CTS trunk or top nets may be
sufficiently unstructured or numerous to reliably use these tracks. Further, without the
sinks, gating and logic complexity present in a regular tree, an H-tree can exploit larger
drivers to drive significant distances in these top routing layers. The combination of
larger drivers and low RC routing layers reduces the non-common path clock insertion
delay, potentially increasing the performance.

Flexible H-tree
The Innovus flexible H-tree feature enables an H-tree to be synthesized even in designs
containing placement blockages such as memories or macros. H-tree synthesis
maintains electrical symmetry but need not mandate geometrical symmetry. However,
with an unblocked rectangular floorplan and a regular grid of sinks, the resulting H-tree
will typically be both electrically and geometrically symmetrical.

A traditional H-tree, due to the geometric symmetry, places a constraint on the number
of H-tree sinks (tap drivers) and the location of these sinks. The Innovus flexible H-tree
feature avoids this restriction, but with uneven H-tree sink distributions, to remain
electrically symmetrical, many sinks may have additional delay in their path to ensure
electrical symmetry. In general, a more geometrically complicated H-tree is likely to
incur additional insertion delay to maintain electrical symmetry.

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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Mesh 3

A further performance increase may be achieved by shorting the outputs of the H-tree
together with a mesh. This has the advantage of reducing the non-common path clock
insertion delay further but at the expense of additional power, routing resource, and
design work. Wire has resistance and therefore, a mesh is not a perfect shorting net.
Design work is required to both implement the mesh as well as characterize the impact
of the H-tree device variation and mesh wire geometry on the mesh skew and power.

Multi-tap with H-tree

An H-tree alone is not a complete solution. Regular CTS is required to complete the
buffering and balancing required between the sinks of the H-tree and the clock sinks
(typically flip-flops). Figure 3 illustrates the logical structure. The root pin, which may be
a cell instance or an external input port, provides the signal to be distributed via the H-
tree. The output pins of the H-tree sinks (in red), serve as multiple sources for multi-tap
CTS, which will synthesize the sub-trees underneath each tap.

H-tree
root pin

H-tree
drivers

H-tree sinks
/ Tap drivers

Multi-tap
sub-trees

Figure 3 - H-tree with multi-tap CTS

3 A future version of this document will discuss clock mesh handling in Innovus.
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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

The step of tap allocation, part of CTS and available as a separate command to aid
debugging, determines which clock sinks are to be in which multi-tap sub-tree. Clock
gating or clock logic common to multiple sinks must be cloned if the sinks are allocated
to different taps. Figure 4 depicts the physical layout of an H-tree along with two sinks A
and B. Buffering and balancing cells are omitted for clarity. Prior to tap allocation, A and
B sinks share a common clock gate.

A A G

G G
B B

Figure 4 - Multi-tap without and with cloning

Without cloning, both sinks continue to share the same clock gate and must be
allocated to the same tap, resulting in additional delay and resource usage from
buffering and routing. With cloning, sinks are allocated to a tap appropriate to their
location and clock gating. In this example, the clock gate is cloned. A common
debugging scenario is when, for example, multi-tap CTS is unable to clone a clock gate
or clock logic, because the user has instructed that one or more clock gates are “don’t
touch”.

Cloning incurs a clock area and associated power cost, and adds additional clock gating
enable fanout into the datapath. Without cloning, or without sufficient cloning, some taps
may have significantly higher under-the-tap insertion delay than others. Any such
imbalance between taps is corrected by CTS skew balancing, which will cost additional
resources and potentially increases the non-common path latency between sinks.

Innovus multi-tap allocation aims to minimize the amount of cloning by internally using a
clustering like algorithm. If needed, the user can adjust the tradeoff between the
increase in the number of clock gates and the likely imbalance of insertion delay
between taps.

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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Multi-tap without flexible H-tree or with mesh

Innovus multi-tap CTS can be used independently of the flexible H-tree feature. The
user is required to supply a list of preexisting tap driver output pins or use a provided
utility command to insert them. This permits deployment with custom top of tree
structures such as spines or a clock mesh. Further details on configuring multi-tap CTS
will be provided later.

Tradeoffs
There are multiple tradeoffs involved in deciding to use an H-tree. Many of these are
design dependent and are outside the scope of this document but three important
considerations are:

• Is the clock architecture suited to an H-tree?

An architecture with multiple levels of clock logic, or multiplexors between many
clocks, perhaps with re-convergence, is unlikely to present a single logical point
into which an H-tree could be inserted. If such a logical point does exist, it might
entail an extensive cloning of that logic. Note that the user must specify the
precise point, at a named cell output pin or input port, where an H-tree is
inserted.

• Will an H-tree help design goals?

As discussed earlier, the main benefits of an H-tree are improved cross corner
skew resulting from improved cross corner scaling and the potential for insertion
delay reduction. The cost, beside additional flow steps and setup, is the
necessity of dividing the lower portion of the tree into sub-trees including the cost
of cloning clock gates and clock logic. Improved cross corner scaling and/or
insertion delay reduction does not necessarily translate into design timing or
power advantages.

• Are physical resources available to insert an H-tree?

Routing resources in top layer metal are needed to realize the insertion delay
and tight skew benefits of an H-tree. If there are too few routing tracks available,
H-tree nets may be detoured or unrouteable. Placement locations are needed for
H-tree buffers and sinks. While the flexible H-tree feature copes with placement
blockages, macro obstructions, and rectilinear floorplans, inserting an H-tree into
a thin channel style design with many H-tree sinks is unlikely to offer any
significant design benefit.

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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Another related consideration is:

• How many tap drivers?

This is a complex design-dependent trade off involving amongst others:
improvement in cross corner scaling and insertion delay, cost of cloning, locality
or lack of locality of critical timing paths, floorplan, and the number of levels of
clock gating present underneath the H-tree.

For high performance CPU/GPU cores, an H-tree may be of benefit, and users are
typically using up to 32 tap H-trees. For system-on-a-chip style blocks that are power
sensitive with lower performance requirements, an H-tree may be of limited advantage
or even a disadvantage. For other design styles, it may be necessary to explore and
compare flows both with and without an H-tree.

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H-tree with multi-tap CTS flow – overview

Figure 5 depicts the typical H-tree with multi-tap CTS flow.

Pre-CTS DB

create_ccopt_clock_tree_spec

… standard CTS configuration here ...

Top routing rule NDR

create_route_type … -shield_net …
set_ccopt_property –net_type top …

H-tree transition constraint set_ccopt_property target_max_trans –

net_type top …

Define H-tree(s) create_ccopt_flexible_htree …

[create_ccopt_flexible_htree …] H-tree
debug

Build/Debug H-tree(s) synthesize_ccopt_flexible_htrees …

Multi-tap
Tap assignment debug [assign_clock_tree_source_groups] debug

Multi-tap CTS ccopt_design [-cts]

Figure 5 - H-tree with multi-tap CTS flow

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The additional requirements to the standard CTS flow are:

• Configuration of a route-type for use with H-tree nets. H-tree synthesis uses the
top net type 4.

• Configuration of a transition constraint for H-tree synthesis

• Defining H-tree(s). Definition is performed by creating one or more

flexible_htree objects, each of which represents a yet to be synthesized H-
tree.

• Synthesizing the H-tree(s). This step will build the H-trees, detail route the H-
trees, and update the in-memory clock tree spec for multi-tap CTS to be run. The
synthesize_ccopt_flexible_htrees -dry_run command can be used
to debug and view what H-tree synthesis will do without modifying the design
database.

• Optionally checking tap assignment using the

assign_clock_tree_source_groups command. This step, intended for
debugging during initial setup, performs assignment of sinks to taps along with
cloning, but does not place cloned cells or perform any buffering. This is useful to
identify un-cloneable cells that will otherwise result in inferior CTS results later.
Once the initial setup is debugged, this step can be removed. This step can be
left in place prior to running CTS without harm.

• Multi-tap CTS / CCOpt is invoked in the normal way. The clock tree spec
modifications made by H-tree synthesis instruct CTS to perform multi-tap
allocation as required.

Further details of each of the above steps are provided in the next section.

If using the Innovus Early Clock Flow (ECF), for production, H-tree synthesis is best
performed before running place_opt_design. Multi-tap allocation will be performed
internally to place_opt_design when Innovus performs a fast CTS to estimate clock
timing and resource requirements. Such a flow is depicted in Figure 6 5. For debugging,
note that prior to place_opt_design, the sinks (flops) will be unplaced and therefore,
the assign_clock_tree_source_groups command may not be used. Debugging
of tap allocation must be performed on a placed design.

4 Refer to the Design Implementation Capabilities – Clock Tree Synthesis section of the Innovus User

Guide for information on top, trunk and leaf net types.

5 As should be apparent by comparing Figure 5 and Figure 6, the additional steps to add H-tree synthesis

and multi-tap CTS into the flow are largely independent of the choice of the flow. The ECF will not be
discussed further in this document except where explicit differences arise.
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The ECF enables Innovus to measure and optimize for the impact of multi-tap CTS
clock gate cloning earlier in the flow when more powerful optimization transforms such a
pre-CTS skewing, critical path placement changes, and multi-bit flop optimization are
available.
Pre-CTS DB

create_ccopt_clock_tree_spec

… early clock flow & CTS configuration here ...

Top routing rule NDR

create_route_type … -shield_net …
set_ccopt_property –net_type top …

H-tree transition constraint set_ccopt_property target_max_trans –

net_type top …

Define H-tree(s) create_ccopt_flexible_htree …

[create_ccopt_flexible_htree …] H-tree
debug

Build/Debug H-tree(s) synthesize_ccopt_flexible_htrees …

place_opt_design

Multi-tap CTS ccopt_design [-cts]

Figure 6 - H-tree with multi-tap CTS and early clock flow

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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

6
H-tree with multi-tap CTS flow – step by step
This section expands on the previous overview with a step-by-step illustration of the
commands, netlist state, and clock tree spec7 state at each step. Detailed explanation of
available configuration parameters will be covered later.

Initial pre-CTS DB
Assume the initial pre-CTS DB state is with all the unbuffered pre-CTS trees connected
directly to the clock root pin. A single SDC create_clock -name ck [get_ports
{ck}] results in a clock tree spec generated by create_ccopt_clock_tree_spec,
containing one clock tree and one skew group with the same name.

clock_tree ck
skew_group ck

G1 G2

Figure 7 - Pre-CTS unbuffered tree

Standard CTS configuration is not discussed in this document. Typically, such

configuration will consist of specifying route types, buffer, inverter and clock gating cell
lists, and transition targets, possibly combined with clock spec modifications. H-tree
synthesis does not concern itself with the majority of the clock spec setup except for the
configuration items noted in this section. H-tree synthesis requires that the H-tree root
pin is part of a clock tree definition included in the clock tree spec, and except in an
unusually heavily customized setup, this will be true in the automatically generated spec
from create_ccopt_clock_tree_spec.

6 A Rapid Adoption Kit (RAK) for the flexible H-tree feature is under development. This will provide a

hands-on style tutorial with example scripts and database. This may be included in a future version of this
document or made available separately.
7 Refer to the Design Implementation Capabilities – Clock Tree Synthesis section of the Innovus User

Guide for information on clock tree and skew group definitions within the clock tree spec.
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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

H-tree route type

H-tree synthesis uses the top net type 8. Define a suitable route type and then assign it
to the top net type.

Example:

> create_route_type 9 -name htree_route -top_preferred_layer M12

-bottom_preferred_layer M11 -non_default_rule NDR_htree -
shield_net vss

> set_ccopt_property route_type htree_route -net_type top

The recommendation is to use the highest possible routing layers and wider than default
width in lower layers. Shielding is usually desirable unless the H-tree nets are otherwise
adjacent to a power grid. The NDR should specify multiple cuts per via, or the H-tree
driver cell should be configured with via pillar rules. 10

H-tree DRV constraints

By default, H-tree synthesis will build an electrically symmetric H-tree with as many
levels of driver as required to respect the following DRV constraints:

• Top net type target max transition or default CTS target max transition.

• Applicable SDC set_max_capacitance constraints

• Cell library (Liberty) max capacitance and transition constraints

• The setting of get_ccopt_property max_source_to_sink_net_length

8 Note that the top net type may also be configured for use by CTS including for use with multi-tap CTS
underneath the H-tree. However, this top net type is shared between both uses so care is required in the
configuration.
9 Refer to the Innovus Command Reference guide or the man page for further information on the

create_route_type command and NDR definition.

10 See the set_via_pillars command and consult the Innovus User Guide or Cadence support for

information on via pillar setup.

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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

It is recommended to set the top net target max transition.

Example:

> set_ccopt_property target_max_trans 150ps -net_type top

If the top net target max transition has not been set, H-tree synthesis will default to
using the same transition target as set for all net types with set_ccopt_property
target_max_trans.

Alternatively, H-tree synthesis can be directed to ignore DRV and target a max length
constraint instead. This mode is useful for debugging and is discussed later.

H-tree definition
H-tree definition is performed by creating a flexible_htree object containing the
intended specification for the H-tree. Multiple H-trees may be configured prior to
synthesis. During synthesis, the routing of all H-trees is performed in the same step thus
reducing run-time.

The following example defines an H-tree:

> create_ccopt_flexible_htree
-name myhtree
-pin ck
-trunk_cell CLKBUFX32
-final_cell CLKBUFX20
-sink_grid {4 3}
-sink_grid_box {300 300 2700 1900}
-image_directory htree_debug

The H-tree is named myhtree and the root pin is specified as ck, the design input port
name in this example. The H-tree drivers will be instances of CLKBUFX32 and the H-
tree sinks that will be instances of CLKBUFX20. Very large drivers may be appropriate
for driving across the H-tree itself but may not be appropriate, or at least required for
driving the multi-tap sub-trees. Inverters or buffers may be specified. The H-tree will
have a 4x3 (x-axis by y-axis) grid of sinks positioned within the rectangle {300 200
2700 1900} (x-min y-min x-max y-max). If the grid bounding box is omitted, the entire
floorplan will be considered.

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Exactly where the H-tree sinks should be located depends on the design and floorplan.
Generally, it will be sensible to ensure no clock sink (that is, flop or macro clock pin
input) is too far away from an H-tree sink, and that H-tree sinks are not too sparsely
located in areas of high clock sink density. The objective is to avoid any one sub-tree
from dominating the insertion delay underneath the H-tree.

To facilitate debugging, the optional -image_directory can be used to specify a

directory into which PNG image files are written during synthesis. This is especially
useful when combined with the -dry_run feature that will be discussed shortly.

Note that defining a flexible_htree object with the

create_ccopt_flexible_htree command does not modify the netlist. The
flexible_htree object definitions are saved as part of the design DB with
saveDesign. Correspondingly, the delete_ccopt_flexible_htrees command
can be used to delete flexible H-tree object definitions. This command will not remove
any existing H-tree from the netlist or modify the netlist.

H-tree synthesis
Once the H-tree definitions are complete, synthesis is invoked.

Example:

> synthesize_ccopt_flexible_htrees
[-dry_run] [-use_estimated_routes]

By default, synthesis will insert the H-tree into the netlist, place and legalize driver and
sink cells, and invoke the detailed router to route the H-tree nets. Wires of the routed H-
tree nets are marked FIXED so that the later flow steps do not adjust them. Typically,
the fanout of the H-tree will remain connected at the output of only one of the H-tree
sinks. Exceptions are made if the preexisting sinks are specified and are subject to
fence constraints.

The clock tree specification will be updated to include the generated clock tree
definitions and a clock tree source group at the output pins of the H-tree sinks. This
clock tree specification change instructs CTS to operate in a multi-tap aware manner.
Alternatively, the clock tree specification modifications can be written to a Tcl file using
-spec_file <filename> instead of updating the active spec in memory. If desired,
the spec modifications can then be loaded by sourcing the Tcl file.

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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Figure 8 illustrates the updated netlist and clock tree spec. Typically, the clock spec
modification is of little concern to the user. The skew group definitions that constrain
CTS are unchanged such that the single skew group ck continues to ensure all sinks
are balanced, even sinks that are later allocated to different taps. A non-constraining
(reporting only) skew group definition is added to facilitate reporting of the H-tree skew
and insertion delay. This skew group is sourced at the H-tree root pin with sinks at the
H-tree sink cell instances input pins.

create_ccopt_skew_group clock_tree ck
-name flexible_htree_myhtree/reporting_only
-constrains none -source ck -sinks {...} skew_group ck

clock_tree_source_group myhtree
G1 G2
generated clock_tree
flexible_htree_myhtree_0 ... _3

Figure 8 - Clock structure after H-tree synthesis

For debugging purposes, -dry_run can be specified to skip the netlist update, clock
spec update, and routing step, which is intended for use with the -image_directory
debug feature mentioned previously.

If a detail routed H-tree is not required (for example, to run multi-tap CTS during
debugging and development), this can be skipped by specifying -
use_estimated_routes to reduce run-time. Note though that H-tree nets will not be
detail routed during or after CTS.

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Multi-tap debug
The following command will assign sinks to tap drivers as specified by the clock tree
source group definitions (for example, those created automatically by H-tree synthesis).

> assign_clock_tree_source_groups

Tap allocation examines the clock sink placement, the clock structure including clock
gating, and the tap driver locations, and determines which sinks to assign to which taps.
Clock gating and clock logic is cloned as required to implement that allocation, but the
clones are not placed and CTS buffering is not performed. This is illustrated in Figure 9.

G1 G2 G1 G2 G2 cloned,
unplaced,
unbuffered

Figure 9 - Clock structure after tap assignment

Tap allocation is relatively fast compared to CTS. Thus, it is possible to quickly check
the quality of tap allocation, in particular check for nodes which are un-cloneable, the
number of sinks per tap, the radius of sinks assigned to each tap, and spot if any taps
will be unexpectedly unused.

This step is optional and is purely for debug purposes. The process of tap
allocation is repeated inside CTS where placement and buffering are additionally
performed. This step can remain in the flow before CTS or it can be removed.

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Multi-tap CTS
Multi-tap CTS is quite simply regular CTS / CCOpt. The multi-tap functionality is
enabled by the existence of one or more clock tree source groups (for example, those
created automatically by H-tree synthesis).

CTS will perform multi-tap assignment, cloning if required, and will place the clones as
part of regular CTS placement and buffering. Balancing will take place per the skew
group definitions. Typically, a single skew group will balance all sinks under the H-tree
together. This is illustrated in Figure 10.

G1 G2 G2 fully buffered and

balanced

G1 G2

Figure 10 - Clock structure after multi-tap CTS

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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

H-tree setup
The information provided to create_ccopt_flexible_htree can be divided into the
following categories: mandatory parameters, sink grid and/or sink specification, and
mode.

Mandatory parameters
-name <name> Name of the flexible H-tree to be defined
-pin <pin | port> Pin or port to form the root of the H-tree
-trunk_cell <cell> The library cell name to use for drivers inside the H-
tree. This can be a buffer cell or an inverter cell.
-final_cell <cell> The library cell name to use for sinks of the H-tree.
This can be a buffer cell or an inverter cell.

Sink grid
The following parameters are used to control the generation of a grid of H-tree sinks:

-sink_grid {columns rows} Optional. Specifies the number of columns and

rows in a grid of H-tree sinks. If not specified,
no sink grid is used and -sinks must be
specified (see below). Rows and columns are
automatically reversed to align with the aspect
ratio of the sink grid area, as per the next
parameter.
-adjust_sink_grid_ Optional, default true. If the set column and
for_aspect_ratio row counts are reversed as required such that
<true|false> the axis with more grid points is always the
axis with larger length.
-sink_grid_box {xmin ymin Optional. Specifies the area of the box that the
xmax ymax} sinks grid must cover. The default is full
floorplan.
-sink_grid_exclusion_zones Optional. Specifies a list of rectangles that are
{ {xmin ymin xmax ymax} excluded from the sink grid. It is not necessary
...} to specify areas covered by macros or
placement blockages. However, it is desirable
to exclude thin channels between large
macros if there is no need for H-tree sinks in
those channels. Note that only sinks are
excluded, not H-tree drivers or routing. The
default is no exclusion zones.

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-sink_grid_sink_area {width Optional. The size of a ‘search’ rectangle

height) centered around each computed sink grid
location. If a sink cannot be placed within this
rectangle, the sink is omitted. The default is
auto determined.
-sink_instance_prefix Optional. Specifies a name prefix for the leaf
<name> instance name of sink cells inserted, both via a
sink grid and via -sinks

Figure 11 illustrates how these parameters interact. A grid of 4x4 sinks is positioned
within the user specified grid bounding box. The combination of an exclusion zone and
placement blockages causes sinks to be omitted.

-sink_grid {4 4}
-sink_grid_sink_area { 200 200 }
- sink_grid_box { 300 300 2700 1900 }
- sink_grid_exclusion_zones { { 300 700 1500 1200 } }
-sink_instance_prefix tap -name ht

Vertical spacing/2
(2700, 1900)

200

300 tap_ht_5 tap_ht_9

200 tap_ht_12
tap_ht_2

Placement
Horizontal spacing/2 200 blockage

tap_ht_1 tap_ht_4 tap_ht_8 tap_ht_11

(1500, 1200)

Exclusion zone tap_ht_7

(300, 700)
400
Placement blockage
tap_ht_0 tap_ht_3 600 tap_ht_6

Horizontal spacing = sink box width/number of sink grid columns

(300, 300)
= 2400/4 = 600

Vertical spacing = sink box height/number of sink grid rows

= 1600/4 = 400
(0, 0)
Figure 11 - Flexible H-tree sink grid parameters
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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Sinks without a grid and additional sinks

Although a sink grid remains the most common method to specify sink locations, it is
possible to insert additional sinks at specified locations or to specify existing cell
instance input pins as sinks. Both methods can be combined with one another and with
the sink grid. For example, combining methods can be used to specify a grid of H-tree
sinks to be inserted and to add in some macro input pins.

-sinks {pin | {xmin A list of existing cell instance input pins and/or
ymin xmax ymax} ...} rectangular sink areas. If sink areas are specified
one sink is inserted into each unblocked rectangular
sink area.
-pin <pin | port> Pin or port to form the root of the H-tree.

Note: For large numbers of sinks, it is preferable to use a sink grid rather than
specifying individual sink areas for two reasons. Firstly, a regular spaced grid of sinks
leads to a more efficient H-tree due to the need for electrical symmetry. Secondly, the
synthesis algorithm internal exploits the regularity of a sink grid when determining the H-
tree topology.

Topology guide
It is possible to guide the H-tree topology by specifying a list-based grouping structure
to the -sinks parameter. The following example command requests that sinks A and B
are grouped together as are sinks C and D, as shown in Figure 12.

> create_ccopt_flexible_htree ... -sinks

{ { {xminA yminA xmaxA ymaxA} {xminB yminB xmaxB ymaxB} }
{ {xminC yminC xmaxC ymaxC} {xminD yminD xmaxD xmaxD} } }

A B C D

Figure 12 - H-tree topology guide

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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Symmetry buffers
Flexible H-tree synthesis will by default insert symmetry buffers (which might actually be
inverters) to ensure electrical symmetry. The example in Figure 13 contains two
symmetry buffers where three sinks are missing from a tree, which otherwise will be
expected to have eight 11. The symmetry buffers serve the purpose of ensuring a
balanced pin load and routing structure (that is, electrical symmetry).

symmetry buffers
sinks

Figure 13 – H-tree with symmetry buffers

To disable the use of symmetry buffers, use create_ccopt_flexible_htree ...

-no_symmetry_buffers. Disabling symmetry buffers will reduce the H-tree power in
exchange for a small increase in skew.

NOTE: The command option -no_symmetry_buffers has been changed to

-omit_symmetry in Innovus 20.1.

11This example is intended to illustrate the concept and does not necessarily illustrate the structure which
would be generated for a tree with five sinks.
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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Distance mode
As discussed earlier, flexible H-tree synthesis by default considers timing-based DRV
constraints, especially that of a target max transition time.

An alternative mode is to have H-tree synthesis respect a maximum distance constraint,

ignore DRV constraints including maximum transition and capacitance, and disable
delay optimization. The following parameters to create_ccopt_flexible_htree
can be used to enable this mode:

-mode {drv | distance} Specify distance to enable the distance based

mode. The default is drv.
-max_driver_distance Specify the maximum permitted total length of any
<value in um> net driven by an H-tree driver. Both -mode
distance and -max_driver_distance must
be specified together.
-max_root_distance Specify the maximum permitted total length of the
<value in um> net driven by the H-tree root pin. Defaults to the
max_driver_distance setting if not specified.

Note: The setting of get_ccopt_property max_source_to_sink_net_length is

still adhered to and will indeed take priority over -max_driver_distance if it is more
constraining.

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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Image debug output

To aid debugging, flexible H-tree synthesis can output PNG format image files that
represent the synthesis algorithm view of the floorplan, sink grid, and H-tree. When
combined with the -dry_run parameter, this permits rapid debug and tuning of the
configuration without updating the design database.

Example:

> mkdir debug

> create_ccopt_flexible_htree -image_directory debug ...
> synthesize_ccopt_flexible_htrees -dry_run
> ... view image files ...
> delete_ccopt_flexible_htrees *

Two image files are created.

1. <htree_name>_grid.png, for example Figure 14, which shows the floorplan

and sink grid.

Figure 14 - H-tee grid debug image <htree_name>_grid.png

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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

2. <htree_name>_tree.png, for example Figure 15, which includes the

proposed H-tree layout and driver locations.

Figure 15 - H-tree debug image <htree_name>_tree.png

Note: H-tree synthesis operates on an internal synthesis grid and all features are
aligned to that grid.

Figure 16 details the coloring scheme used in the image files. The image files are
written at a high resolution such that it is possible to zoom in to see the precise detail.

Color/Shape Purpose
white grid The synthesis grid
red Grid points that are blocked for trunk cell placement
orange Grid points that are blocked for final cell placement
red-orange Grid points that are blocked for both trunk and final cell placement
yellow circle Root pin
yellow cross Target location for an H-tree sink to be inserted
yellow rectangle Sink area, as per -sink_grid_sink_area or user specified
area with -sinks
brown rectangle Sink grid bounding box if -sink_grid_box is specified
green/blue Intended edges of the synthesized H-tree
(<htree_name>_tree.png only)
yellow dots H-tree drivers (<htree_name>_tree.png only)
Figure 16 - H-tee debugging image labelling scheme
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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Multi-tap CTS setup

Clock tree source groups
The multi-tap CTS functionality is enabled by the existence of one or more 12 clock tree
source groups within the clock tree spec. A clock_tree_source_group binds
together multiple clock_tree definitions and declares that those clock tree roots are
logically equivalent 13 and that sinks may be interchanged freely between them.
Correspondingly, the output of each tap driver within a group of tap drivers is given a
clock_tree definition, most typically a generated clock tree definition. This is to
ensure that the single shared skew_group will propagate through the tap drivers to all
sinks.

Flexible H-tree synthesis will update the clock tree spec by adding the appropriate
generated clock tree definitions and a clock tree source group as illustrated in Figure 8.
However, with custom top of tree structures where the user has inserted tap drivers
manually or with scripting, the user must configure a clock tree source group directly as
shown in Figure 17.

clock_tree ck
skew_group ck
Custom structure
above tap drivers

tap_0 tap_1 tap_2 tap_3

G1 G2 create_ccopt_generated_clock_tree create_ccopt_generated_clock_tree
-name tap_0 -source tap0/Y
-allow_unordered_definition
... -name tap_3 -source tap3/Y
-allow_unordered_definition

create_clock_tree_source_group -name tap_group

-clock_trees [get_ccopt_clock_trees tap_*]

Figure 17 - Multi-tap generated clock trees and clock tree source group

Using -allow_unordered_definition in
create_ccopt_generated_clock_tree_command permits the generated clock
trees to be defined in the middle of the existing clock tree, even if there are existing
generated clock tree definitions further down the tree in the fanout cones of the tap
drivers.

12 Most designs typically have a single clock tree source group, corresponding to a single high

performance functional mode clock.

13 Note that Innovus makes no attempt to verify that the multiple clock tree roots are in fact logically

equivalent. Specifying logically non-equivalent clock tree roots will typically result in a formal equivalence
verification failure because sinks will be moved from one root to another.
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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Multi-driver clock mesh nets

At present, a multi-driver net cannot be contained within the logical circuit covered by a
clock_tree definition 14. This dictates the use of non-generated clock trees at the
output of tap drivers driven by a mesh net 15.

Multi-tap allocation cloning control

The user can adjust the tradeoff between the increase in the number of clock gates from
cloning, the need for which was discussed earlier, and the likely imbalance of insertion
delay between taps.

This is performed with the clustering_source_group_max_cloned_fraction

property. The default setting is 0.2, which implies at most a 20% increase in the number
of clock gates. Smaller values can be used to further limit the amount of cloning but will
risk increasing the insertion delay under any one tap. For example, the following
command will change the limit to a maximum 5% increase in the number of clock gates:

> set_ccopt_property
clustering_source_group_max_cloned_fraction 0.05

Overriding tap allocation

It is possible to override tap allocation and force individual sinks to be assigned to
specific taps. This is performed using the force_clock_tree property. For example,
the following command will force the sink f1/CK to be assigned to the clock tree named
tap_1:

> set_ccopt_property force_clock_tree -pin f1/CK tap_1

Future Innovus versions may ease this restriction.

14

A future version of this document will discuss the configuration steps required to use a clock mesh in
15

more detail.
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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Multi-tap allocation reporting

Tap allocation, invoked with the assign_clock_tree_source_groups command or
integral to place_opt_design (ECF) or ccopt_design, reports in the log
information per clock tree source group regarding:

• Clock nodes (clock gating, clock logic or other) that are un-cloneable, and why.
These typically result in excessive insertion delay under one or more taps.
Alternatively, a message of the form, “There are no uncloneable nodes”,
will confirm that there are no restrictions on cloning. Note that un-cloneable
nodes are reported even if tap allocation does not actually need to clone the
node given the current settings and placement.

• The number of sinks allocated to each tap and the number of sinks that the user
had overridden to be assigned to specific taps

Cluster run recommendation

It is recommended to perform a cluster-only CTS run prior to invoking full CTS. CTS
clustering will buffer each sub-tree underneath the tap drivers to meet DRV constraints
but will not attempt to balance the sub-trees together. This is very helpful for checking
that the insertion delay under each sub-tree is approximately similar, or at least that
there are no sub-trees with excessive delay. In a full CTS run, balancing will downsize
and/or add delay to sub-trees to balance the skew, making it hard to know which sub-
trees are the real problem. The Clock Tree Debugger16 can be used to explore the
result.

Example:

> assign_clock_tree_source_groups

> set_ccopt_property balance_mode cluster

> ccopt_design -cts

> ctd_win

16See the Innovus User Guide and associated documentation for further information on using the Clock
Tree Debugger.
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 Flexible H-tree and Multi-Tap Clock Flow in Innovus

Related documentation
The following documents about clock tree synthesis and the clock tree debugger are
available:

• Chapters in the Innovus User Guide

o Design Implementation Flow
o Clock Tree Synthesis
o CCOpt Properties
• Chapters in the Innovus Text Command Reference
o Clock Tree Synthesis Commands
• Chapters in the Innovus Menu Reference
o Clock Menu (for information about the clock tree debugger)
• For CUI compatible CCOpt Flexible HTree flow, refer below article
o Article: Sample script to create CCOpt flexible HTree [click here]

Summary
This document provided a guide to the Innovus Flexible H-tree and multi-tap clock tree
synthesis capabilities. A flow overview and configuration details were provided.
Feedback from users of this functionality and feedback from readers of this document is
valued as these product features continue to evolve.

Support
Cadence Support Portal provides access to support resources, including an extensive
knowledge base, access to software updates for Cadence products, and the ability to
interact with Cadence Customer Support. Visit https://support.cadence.com.

Feedback
Email comments, questions, and suggestions to [email protected].

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