NOT Gate Design and Verification
Specification
[Link]
2023-07-18
Table of Contents
1. Abstract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Design Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1. Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2. Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.3. Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.4. Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4. PART 1: SystemVerilog Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.1. Verification Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.2. Test Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.2.1. Random Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.2.2. Corner Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.3. Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.4. Verification Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.4.1. Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.4.2. Transaction Class. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.4.3. Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.4.4. Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.4.5. Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.4.6. Scoreboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.4.7. Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.4.8. Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.4.9. Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.4.10. Top-level Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5. PART 2: UVM Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1. Verification Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2. Test Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2.1. Random Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2.2. Corner Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3. Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.4. Verification Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.4.1. Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.4.2. Transaction Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.4.3. Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.4.4. Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4.5. Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4.6. Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4.7. Scoreboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4.8. Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4.9. Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4.10. Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4.11. Top-level Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 1. Abstract
This document specifies the design and verification plan for a simple NOT gate implemented in
SystemVerilog, including a comprehensive testbench structure with coverage and a top-level
module. The document is divided into two parts: SystemVerilog verification and UVM-based
verification.
1
Chapter 2. Introduction
The NOT gate is a fundamental digital logic component that inverts its input. This specification
outlines the design and verification methodology for implementing and testing a NOT gate using
SystemVerilog and UVM.
2
Chapter 3. Design Specification
3.1. Overview
The NOT gate is designed to invert a single-bit input signal.
3.2. Interface
Signal Direction Description
in Input Input signal to be inverted
out Output Inverted output signal
3.3. Functionality
The NOT gate will invert the input signal according to the following truth table:
Input Output
0 1
1 0
3.4. Implementation
module not_gate (
input logic in,
output logic out
);
assign out = ~in;
endmodule
3
Chapter 4. PART 1: SystemVerilog
Verification
4.1. Verification Environment
The verification environment consists of the following components:
• Interface
• Transaction class
• Generator
• Driver
• Monitor
• Scoreboard
• Coverage
• Environment class
• Testbench module
• Top-level testbench module
4.2. Test Cases
4.2.1. Random Stimulus
Generate 100 random input vectors and verify the correct output for each.
4.2.2. Corner Cases
Ensure the following cases are covered:
• Input transition from 0 to 1
• Input transition from 1 to 0
• Stable input at 0
• Stable input at 1
4.3. Coverage
Functional coverage will be collected on both input and output signals, including cross coverage
between them.
4
4.4. Verification Components
4.4.1. Interface
interface not_gate_if;
logic in;
logic out;
modport dut (input in, output out);
modport tb (output in, input out);
endinterface
4.4.2. Transaction Class
class not_gate_transaction;
rand bit in;
bit out;
function void print();
$display("Input: %b, Output: %b", in, out);
endfunction
endclass
4.4.3. Generator
class not_gate_generator;
mailbox #(not_gate_transaction) gen2drv;
function new(mailbox #(not_gate_transaction) gen2drv);
this.gen2drv = gen2drv;
endfunction
task run();
not_gate_transaction tr;
repeat(100) begin
tr = new();
assert([Link]());
[Link](tr);
#2; // Wait for 2 time units
end
endtask
endclass
5
4.4.4. Driver
class not_gate_driver;
virtual not_gate_if.tb vif;
mailbox #(not_gate_transaction) drv_mbx;
function new(virtual not_gate_if.tb vif, mailbox #(not_gate_transaction) drv_mbx);
[Link] = vif;
this.drv_mbx = drv_mbx;
endfunction
task run();
not_gate_transaction tr;
forever begin
drv_mbx.get(tr);
[Link] <= [Link];
#1; // Wait for 1 time unit
end
endtask
endclass
4.4.5. Monitor
class not_gate_monitor;
virtual not_gate_if.tb vif;
mailbox #(not_gate_transaction) mon_mbx;
function new(virtual not_gate_if.tb vif, mailbox #(not_gate_transaction) mon_mbx);
[Link] = vif;
this.mon_mbx = mon_mbx;
endfunction
task run();
not_gate_transaction tr;
forever begin
tr = new();
@([Link] or [Link]);
[Link] = [Link];
[Link] = [Link];
mon_mbx.put(tr);
end
endtask
endclass
4.4.6. Scoreboard
class not_gate_scoreboard;
6
mailbox #(not_gate_transaction) mon_mbx;
int passes, fails;
function new(mailbox #(not_gate_transaction) mon_mbx);
this.mon_mbx = mon_mbx;
passes = 0;
fails = 0;
endfunction
task run();
not_gate_transaction tr;
forever begin
mon_mbx.get(tr);
if ([Link] == ~[Link]) begin
$display("PASS: Input = %b, Output = %b", [Link], [Link]);
passes++;
end else begin
$display("FAIL: Input = %b, Output = %b (Expected %b)", [Link], [Link],
~[Link]);
fails++;
end
end
endtask
function void report();
$display("Verification completed");
$display("Passes: %0d", passes);
$display("Fails: %0d", fails);
endfunction
endclass
4.4.7. Coverage
class not_gate_coverage;
covergroup not_gate_cg @(posedge in);
input_cp: coverpoint in {
bins zero = {0};
bins one = {1};
}
output_cp: coverpoint out {
bins zero = {0};
bins one = {1};
}
in_out_cross: cross input_cp, output_cp;
endgroup
function new();
not_gate_cg = new();
endfunction
7
endclass
4.4.8. Environment
class not_gate_env;
not_gate_generator gen;
not_gate_driver drv;
not_gate_monitor mon;
not_gate_scoreboard scb;
not_gate_coverage cov;
mailbox #(not_gate_transaction) gen2drv, drv_mbx, mon_mbx;
virtual not_gate_if.tb vif;
function new(virtual not_gate_if.tb vif);
[Link] = vif;
gen2drv = new();
drv_mbx = new();
mon_mbx = new();
gen = new(gen2drv);
drv = new(vif, drv_mbx);
mon = new(vif, mon_mbx);
scb = new(mon_mbx);
cov = new();
endfunction
task run();
fork
[Link]();
[Link]();
[Link]();
[Link]();
join_none
endtask
endclass
4.4.9. Testbench
module not_gate_tb (
not_gate_if dut_if
);
import not_gate_pkg::*;
not_gate_env env;
initial begin
env = new(dut_if.tb);
[Link]();
8
// Run simulation for a specific time or until $finish is called
#1000;
if ($time > 999) $display("Simulation timeout");
[Link]();
$finish;
end
endmodule
4.4.10. Top-level Testbench
`include "not_gate.sv"
`include "not_gate_if.sv"
`include "not_gate_pkg.sv"
`include "not_gate_tb.sv"
module not_gate_tb_top;
// Instantiate the interface
not_gate_if dut_if();
// Instantiate the DUT (Design Under Test)
not_gate dut (
.in(dut_if.in),
.out(dut_if.out)
);
// Instantiate the testbench
not_gate_tb tb (
.dut_if(dut_if)
);
// Optional: System tasks for simulation control
initial begin
$timeformat(-9, 2, " ns", 20);
$display("Simulation started");
end
// Optional: Waveform dumping
initial begin
$dumpfile("not_gate_tb_top.vcd");
$dumpvars(0, not_gate_tb_top);
end
endmodule
9
Chapter 5. PART 2: UVM Verification
5.1. Verification Environment
The verification environment consists of the following UVM components:
• Interface
• Transaction class
• Sequence
• Sequencer
• Driver
• Monitor
• Scoreboard
• Coverage
• Environment class
• Testbench module
• Top-level testbench module
5.2. Test Cases
5.2.1. Random Stimulus
Generate 100 random input vectors and verify the correct output for each.
5.2.2. Corner Cases
Ensure the following cases are covered:
• Input transition from 0 to 1
• Input transition from 1 to 0
• Stable input at 0
• Stable input at 1
5.3. Coverage
Functional coverage will be collected on both input and output signals, including cross coverage
between them.
5.4. Verification Components
10
5.4.1. Interface
interface not_gate_if;
logic in;
logic out;
modport dut (input in, output out);
modport tb (output in, input out);
endinterface
5.4.2. Transaction Class
class not_gate_transaction extends uvm_sequence_item;
rand bit in;
bit out;
function new(string name = "not_gate_transaction");
[Link](name);
endfunction
`uvm_object_utils_begin(not_gate_transaction)
`uvm_field_int(in, UVM_DEFAULT)
`uvm_field_int(out, UVM_DEFAULT)
`uvm_object_utils_end
function void print();
$display("Input: %b, Output: %b", in, out);
endfunction
endclass
5.4.3. Sequence
class not_gate_sequence extends uvm_sequence #(not_gate_transaction);
function new(string name = "not_gate_sequence");
[Link](name);
endfunction
`uvm_object_utils_begin(not_gate_sequence)
`uvm_object_utils_end
virtual task body();
not_gate_transaction tr;
repeat (100) begin
tr = not_gate_transaction::type_id::create("tr");
start_item(tr);
assert([Link]());
11
finish_item(tr);
end
endtask
endclass
5.4.4. Sequencer
class not_gate_sequencer extends uvm_sequencer #(not_gate_transaction);
`uvm_component_utils(not_gate_sequencer)
function new(string name, uvm_component parent);
[Link](name, parent);
endfunction
endclass
5.4.5. Driver
class not_gate_driver extends uvm_driver #(not_gate_transaction);
virtual not_gate_if.tb vif;
`uvm_component_utils(not_gate_driver)
function new(string name, uvm_component parent);
[Link](name, parent);
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
if (!uvm_config_db #(virtual not_gate_if.tb)::get(this, "", "vif", vif))
`uvm_fatal("NOVIF", "virtual interface must be set for: " + get_full_name() +
".vif")
endfunction
virtual task run_phase(uvm_phase phase);
not_gate_transaction tr;
forever begin
seq_item_port.get_next_item(tr);
[Link] <= [Link];
#1; // Wait for 1 time unit
seq_item_port.item_done();
end
endtask
endclass
5.4.6. Monitor
12
class not_gate_monitor extends uvm_component;
virtual not_gate_if.tb vif;
uvm_analysis_port #(not_gate_transaction) ap;
`uvm_component_utils(not_gate_monitor)
function new(string name, uvm_component parent);
[Link](name, parent);
ap = new("ap", this);
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
if (!uvm_config_db #(virtual not_gate_if.tb)::get(this, "", "vif", vif))
`uvm_fatal("NOVIF", "virtual interface must be set for: " + get_full_name() +
".vif")
endfunction
virtual task run_phase(uvm_phase phase);
not_gate_transaction tr;
forever begin
tr = not_gate_transaction::type_id::create("tr");
@([Link] or [Link]);
[Link] = [Link];
[Link] = [Link];
[Link](tr);
end
endtask
endclass
5.4.7. Scoreboard
class not_gate_scoreboard extends uvm_component;
uvm_analysis_imp #(not_gate_transaction, not_gate_scoreboard) analysis_port;
int passes, fails;
`uvm_component_utils(not_gate_scoreboard)
function new(string name, uvm_component parent);
[Link](name, parent);
analysis_port = new("analysis_port", this);
passes = 0;
fails = 0;
endfunction
virtual function void write(not_gate_transaction tr);
if ([Link] == ~[Link]) begin
`uvm_info("PASS", $sformatf("Input = %b, Output = %b", [Link], [Link]), UVM_LOW)
passes++;
13
end else begin
`uvm_error("FAIL", $sformatf("Input = %b, Output = %b (Expected %b)", [Link],
[Link], ~[Link]))
fails++;
end
endfunction
function void report_phase(uvm_phase phase);
`uvm_info("RESULTS", $sformatf("Passes: %0d, Fails: %0d", passes, fails),
UVM_NONE)
endfunction
endclass
5.4.8. Coverage
class not_gate_coverage extends uvm_subscriber #(not_gate_transaction);
covergroup not_gate_cg @(posedge [Link]);
input_cp: coverpoint [Link] {
bins zero = {0};
bins one = {1};
}
output_cp: coverpoint [Link] {
bins zero = {0};
bins one = {1};
}
in_out_cross: cross input_cp, output_cp;
endgroup
`uvm_component_utils(not_gate_coverage)
function new(string name, uvm_component parent);
[Link](name, parent);
not_gate_cg = new();
endfunction
virtual function void write(not_gate_transaction tr);
not_gate_cg.sample();
endfunction
endclass
5.4.9. Environment
class not_gate_env extends uvm_env;
not_gate_sequencer sqr;
not_gate_driver drv;
not_gate_monitor mon;
not_gate_scoreboard scb;
not_gate_coverage cov;
14
virtual not_gate_if.tb vif;
`uvm_component_utils(not_gate_env)
function new(string name, uvm_component parent);
[Link](name, parent);
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
sqr = not_gate_sequencer::type_id::create("sqr", this);
drv = not_gate_driver::type_id::create("drv", this);
mon = not_gate_monitor::type_id::create("mon", this);
scb = not_gate_scoreboard::type_id::create("scb", this);
cov = not_gate_coverage::type_id::create("cov", this);
if (!uvm_config_db #(virtual not_gate_if.tb)::get(this, "", "vif", vif))
`uvm_fatal("NOVIF", "virtual interface must be set for: " + get_full_name() +
".vif")
uvm_config_db #(virtual not_gate_if.tb)::set(this, "drv", "vif", vif);
uvm_config_db #(virtual not_gate_if.tb)::set(this, "mon", "vif", vif);
endfunction
virtual function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
drv.seq_item_port.connect(sqr.seq_item_export);
[Link](scb.analysis_port);
[Link](cov.analysis_export);
endfunction
endclass
5.4.10. Testbench
class not_gate_test extends uvm_test;
not_gate_env env;
not_gate_sequence seq;
`uvm_component_utils(not_gate_test)
function new(string name, uvm_component parent);
[Link](name, parent);
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
env = not_gate_env::type_id::create("env", this);
seq = not_gate_sequence::type_id::create("seq");
endfunction
virtual task run_phase(uvm_phase phase);
15
phase.raise_objection(this);
[Link]([Link]);
#1000;
if ($time > 999) `uvm_error("TIMEOUT", "Simulation timeout");
phase.drop_objection(this);
endtask
endclass
5.4.11. Top-level Testbench
`include "not_gate.sv"
`include "not_gate_if.sv"
`include "not_gate_pkg.sv"
module not_gate_tb_top;
// Instantiate the interface
not_gate_if dut_if();
// Instantiate the DUT (Design Under Test)
not_gate dut (
.in(dut_if.in),
.out(dut_if.out)
);
// Instantiate the UVM test
initial begin
run_test("not_gate_test");
end
// Optional: System tasks for simulation control
initial begin
$timeformat(-9, 2, " ns", 20);
$display("Simulation started");
end
// Optional: Waveform dumping
initial begin
$dumpfile("not_gate_tb_top.vcd");
$dumpvars(0, not_gate_tb_top);
end
endmodule
16
Chapter 6. Conclusion
This specification outlines the complete design and verification plan for a NOT gate using
SystemVerilog and UVM. The verification strategy includes a combination of directed and random
test cases, functional coverage, and a comprehensive testbench environment.
17
