f Unit -1 IC Technologies, MOS & Bi CMOS Circuits VLST Oy laseye ACA dyke tao Oe j C d INTRODUCTION TO 1C TECHNOLOGY The development of elect onics endless with invention of vaccum tubes and associated electronic citeits. This activity termed as vaccum tube electronics, afterward the evolution of solid state devices and consequent development of integrated circuits are responsible for the present status of communication, computing and instrumentation, + The first vaccum tube diode was invented by john amb ase Fleming in 1904, + The vaccum triode was invented by lee de forest in 1906, Early developments of the Integrated Circuit (IC) zo back to 1949. German engineer Wemer Jacobi filed a patent for an IC like semiconductor amplifying devi showing five transistors on a common substrate in a 2-stage amplifier arrangement, Jacobi disclosed small cheap of hearing aids. Integrated circuits were made possible by experimental discoveries which showed that semiconductor devices could perform the functions of vacuum tubes and by mid-20th-century technology advancements in semiconductor device fabrication. The integration of large numbers of tiny transistors into a small chip was an enormous improvement over the manual assembly of circuits using electronic components. The integrated circuits mass production capability, reliability, and building-block approach to circuit design ensured the rapid adoption of standardized ICs in place of designs using discrete transistors, An integrated circuit (IC) is a small semiconductor-based electronic dev ce consisting of pacitors. Integrated circuits are the building blocks of most electronic devices and equipment. An integrated circuit is also known as a chip or microchip. fabricated transistors, resistors and ‘There are two main advantages of ICs over discrete circuits: cost and performance. Cost is ow because the chips, with all their components, are printed as a unit by photolithography rather ‘han being constructed one transistor ata time. Furthermore, much less material is used to construct a packaged IC die than a discrete cireit, Performance is high since the components switch quickly and consume little power (compared to their discrete counterparts) because the components are small and positioned close together. As of 2006, chip areas range from a few square millimeters to around 350 mm?, with up to | million transistors per mm. © scanned with OKEN Scanneri arge expensive, power Fleming ‘Vacuum tube diode large x pene po Vacuum triode William Shockley ‘Semiconductor replacing (Bell labs) vacuum tube f Bardeen and Point Contact transfer _ | Driving factor of growth o! Brattain and the VLSI technology [Shockley (Belt Inbs)} resistance device “BJT” Werner Jacobi VIC containing amplifying| No commercial use reported (Siemens AG) Device 2stage amplifier ‘Shockley 1951 ‘Junction Transistor “Practical form of transistor” Jack Kilby | July 1958 | Integrated Cireui Father of IC design With 2-T Germa (Texas and gold wires Instruments) Noyce Fairchild | Dec. 1958 | Integrated Cireuits Silicon Semiconductor “The Mayor of Silicon 2 Valley" Kahng Bell Lab | 1960 First MOSFET. Start of new era for semiconductor industry r Fairchild | 1061 First Commercial Semiconductor And Texas Ic Frank Wanlass 1963 (Fairchild Ser mnductor) Federico Faggin Silicon gate IC technology | Later Joined Intel to lead eactiaa first CPU Intel 4004 in 1970 es oi conductor) 2300 T on 9mm. Zarlink Recently ‘M2A capsule for take photographs of Semiconductors endoscopy digestive tract 2/sec. pe © scanned with OKEN Scannerwologies, MOS & Bi CMOS Circuits NES MOS & BLCMOS Circuits Moore's 1 * Gordon E, Moore ~ Chairman Emeritus of Intel Corporation 1965 - observed trends in industry + of transistors on ICs vs release dates Noticed number of transistors doubling with release ofeach new IC generation Release dates (separate generations) were all 18-24 months apart [The number of sistors on ted cir will double every 18 months The level of integr Si Vion of silicon technology as measured in terms of number of devices per IC iconductor industry has followed this prediction with surprising accuraey. IC Technology: * Speed / Power performance of available technologies + The microelectronies evolution + SIA Roadmap Semiconductor Manufacturers 2001 Ranking Circuit Technology IC Technology (rms (iets Paracas Dissipation sa ed [srg . Equal rise Gm ms 0.4ms and fall aie Switch poor Good implementation Technology slower_—-Faster improvement Fully Sac) aes Scale down Gate © scanned with OKEN Scannerbw IC Technologies, MOS & Bi MOS technology is considered as one of the very important and promising technologies in the VLSI design process. The circuit designs are realized based on pMOS, nMOS, CMOS and BICMOS devices. The pMOS devices are based on the p-channel MOS transistors, Specifically, the pMOS channel is part of a n-type substrate lying between two heavily doped p+ wells beneath the source and drain electrodes, Generally. speaking, a pMOS transistor is only constructed in consort with an NMOS transistor, The nMOS technology and design processes provide an excellent backzround for other technologies In particular, some familiarity with nMOS allows a relatively easy transition to CMOS technology and design. ‘The techniques employed in nMOS technology for logic design are similar to GaAs technol ‘Therefore. understanding the basies of nMOS design will help in the layout of GaAs circuits In addition to VLSI technology, the VLSI design processes also provides a new degree of freedom for designers which helps for the significant developments. With the rapid advances in technology the the size of the ICs is shrinking and the integration density is increasing, The minimum line width of commercial products over the years is shown in the graph below. nena ine th eons) ‘The graph shows a significant decrease in the size of the chip in recent years which implicitly indicates the advancements in the VLSI technology. © scanned with OKEN ScannerUnit 1 1C Technologies, MOS & Bi CMOS Circuits MOS Transistor Symbol: AE RE CE e (a) (b) (c) HGRA wos transistor _ symbols ENHANCEMENT AND DEPLETION MODE MOS TRANSISTORS MOS Transistors are built on a silicon substrate, Silicon which is ‘group IV material is the cighth most common element in the universe by mass, but very rarely occurs as the pure free element in nature, It is most widely distributed in dusts, sands, planetoids, and planets as various forms of silicon dioxide (silica) or silicates, [¢ forms crystal lattice with bonds to four neighbours. Silicon is a eee semiconductor. Pure silicon has no free carriers and conducts poorly. But adding dopants to silicon increases its conductivity. If a group’ V material ie. an extra electron is added, it forms an n-type semiconductor. Ite group {If material re. missing eleciton pattem is formed (hole), the resulting semiconductor is a ‘A junction between p-type and 1-type semiconductor forms a conduction path. Source and Drain of the Metal Oxide Semiconductor (MOS) Transistor is formed by the “doped” regions on He eS © scanned with OKEN Scannerschnologies, MOS & Bi CMOS surface of chip. Oxide layer is formed by means of deposition of the silicon dioxide (S102) Ia which forms as an insulator and is a very thin pattern, Gate of the MOS transistor is the thin layer of polysilicon (poly)": used to apply electric field to the surface of silicon between Drain and Source. to form a “channel” of electrons or holes. Control by the Gate voltage is achieved by modulating the conductivity of the semiconductor region just below the gate. This region is known as the channel which isa The Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is a transistor ee yoltaye-controlled current device, in which current at two electrodes, drain by the action of an electric field at another le having in-between 5 Very thin metal oxide layer, is used for amplifying or switching electronic signals. ~ and source is controlled emiconductor and a fi fied as N-type named The Enhancement and Depletion mode MOS transistors are further classified as N-type 0 NMOS (or N-channel MOS) and P-type named PMOS (or P-channel MOS) devices shows the MOSFETs along with their enhancement and depletion modes. _, é Source 2 Li of i [ci > (Le Fete Le J n substrate n substrate i re Body Body Figure 1.5: (c) Enhancement P-type MOSFET (d) Depletion Paype MOSFET ‘The depletion mode devices are doped so that a channel exists even with zero voltage from gate to source during manufacturing of the device. Hence the channel always appears in the device. To Control the channel, a negative voltage is applied to the gate (for an N-channel device), depleting the = © scanned with OKEN Scannereal IC Technologies, MOS & Bj Goose ine c deviee. In essence, the depletions ‘channel, whieh reduces the current flow through the device. In essence, the depletion, Mode dei Doi channel ands equivalent to an open (OFF) swith. Due tothe dficulty of turning off the dpi, equivalent to a closed (ON) switch, while the enhancement-mode device does not have the mode devices, they are rarely used oa Working of Enhancement Mode Transistor The enhancement mode devices do not have the in-built channel. By applying the required potentials, the channel can be formed. Also for.the MOS devices, there is a threshold voltage (V,), below which ‘not enough charges will be attracted for the channel to be formed. This threshold voltage for a MOS se caae Lransistoris a function of doping k ind thickness of the oxide fayer. Case 1: Ves= OV and Vi, < Vy The device fs non-conducting, when no gate voage is applied (Vj, = OV) or (Vp < V,) and also drain ‘© source potential Va, = 0. With an insufficient voltage on the gate to'establish the channel region as N-type there will be no conduction between the source and drain. Since there # no conducting channel, there is no current drain, ie. 4,0, andthe device is said to be in the cut-off region. This is shown in the Figure'1.7 (a). ee euer Gai? uses” eee ey eter Figure 1.7: (a) Cut-off Region Case 2: Vgs > Vt When a riniam voltage greater than the threshold voltage V, (ic. Ves > Vo is applied, a high Concentration of negative charge carers forms an inversion layer located by a thin lyer vet to the interface between the semiconductor and the oxide insulator. This forms @ channel between the souree and drain of the trangistor, This is shown inthe Figure 1.7 (b), Si Figure 1 (b) Formation of a Channel © scanned with OKEN Scannerdrain widens, and since the drain is This is shown in Figure the depletion region around the aubjacent to the gate edge, the depletion r 17), channel wane : ion widens in the 5 his results in flow af el resulting in cure results in flow of electeon from source to drain "0 operate in linear r ‘Ses the reverse bias on the ses inversion | increase in Vy, inere layer whieh e; during this phase. Further n substrate junction in contact with the inversion aver density to decrease. This is shown in Figure 1.7 (d), The point at ersion layer density becomes ver Off. The value of Ve, which the ¥y smnall (nearly zero) at the drain end is termed pinch- ae St pinch-off is denoted as Vayu. This is termed as saturation region for the device. Diffusion current completes the a th from source to drain in this case, causing the channel to exhibit ‘thigh resistance and behaves as a constant current source P Substrate P sunsiate Booy 0d Figure 1.7: (c} Linear Region. (d) Saturation Region The MOSFET Ip versus Vos characteristics (V-1 Characteristics) is shown in the Figure 1.8. For Ves Tn odo 4 Tro onset TT a7 res TT, Sticon Subetrate sitcom Subatate | Poi a _ansuiating! Patyailicon Eeneg _Insuating ‘ Payatige wavered! yaitonn seu al 802 Siicon Substrate stican Substrate ot (A cy Mota Poysiicon Twincnae> PPP end oe OAT vinusion Siicon Substvate Figure 1.9: Fabrication Process of NMOS Device (CMOS FABRICATION: CMOS fabrication can be accomplished using either of the three technologies: + Newell technologies/P-well technologies = + Twin well technology + + Silicon On Insulator (SO) V—™ ‘The fabrication of CMOS can be done by following the below shown twenty steps, by which CMOS can be obtained by integrating, both the, NMC ind PMOS transistors on the same chip substrate. For integrating these NMOS and PMOS devices on the same chip, special regions called as well or tubs are required in which semiconductor type and substrate type are opposite to cach other. © scanned with OKEN ScannerUnit IC Technologies, MOS & Bi CMOS Circuits ‘\ Pavell has to be created on a Nesubstrate or N-well has to be ereated on a P-substrate. In this article, the fabrication of CMOS is deseribed using the P-substrate, in which the NMOS transistor is fabriea ated on a P-type substrate and the PMOS transistor is fabricated in Newell 2 - ‘The fabrication process involves twenty steps, which are as follows: N-Well Process Stepl: Substrate Primarily, start the process with a P-substrate, Step2: Oxidation cad ‘The oxidation process is done by using high-purity oxygen and hydrogen, oxidation furnace approximatel Which are exposed in an ly at 1000 degree centigrade. Step3: Photoresist. = A light-sensitive polymer that softens whenever exposed to light is called as Ph hotoresist layer. Itis formed Step4: Masking A ‘The photoresist is exposed to UV rays through the N-well mask © scanned with OKEN ScannerUnit-1 sr with the basic or acidic solutio n. A pait of the photoresist layer is removed by treating the wa Step6: Removal of SiO2 using acid etching — The SiO2 oxidation layer is removed through the open area made by the removal of photoresist usinu hydrofluoric acid, Step7: Removal of photoresist is stripped off, as shown in the below figure. ‘The entire photoresist. layer Step8: Formation of the N-well By using ion implantation or diffusion proces a s N-well is formed. 27 A Step9: Removal of SiO2 a Using the hydrofluoric acid, the remaining SiO2 i Step10: D removed. of polysilicon © scanned with OKEN Scanner‘Chomival Vapor Deposition (CVD) process is us Steplts Removing the layer Except the two small rey layer is stipped off. vr barring a small gions required for formi = rz ee __ Step12: xidation process 4 formed on this layer MOS. Next, an oxidation layer is f terminals of NMOS and PI Step13: Masking and N-diff By using the masking proce small gaps are m with two small regions forthe formation ofthe gate a Sr (Technologies, MOS & Bi Cos we to deposit a very thin layer of gate oxide a PMOS, the remaining area for the Gi es ing the Gates of NMOS and nade for the purpose of N -diffusion, Pub eve The n-type (n+) dopants are d of the terminals of NMOS, ised oF ion imj jplanted, and the three n+ are formed for the formation. © scanned with OKEN Scannerrhe remaining oxidation layer Step15: P-diffusion Similar to the above N-diffusion process, the P-difflusion regions are diffused to form the terminals of the PMOS. . em A | Step16: Thick field oxide 7 ield_ oxide is formed in all regions except the terminals of the PMOS and NMOS. __= : step1 7: Metallization ae 7 Pea OOS Tel ho Step18: Removal of excess metal = The excess metal is removed from the wafer la Step19: The terminals of the PMOS and NMOS are made from respective gaps. © scanned with OKEN Scanner“IC Technologies, MOS & Bi CMOS Cina Fabrication of CMOS using P-well process Among all the fabrication pro of the CMOS, N-well process is mostly used for the fabrication of the CMOS, Pavell process is almost similar to the Newell, But the only difference in powell Process is that it consists Nesubstrate and, thus, P-wells itself acts as substrate for the N- SS, Separate optimization of the hinsisiirs Will be provided. The independent optimization of Vt, body effect and gain of the P-devices, Nulevices ean be made possible with this prov Different steps of the fabrication of the CMOS using the twintub process are as follows: + Lightly doped né or p¥ substrate is taken and, to protect the latch up, epitasial layer is used. + The high-purity controlted thickness of the layers of silicon are grown with exact dopant concentrations, 1¢ dopant and its concentration in Silicon are used to determine electrical properties. + Formation of the tub Thin oxide construction © scanned with OKEN Scannerunit =1 pnologies, MOS & Bi CMOS Circuits + Inplantation of the source and drain + Cuty for making. contacts + Metallization Hy using the above steps we can fabricate CMOS using Lwin tub process method. Silicon-on-Insulator (SOL) CMOS Process Rather than using silicon as the substrate material, technologists have sought to use an insulating nd latch-up susceptibility. The SOF substrate to improve process characteristics such as speed pMos CMOS technology allows the ereation of independent, completely isolated nMOS and transistors virtually side-by-side onan insulating substrate. The main advantages of this technol0By are the higher integration density (because ofthe absence of well regions), complete avoidance of the Iatelup problem, an lower parasiti capacitances compared 10 the conventional p & newell or twine ul CMOS processes. A exoss-section of aMOS and pMOS devicesusing SOI provessis shown below. nos PMos Pe Insulating Substrate The SOL CMOS process is considerably more costly than the standard p & n-well CMOS process. Yet the improvements of device performance and the absence of latch-up problems can justify its use, especially for deep-sub-mieron devices. © scanned with OKEN ScannerBasic Electrical Properties of MOS and Bi CMOS c IpcVng Characteristics of MOS Transistor : The graph below shows the II) Vs VS characteristics of an ne MOS transistor for several values of VGS tis clear that there are two conduction states when the device is ON. The saturated state and the non-saturated state, The saturated curve isthe Mat portion and defines the saturation region. For Ves < VDS + Vth, the nMOS device is conducting and ID is independent of VS, For Ves > VDS + Vth, ‘he transistor is inthe non-saturation region and the curve isa half parabola, When the transistor 's OFF (Vgs < Vth), then ID is zero for any VD§ value. Resistive San {a) Depletion mode device The boundary ofthe ssturaton/non-saturation bias states is a point seen foreach curve in the the intersection of the straight line of the saturated region with the raph as quadratic curve of the Saturated region. This imerseetion point occurs atthe channel pinch off voltage diamond symbol marks the pinch-off voltage Vj non. called VDSAT. The DSAT for each value of VGs, VDSAT is detined as. ‘he minimum drain-source voltage tht is required to keep the ansstor in saturation Fo a given Vas 4m the non-saturated state, the drain current initially increases almost linearly from the origin betore bending in a parabolic response. Thus the name ohmic o linear forthe non- saturated reson, The drain current in saturation is vitally independent of VDS and the transistor aets as a current © scanned with OKEN Scanneris nu carrier inversion at the drain region of the channel. Carriers are of the drain/substrete pn junction and ejected out of the drein oon (b). Enhance mode devi Drain-to-Source Current Iyy Versus Voltage Vps Relationship: s based on the principle that the use of a voltage on the gate induce source and drain, which may then be caused to move from source to field created by voltage Vds applied between drain and ¢ to source voltage Vgs then Ids is dependent which electrons will flow source to drain .So.the drain current isd = Electron transit time(t) Length of the channel Where the _ © scanned with OKEN ScannerBut velocity v= peas Where jt =electron or hole mobility and Eds = Electric field also, Eds = Vds/L Sw = HVds/L and tds =? /yNids The (ypical values ofp at room temperature are given below, I» = 650 emV see (surface) Hp # 240 emAV see (surface) Non-saturated Region ; ‘88 (assuming substrate connected to source). The voltage along t he channel varies tnearly with distance X from the Souree due to the IR drop in the channel In the non Saturated state the average value is Ves/2. Also the effective gate voltage V, Vas - Vt where Vt, charge under the gate and establish the channel, Hence the induced charge is Qe = Where is the threshold voltage ceded to invert the Eg sins coW.L Eg= average electric field gate to channel Sins = relative permittivity of insulation between gate and channel eo=permitivty (ve »- ") ee P 2) " D © scanned with OKEN Scanner