New L J Institute of Engineering and Technology Semester: IV (2024)

NEW L J INSTITUTE OF ENGINEERING &

TECHNOLOGY

SEMESTER- 4

BRANCH- CSE/CSE[AIML]

SUBJECT NAME: COMPUTER ORGANIZATION AND

ARCHITECTURE

SUBJECT CODE: 3140707

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GTU SYLLABUS
Sr. No. Content % Weightage
1 Computer Data Representation 4
Basic computer data types, Complements, Fixed point representation, Register
Transfer and Micro-operations:
Floating point representation, Register Transfer language, Register Transfer,
Bus and Memory Transfers (Tree-State Bus Buffers, Memory Transfer),
Arithmetic Micro-Operations, Logic Micro-Operations, Shift Micro-
Operations, Arithmetic logical shift unit

2 Basic Computer Organization and Design 4

Instruction codes, Computer registers, computer instructions, Timing and
Control, Instruction cycle, Memory-Reference Instructions, Input-output and
interrupt, Complete computer description, Design of Basic computer, Design
of Accumulator Unit.

3 Basic Computer Organization and Design 8

Instruction codes, Computer registers, computer instructions, Timing and
Control, Instruction cycle, Memory-Reference Instructions, Input-output and
interrupt, Complete computer description, Design of Basic computer, Design
of Accumulator Unit.

4 Micro programmed Control Organization: 4

Control Memory, Address sequencing, Micro program example, Design of
Control Unit

5 Central Processing Unit 5

Introduction, General Register Organization, Stack Organization, Instruction
format, Addressing Modes, Data transfer and manipulation, Program control,
Reduced Instruction Set Computer (RISC) & Complex Instruction Set
Computer (CISC)

6 Pipeline And Vector Processing 5

Flynn's taxonomy, Parallel Processing, Pipelining, Arithmetic Pipeline,
Instruction, Pipeline, RISC Pipeline, Vector Processing, Array Processors

7 Computer Arithmetic 4
Introduction, Addition and subtraction, Multiplication Algorithms (Booth
Multiplication Algorithm), Division Algorithms, Floating Point Arithmetic
operations, Decimal Arithmetic Unit.

8 Input-Output Organization 4
Input-Output Interface, Asynchronous Data Transfer, Modes Of Transfer,
Priority Interrupt, DMA, Input-Output Processor (IOP), CPUIOP
Communication, Serial communication.

9 Memory Organization 6

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Memory Hierarchy, Main Memory, Auxiliary Memory, Associative Memory,

Cache Memory, Virtual Memory.

10 Multiprocessors 4
Characteristics of Multiprocessors, Interconnection Structures, Inter-
processor Arbitration, Inter-processor Communication and Synchronization,
Cache Coherence, Shared Memory Multiprocessors.

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CHAPTER NO- 2 : Basic Computer Organization and Design

TOPIC:1 Instruction Codes
Question: Explain Instruction code, Program, Computer instruction, Operation
Code
Solution:
Instruction Code
• An instruction code is a group of bits that instruct the computer to perform a
specific operation.
Program
• A program is a set of instructions that specify the operations, operands and the
sequence by which processing has to occur.
Computer Instruction
• A computer instruction is a binary code that specifies a sequence of micro-
operations for the computer.
• The computer reads each instruction from memory and places it in a control
register.
• The control then interprets the binary code of the instruction and proceeds to
execute it by issuing a sequence of micro-operations.
Operation Code (Opcode)
• The operation code of an instruction is a group of bits that define such operations
as add, subtract, multiply, shift, and complement.
• The number of bits required for the operation code of an instruction depends on the
total number of operations available in the computer.
• The operation code must consist of at least n bits for a given 2n (or less) distinct
operations.
Stored Program Organization

• The simplest way to organize a computer is to have one processor register(AC) and
an instruction code format with two parts.
The first part specifies the operation (opcode) to be performed and the second
specifies an address (operand).
• The memory address tells the control where to find an operand in memory.
• This operand is read from memory and used as the data to be operated on together
with the data stored in the processor register.

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• Instructions are stored in one section of memory and data in another.

• For a memory unit with 4096 words, we need 12 bits to specify an address since
212 = 4096.
• If we store each instruction code in one 16-bit memory word, we have available
four bits for operation code (opcode) to specify one out of 16 possible operations,
and 12 bits to specify the address of an operand.
• The control reads a 16-bit instruction from the program portion of memory.
• It then executes the operation specified by the operation code.
Instruction format of basic computer

Question: Explain the direct and indirect address with example and compare them.
Solution:
Direct & Indirect Addressing of Memory
• If the second part of an instruction format specifies the address of an operand, the
instruction is said to have a direct address.
• In Indirect address, the bits in the second part of the instruction designate an
address of a memory word in which the address of the operand is found.

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• A direct address instruction is placed at address 22 in memory.

• The I bit is 0, so the instruction is recognized as a direct address instruction.
• The opcode specifies an ADD instruction, and the address part is the binary
equivalent of 457.
• The control finds the operand in memory at address 457 and adds it to the content
of AC.

• The instruction in address 35 has a mode bit I = 1, recognized as an indirect

address instruction.
• The address part is the binary equivalent of 300.
• The control goes to address 300 to find the address of the operand.
• The address of the operand in this case is 1350.
• The operand found in address 1350 is then added to the content of AC.

TOPIC:2 Computer Registers

Question: Construct diagram of common bus system of four 4-bits registers with
diagram Or List out Register for basic computer.
Solution:
• Registers are a type of computer memory used to quickly accept, store, and
transfer data and instructions that are being used immediately by the CPU. The
registers used by the CPU are often termed as Processor registers.
• A processor register may hold an instruction, a storage address, or any data (such
as bit sequence or individual characters).
• The computer needs processor registers for manipulating data and a register for
holding a memory address. The register holding the memory location is used to
calculate the address of the next instruction after the execution of the current
instruction is completed.
Block diagram of a Computer’s CPU(basic computer registers and memory)

• The Memory unit has a capacity of 4096 words, and each word contains 16 bits.
• The Data Register (DR) contains 16 bits which hold the operand read from the
memory location.

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List of Registers for the Basic Computer

• The Memory Address Register (MAR) contains 12 bits which hold the address for
the memory location.
• The Program Counter (PC) also contains 12 bits which hold the address of the next
instruction to be read from memory after the current instruction is executed.
• The Accumulator (AC) register is a general purpose processing register.
• The instruction read from memory is placed in the Instruction register (IR).
• The Temporary Register (TR) is used for holding the temporary data during the
processing.
• The Input Registers (IR) holds the input characters given by the user.
• The Output Registers (OR) holds the output after processing the input data.
Basic computer registers connected to a common bus

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TOPIC:3 Computer Instructions

Question: What do you mean by completeness of instruction set? Give the reasons to
choose the instructions in each category.
Solution:
A computer should have a set of instructions so that the user can construct machine
language programs to evaluate any function that is known to be computable.
The set of instructions are said to be complete if the computer includes a sufficient number
of in each of the following categories:
1. Arithmetic, logical and shift instructions
2. Instructions for moving information to and from memory and processor registers
3. Program control instructions together with instructions that check status conditions
4. Input and output instructions
Types of Computer Instructions
1. Memory Reference Instruction

2. Register Reference Instruction

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3. Input – Output Instruction

The reason to choose the instructions in each category is fundamental for building fast,
efficient computers that optimize memory and processing resources. It specifies the
following supported capabilities:
• instructions
• data types
• processor registers
• main memory hardware
• input/output model
• addressing modes
It sets the rules for the hardware and software interface, defines what the CPU does and
ensures compatibility.
Question: Explain the following instructions 1) CLA 2) ISZ 3) INP
Solution:
1) CLA
• This instruction will perform operations on registers rather than memory addresses
• It will clear the accumulator
2) ISZ
• The Increment if Zero (ISZ) instruction increments the word determined by
effective address.
• If the incremented cost is zero, thus PC is incremented by 1. A negative value is
saved in the memory word through the programmer.
• It can influence the zero value after getting incremented repeatedly. Thus, the PC
is incremented and the next instruction is skipped.
3) INP
• The INP instruction transfers the input information from INPR into the eight least
significant bits of accumulator and clears the input flag to 0.

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Question: Differentiate memory reference and non-memory reference instructions.

Give example of each with required micro-operations.
Solution:
Memory reference instructions and non-memory reference instructions are two types of
instructions that are used by a computer's central processing unit (CPU) to execute
programs. Here is a brief explanation of the differences between these two types of
instructions:
Memory reference instructions:
• Memory reference instructions are instructions that access data stored in the
computer's memory.
• These instructions may include load and store instructions, which are used to read
data from memory or write data to memory, respectively.
• Memory reference instructions typically require the CPU to access the memory
subsystem in order to execute the instruction, which can take longer than executing
a non-memory reference instruction.
Non-memory reference instructions:
• Non-memory reference instructions are instructions that do not access data stored
in the computer's memory.
• These instructions may include arithmetic and logical operations, branching and
control flow instructions, and other types of instructions that do not require access
to the memory subsystem.
• Non-memory reference instructions can typically be executed more quickly than
memory reference instructions, because they do not require the CPU to access the
memory subsystem.
The performance of a computer's CPU can be affected by the balance between memory
reference instructions and non-memory reference instructions in the code being executed.
A program with a high ratio of memory reference instructions may be slower to execute
than a program with a lower ratio of memory reference instructions, because the CPU may
need to spend more time accessing the memory subsystem.
However, the specific impact of memory reference instructions on the performance of a
CPU will depend on a variety of factors, including the specific hardware and software
being used.
TOPIC:4 Timing And Control
Question: Draw and explain control unit diagram for basic computer.
Solution:
Control Unit of Basic Computer
Components of Control unit are
1. Two decoders
2. A sequence counter
3. Control logic gates
Working
• An instruction read from memory is placed in the instruction register (IR).
• In control unit the IR is divided into three parts: I bit, the operation code (12-
14)bit, and bits 0 through 11.
• The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder.
• Bit-15 of the instruction is transferred to a flip-flop designated by the symbol I.
• The eight outputs of the decoder are designated by the symbols D0 through D7.
• Bits 0 through 11 are applied to the control logic gates.
• The 4‐bit sequence counter can count in binary from 0 through 15. The outputs of
counter are decoded into 16 timing signals T0 through T15.

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• The sequence counter SC can be incremented or cleared synchronously.

• Most of the time, the counter is incremented to provide the sequence of timing
signals out of 4 X 16 decoder.
• Once in awhile, the counter is cleared to 0, causing the next timing signal to be T0.
• As an example, consider the case where SC is incremented to provide timing
signals T0, T1, T2, T3 and T4 in sequence. At time T4, SC is cleared to 0 if decoder
output D3 is active. This is expressed symbolically by the statement
D3T4: SC ← 0
• Initially, the CLR input of SC is active.
• The first positive transition of the clock clears SC to 0, which in turn activates the
timing T0 out of the decoder.
• T0 is active during one clock cycle.
• The positive clock transition labeled T0 in the diagram will trigger only those
registers whose control inputs are connected to timing signal T0.
Timing Cycle for D3T4: SC ← 0

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• SC is incremented with every positive clock transition, unless its CLR input is
active.
• This procedures the sequence of timing signals T0, T1, T2, T3 and T4 , and so on. If
SC is not cleared, the timing signals will continue with T5, T6, up to T15 and back
to T0.
• The last three waveforms shows how SC is cleared when D3T4 = 1.
• Output D3 from the operation decoder becomes active at the end of timing signal
T2.
• When timing signal T4 becomes active, the output of the AND gate that
implements the control function D3T4 becomes active.
• This signal is applied to the CLR input of SC.
• On the next positive clock transition the counter is cleared to 0.
• This causes the timing signal T0 to become active instead of T5 that would have
been active if SC were incremented instead of cleared.
Control Organization
Hardwired Control
• The control logic is implemented with gates, flips-flops, decoders and other digital
circuits.
• It can be optimized to produce a fast mode of operation.
• It requires changes in the wiring among the various components if the design has
to be modified or changed.
Microprogrammed Control
• The control information is stored in a control memory.
• The control memory is programmed to initiate the required sequence of micro-
operations.
• Any required changes or modifications can be done by updating the microprogram
in control memory.
TOPIC:5 Instruction Cycle
Question: Which are the different phases of Instruction Cycle? Describe Register
transfer for fetch phase with its diagram.
Solution:
A program residing in the memory unit of the computer consists of a sequence of
instructions. In the basic computer each instruction cycle consists of the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect address.
4. Execute the instruction.
• After step 4, the control goes back to step 1 to fetch, decode and execute the next
instruction.
• This process continues unless a HALT instruction is encountered.
Fetch & Decode
• PC is loaded with the address of the first instruction in the program.
• The micro-operations for fetch and decode phases are as follows:

Determine the type of instruction

• During time T3, the control unit determines the type of instruction i.e. Memory
reference, Register reference or Input-Output instruction.
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• If D7 = 1 then instruction must be register reference or input-output else memory

reference instruction.
To provide the data path for the transfer of PC to AR we must apply timing signal To
to achieve the following connection:

1. Place the content of PC onto the bus by making the bus selection inputs
equal to 010.
2. Transfer the content of the bus to AR by enabling the LD input of AR.
It is necessary to use timing signal T1 to provide the following connections in the bus
system.
1. Enable the read input of memory.
2. Place the content of memory onto the bus by making S2SISo = Ill.
3. Transfer the content Of the bus to IR by enabling the LD input Of IR.
4. Increment PC by enabling the INR input of PC.

The three instruction types are subdivided into four separate paths. The selected
operation is activated with the clock transition associated with timing signal T3. This
can be symbolized as follows:

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Question: Explain register reference instruction format.

Solution:

TOPIC:6 Memory-Reference Instructions

Question: List and explain Memory reference instructions in detail.
Solution:
AND: AND to AC
• This is an instruction that performs the AND logic operation on pairs of bits in AC
and the memory word specified by the effective address. The result of the
operation is transferred to AC.

ADD: ADD to AC
• This instruction adds the content of the memory word specified by the effective
address to the value of AC. The sum is transferred into AC and the output carry
Cout is transferred to the E (extended accumulator) flip-flop.

LDA: Load to AC
• This instruction transfers the memory word specified by the effective address to
AC.

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STA: Store AC
• This instruction stores the content of AC into the memory word specified by the
effective address.

BUN: Branch Unconditionally

• This instruction transfers the program to instruction specified by the effective
address. The BUN instruction allows the programmer to specify an instruction out
of sequence and the program branches (or jumps) unconditionally.

BSA: Branch and Save Return Address

• This instruction is useful for branching to a portion of the program called a
subroutine or procedure. When executed, the BSA instruction stores the address of
the next instruction in sequence (which is available in PC) into a memory location
specified by the effective address.

ISZ: Increment and Skip if Zero

• These instruction increments the word specified by the effective address, and if the
incremented value is equal to 0, PC is incremented by 1. Since it is not possible to
increment a word inside the memory, it is necessary to read the word into DR,
increment DR, and store the word back into memory.

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TOPIC:7 Input-Output And Interrupt

Question: Draw Flowchart for interrupt cycle.
Solution:

• The interrupt cycle is a hardware implementation of a branch and save return

address operation.
• An interrupt flip-flop R is included in the computer.
• When R = 0, the computer goes through an instruction cycle.
• During the execute phase of the instruction cycle IEN is checked by the control.
• If it is 0, it indicates that the programmer does not want to use the interrupt, so
control continues with the next instruction cycle.
• If IEN is 1, control checks the flag bits.
• If both flags are 0, it indicates that neither the input nor the output registers are
ready for transfer of information.
• In this case, control continues with the next instruction cycle. If either flag is set to
1 while IEN = 1, flip-flop R is set to 1.
• At the end of the execute phase, control checks the value of R, and if it is equal to
1, it goes to an interrupt cycle instead of an instruction cycle.
Question: Explain input-output instructions.
Solution:

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TOPIC:8 Complete Computer Description, Design Of Basic Computer,

Design Of Accumulator Unit
Question: Explain Flowchart for Basic Computer operation.
Solution:

Question: Explain the design of basic computer

Solution:
A basic computer consists of the following hardware components.

1. A memory unit with 4096 words of 16 bits each

2. Nine Registers: AC (Accumulator), DR (Data register), AR (Address register), IR
(Instruction register), PC (Program counter), TR (Temporary register), SC
(Sequence Counter), INPR (Input register), and OUTR (Output register).
3. Seven Flip-Flops: I, S, E, R, IEN, FGI and FGO
4. Two decoders: a 3 x 8 operation decoder and 4 x 16 timing decoder
5. A 16-bit common bus
6. Control Logic Gates
7. Adder and logic circuits connected to the input of AC.

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Question: Explain the design of Accumulator logic.

Solution:

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