Internal processor Constant 4 \ Select Figure 7.2 Input and Figure 7.1 Output gating for the registers inVAL Clock figure 7.3 Input and output gating for one @ Tor one register bit cabiained directly ro . 1 eee z ae i the bus, The result produced by the AL inmegister & a 1 sequence of operations to auld - U as stored temporarily jase of register R2 and store the tesult in register in the contents of register RL to ister RA aS * r 1. Rlvwes Vin Y Rogee Select, Add. 4 X Lows R3in Jo duration of the { step, Atbortier signals ate inaetive, Hone, wi step Le Ya enabled, causing the contents > thre mmultaplerees Select signal iS pItel Y to input Sot onty the bus and. e signals applied ye the output of the ALU Hoandedd into wgislCT ye COMETS of registe Zar earried Out TUFINE us during &ny clock saver i anny step are aetivated for th The signals whose names ae tek evele corresponding (0 tha 7 cutpat of register RI and the inpul ol reginte! ee tw be transferred over the bus Yo In sep eee causing the mulliplerct aur gate the gost of) eet At the same dime, the contents of egie RD are gated ee input B, The function performed py the ALL leper eau naa Haag ease. the Aaa He SE wh 2 el wun of the nwo numbers a inputs a trash, Use its input control St anal ts acted \ “ pt sep? wt to the destination © Ra This las in Se cele ccause only ONC register outpul ean be &e wer seme a HN ea sample: : NoR.arwl son lt reality. af the ALU cat perform the required yal eHEONS, gistels area signat for cael tesa® introductory discus xpecit be performed. For’ Name V individual ALU epet degree af encoding. is Thels t e conte eight SAU dierent operauons: three a ye itaations and qe assume ve to spec) trol 8"ko © BASIC PROCESSING UNIT cHAl 7.1.3 FETCHING 4 WORD FROM MEMORY ation from memory, the processor has to specify the air smory location where this information is stored.and request a Read operation ao a ves whether the information to be fetched represents an instruction ina progr his a voperand specified by an instruction. The processor transfers she required address tg the MAR, whose output is connected to the address lines of the memory bus, 4p the same time, the processor uses the control lines of the memory bus to indicate that g Read operation is needed. When the requested data are received from the memory hey are stored in register MDR, from where they can be transferred to other registers in the meth vonnections for register MDR are illustrated in Figure 7.4. It has four contro} signals: MDRj, and MDRou control the connection to the internal bus _ and MDR,,- dnd MDRyure control the connection to the external bus. The circuit in Figure 73, easily modified to provide the additional connections. A three-input multiplexer can be used, with the memory bus data line connected to the third input. This input is selected when MDRing = 1. A second tri-state gate, controlled by MDRowe can be used to connect the output of the flip-flop to the memory bus. During memory Read and Write operations, the timing of internal processor op- erations must be coordinated with the response of the addressed device on the mem- ory bus, The processor completes one internal data transfer in one clock cycle. The speed of operation of the addressed device, on the other hand, varies with the de- vice. We saw in Chapter 5 that modern processors include a cache memory on the same chip as the processor. Typically, a cache will respond to a memory read request in one clock cycle. However, when a cache miss occurs, the request is forwarded to the main memory, which introduces a delay of several clock cycles. A read or write request may also be intended for a register in a memory-mapped I/O device. To fetch a word of in! forma or Memory-bus Internal processor datalines Nap MPR bus er “er MDR,, n ‘gure 7-4 Connection and contol signals for register MDR77.1 SOME FUNDAMENTAL CONCEPTS pare VO registers are not cached, so their accesses always take a number of clock cycles. | To accommodate the variability in response time, the processor waits until it re- ceives an indication that the requested Read operation has been completed. We will assume that a control signal called Memory-Function-Completed (MFC) is used for this purpose. The addressed device sets this signal to | to indicate that the contents of the specified location have been read and are available on the data lines of the memory bus. (We encountered several examples of such a signal in conjunction with the buses discussed in Chapter 4, such as Slave-ready in Figure 4.25 and TRDY# in Figure 4.41.) As an example of a read operation, consider the instruction Move (RI),R2. The actions needed to execute this instruction are: MAR < [RI] Start a Read operation on the memory bus Wait for the MFC response from the memory Load MDR from the memory bus ; R2 <— [MDR] wrens These actions may be carried out as separate steps, but some can be combined into a single step. Each action can be completed in one clock cycle, except action 3 which requires one or more clock cycles, depending on the speed of the addressed device. For simplicity, let us assume that the output of MAR is enabled all the time. Thus, the contents of MAR are always available on the address lines of the memory bus. This is the case when the processor is the bus master. When a new address is loaded into MAR, it will appear on the memory bus at the beginning of the next clock cycle, as shown in Figure 7.5. A Read control signal is activated at the same time MAR is loaded. This signal will cause the bus interface circuit to send a read command, MR, on the bus. With this arrangement, we have combined actions 1 and 2 above into a single control step. Actions 3 and 4 can also be combined by activating control signal MDR we while waiting for a response from the memory. Thus, the data received from the memory are loaded into MDR at the end of the clock cycle in which the MFC signal is received In the next clock cycle, MDRow is activated to transfer the data to register R2. This means that the memory read operation requires three steps, which can be described by the signals being activated as follows 1. Rl ous MARin, Read 2. MDRine, WMFC 3. MDRows R2in where WMEC is the control signal that causes the processor’s control circuitry to Wall he arrival of thie MFC signal. . “" ‘Figure 7 § shows that MDRige is set (0 1 for exactly the same period as the read command, MR. Hence, in subsequent discussion, we will not specify the value of MDR._~ explicitly, with the understanding that itis always equal to MRSiep j=— | —-|-——_____ 2 —+——__+|._ , Clock J UF LI LUI Lp ri MAR,y, | Address X 7 - | | | Read >| MR MDRing MDR, out Figure 7.5 Timing of a memory Read operation. 7.1.4 STORING A WORD IN MEMORY Writing a word into a memory location follows a similar procedure. The desired address is loaded into MAR. Then, the data to be written are loaded into MDR, and a Write command is issued. Hence, executing the instruction Move R2,(R1),_ requires the following sequence: _—— Ie Row, MARin 2. R2vy, MDRin, Write 38. MDRouwe, WMFC As in the case of the read operation, the Write control signal causes the memory b interface hardware to issue a Write command on the memory bus. The processor remains in step 3 until the memory operation is completed and an MFC response is received wsEXECUTION OF A COMPLETy 1 together the sequer «now put 102 quence of ele, eon ‘Consider the instruction MENLAY operations requi Mie ‘quired to execute one Add (R3).R} 7 e contents of a mer j adds the con mory location o uires th ‘i Pointed to by : jnstruction req 1¢ following actions: y R3 to, register. Executing sis reich the instruction * ach the first operand (the contents of the memory | © perform the addition. ¥ location pointed to by R3). Load the result into RI. igure 7.6 gives the sequence of con : \ t 7 insle-bus architecture of Figure ae eed ‘o perform these operations fat ihe instruction fetch operation is initiated be fe roceeas as follows inseep |, Peration is initiated by loading the contents of the PC menthe MAR and sending a Read request to the memory. The Selet signal is cet eiatd which causes the multiplexer MUX to select the constant 4 This values added ve operand at input B, which is the contents of the PC-and the result is stored in sister Z. The updated value is moved from register Z back into the PC during tep 2, siike waiting for the memory to respond. In Sip, thé word etched from the memory) isloaded into the IR. Steps I through 3 constitute the instruction fetch phase, which isthe same forall instructions. The instruction decoding circuit interprets the contents of the IR at the heginning of step 4. This enables the control circuitry to activate the control signals for saps 4 through 7, which constitute the execution phase. The contents of register R3 ure transferred to the MAR in step 4, and a memory read operation is initiated. Then Step Action Read, Select4, Add. Zin Te PCouty MARins 2 Zouts PCin: Yin: WMFC_ 3 MDRout, HRin 4 R3our: MARin- Read 5 Rout: Yin: WMC MDRouts Select, Add, Zin Zouts Rlin+ End x ion of the . ace for execution o Figure 7.6 Control seqvense 4 instruction Ad 421