Principle of Microcomputer

Based on ARM Technology

STM32F10x Device
CONTENTS

• Objectives
• STM32F10x Device
• Block Diagram
• Memory mapping and boot modes
• System Architecture
• STM32F10x System Peripherals
• Main features
• STM32F10x Minimum External Components

2
★Objectives:

▪ Familiarize with STM32F10x device

▪ Know the main features of the STM32F10x
system peripherals.

3
More choice with STM32 series
▪ The general purpose F-1 series
addresses a wide range of applications,
from the lowest price-sensitive design to
the computing intensive, high memory
Footprint

▪ Get the highest performance with the

F-2 series for computing intensive
application and advanced connectivity.
The F-2 series maintains the compatibility
with the F-1 series.

▪ Get the highest performance with the

Design ultra-low-power applications with
the L-1 series for those who are power
conscious and seek the absolute lowest
energy consumption. The L-1 series
maintains the compatibility with the F-1
series.

4
STM32 portfolio based on F1 series

5
STM32 Value line 16K-32KBytes block diagram

CORTEXTM-M3

Flash I/F
Power Supply
▪ Core and operating conditions CPU 16kB - 32kB
Reg 1.8V
24 MHz Flash Memory
▪ ARM® Cortex™-M3 POR/PDR/PVD

Matrix / Arbiter (max 24MHz)

▪ 1.25 DMIPS/MHz up to 24 MHz

ARM Lite Hi-Speed Bus

4kB SRAM XTAL oscillators
▪ 2.0 V to 3.6 V range 32KHz + 4~25MHz
▪ -40 to +105 °C JTAG/SW Debug 20B Backup Data Int. RC
Nested vect IT Ctrl oscillators
40KHz + 8MHz
▪ Rich connectivity 1 x Systick Timer
PLL
▪ 5 communications peripherals
RTC / AWU
DMA Clock Control
▪ Advanced analog 7 Channels
▪ 12-bit1.2 µs conversion time ADC Bridge
ARM® Peripheral Bus 1
▪ Dual channel 12-bit DAC (max 24MHz)
Bridge
1 x 16-bit PWM

ARM® Peripheral Bus 2

Synchronized AC Timer 5 x 16-bit timer 1 x CEC
▪ Enhanced control
Up to 16 Ext. ITs 2 x Watchdog
▪

(max 24MHz)
16-bit motor control timer (independent & window)
▪ 5x 16-bit PWM timers 1 x USART/LIN
37/51 I/Os 2-channel 12-bit DAC Smartcard / IrDa
Modem Control
1 x SPI 1 x 12-bit ADC
▪ LQFP48, LQFP/BGA64 1 x USART/LIN up to 16 channels
Smartcard/IrDa
Modem Control Temperature Sensor 1 x I 2C

AWU: Automatic Wake Up

6
CEC: Consumer Electronic Control
STM32 Value line 64K-128KBytes block diagram

Flash I/F
CORTEXTM-M3 64kB - 128kB Power Supply
▪ Core and operating conditions CPU Flash Memory Reg 1.8V
24 MHz POR/PDR/PVD
▪ ARM® Cortex™-M3

Matrix / Arbiter (max 24MHz)

ARM® Lite Hi-Speed Bus
▪ 1.25 DMIPS/MHz up to 24 MHz 8kB SRAM XTAL oscillators
▪ 2.0 V to 3.6 V range 32KHz + 4~25MHz

▪ -40 to +105 °C JTAG/SW Debug 20B Backup Data Int. RC

Nested vect IT Ctrl oscillators
40KHz + 8MHz
1 x Systick Timer
▪ Rich connectivity PLL
▪ 8 communications peripherals DMA
7 Channels Clock Control RTC / AWU
▪ Advanced analog ARM® Peripheral Bus1
▪ 12-bit1.2 µs conversion time ADC Bridge
(max 24MHz)
▪ Dual channel 12-bit DAC
Bridge
1 x 16-bit PWM

ARM® Peripheral Bus2

Synchronized AC Timer 6 x 16-bit Timer
1 x CEC
▪ Enhanced control Up to 16 Ext. ITs 2 x Watchdog

(max 24MHz)
▪ 16-bit motor control timer (independent & window)
▪ 6x 16-bit PWM timers 37/51/80 I/Os 2 x USART/LIN
2-channel 12-bit DAC Smartcard / IrDa
Modem Control
1 x SPI 1 x 12-bit ADC
▪ LQFP48, LQFP/BGA64, LQFP100 up to16 channels 1 x SPI
1 x USART/LIN
Smartcard/IrDa
Modem Control Temperature Sensor 2 x I 2C

7
STM32 Value line 256K-512KBytes block diagram
CORTEXTM-M3

Flash I/F
CPU Power Supply
256KB-512kB
▪ Core and operating conditions 24 MHz
Flash Memory
Reg 1.8V
POR/PDR/PVD
▪ ARM® Cortex™-M3
▪ 1.25 DMIPS/MHz up to 24 MHz

ARM ® Lite Hi-Speed 36us

Matrix / Arbiter (max 24MHz)
24KB-32kB SRAM XTAL oscillators
▪ 2.0 V to 3.6 V range 32KHz + 4~25MHz

▪ -40 to +105 °C JTAG/SW Debug 84B Backup Data

Int. RC oscillators
Nested vect IT Ctrl 40KHz + 8MHz
FSMC
1 x Systick Timer
▪ Rich connectivity SRAM/ NOR/ LCD parallel
interface
PLL
▪ 11 communications peripherals
DMA RTC / AWU
up to 12 Channels Clock Control
▪ FSMC
▪ SRAM, NOR, memories support. Bridge
ARM® Peripheral Bus 1
(max 24MHz)
▪ LCD Parallel interface 8/16-bit
Bridge
▪ Intel 8080 and Motorola 68K
1 x 16-bit PWM
Synchronized AC Timer 10 x 16-bit Timer

ARM® Peripheral Bus 2

1 x CEC
▪ Enhanced control
Up to 16 Ext. ITs 2 x Watchdog
▪ 16-bit motor control timer

(max 24MHz)
(independent & window)
▪ 10x 16-bit PWM timers 51/80/112 I/Os 4 x USART/LIN
2-channel 12-bit DAC Smartcard / IrDa
Modem Control
1 x SPI
1 x 12-bit ADC
▪ LQFP64, LQFP100, LQFP144 up to 16 channels 2 x SPI
1 x USART/LIN
Smartcard/IrDa
Modem Control Temperature Sensor 2 x I 2C

8
Memory Mapping and Boot Modes
▪ Addressable memory space of 4 GBytes
▪ RAM : up to 64 kBytes
▪ FLASH : up to 512 kBytes
▪ Boot modes:
Depending on the Boot configuration
0xFFFF FFFF - Embedded Flash Memory
Reserved - System Memory
0xE010 0000
0xE00F FFFF
Cortex-M3
- Embedded SRAM Memory
internal is aliased at @0x00
0xE000 0000 peripherals

Reserved
BOOT Mode
0x1FFF F80F Selection Pins Boot Mode Aliasing
Option Bytes 0x1FFF F800
Reserved BOOT1 BOOT0
0x1FFF F7FF
SystemMemory
User Flash User Flash is selected as
0x1FFF F000 x 0
boot space

Reserved SystemMemory is
0 1 SystemMemory
selected as boot space

Peripherals 0x0801 FFFF Embedded Embedded SRAM is

0x4000 0000 1 1
Flash
SRAM selected as boot space
Reserved
0x0800 0000

▪
0x2000 0000
SRAM
SystemMemory: contains the Bootloader
Reserved
used to re-program the FLASH through USART1.
CODE
0x0000 0000

9
System Architecture
▪ Multiply possibilities of bus accesses to SRAM, Flash, Peripherals, DMA
▪ BusMatrix added to Harvard architecture allows parallel access
▪ Efficient DMA and Rapid data flow
▪ Direct path to SRAM through arbiter, guarantees alternating access
▪ Harvard architecture + BusMatrix allows Flash execution in parallel with DMA transfer
I-bus

Flash I/F
D-bus
FLASH
CORTEX-M3
Master 1

BusMatrix
SRAM
Slave
APB2 Peripheral Bus APB2
GP-DMA AHB AHB-APB2
Master 2 APB1
AHB-APB1
Peripheral Bus APB1
Arbiter Bridges

Buses are not overloaded with data movement tasks

10
STM32F103x Series Block Diagram

11
 STM32F103x Series Block Diagram
▪Please see STM32F103VET6
datasheet P12

12
Power Control (PWR) and Backup Domain (BKP)

13
Power Supply
VDDA domain

VREF-
A/D converter
• Power Supply Schemes VREF+
Temp. sensor
Reset block
VDDA
PLL
▪ VDD = 2.0 to 3.6 V: External Power VSSA

Supply for I/Os and the internal VDD domain V18 domain

regulator. I/O Rings

▪ VDDA = 2.0 to 3.6 V: External VSS

STANDBY circuitry
(Wake-up logic,
Core
Memories
Analog Power supplies for ADC, VDD
IWDG, RCC CSR reg) Digital
peripherals
Reset blocks, RCs and PLL. Voltage Regulator

➔ ADC working only if VDDA ≥ 2.4V Low Voltage Detector

Backup domain
▪ VBAT = 1.8 to 3.6 V: For Backup
LSE crystal 32K osc
domain when VDD is not present. VBAT BKP registers
RCC BDCR register
RTC

14
Power On Reset / Power Down Reset

• Integrated POR(Power On VDD

Reset )/ PDR(Power Down Vtrh POR

Reset ): circuitry guarantees Vtrl 40mv hysteresis
PDR

proper product reset when Tempo

2ms
voltage is not in the product
guaranteed voltage range (2V
Reset
to 3.6V)
▪ No need for external reset circuit
Vtrl min 1.8V / Vtrh max 2V
• POR and PDR have a typical
hysteresis of 40mV

15
Programmable Voltage Detector (PVD)

• Programmable Voltage VDD

Detector(PVD)
▪ Enabled by software Threshold
PVD Threshold 100mv
▪ Monitor the VDD power supply hysteresis

by comparing it to a threshold
▪ Threshold configurable from
PVD
2.2V to 2.9V by step of 100mV Output

16
Backup Domain
• Backup Domain contains
▪ RTC (Counter, Prescaler and Alarm mechanism)
▪ Separate 32KHz Osc (LSE) for RTC
Backup domain
▪ 20-byte user backup data
VBAT
power switch
▪ RCC BDSR register: RTC source clock selection RCC BDSR 32KHz OSC
reg (LSE)
and enable + LSE config
➔ Reset only by Backup domain RESET VDD

• VBAT independent voltage supply ANTI_ 20 byte

RTC
TAMP data
▪ Automatic switch-over to VBAT when VDD goes lower
than PDR level
▪ No current sunk on VBAT when VDD present

• Tamper detection: resets all user backup

registers
▪ Configurable level: low/high
▪ Configurable interrupt generation

17
Low Power Modes
• STM32F10x Low Power modes: uses Cortex-M3 Sleep modes
• SLEEP, STOP and STANDBY modes
➔ The reset circuitry, POR/PDR, is active in STANDBY and STOP modes
Feature STM32F10x typ (*)

Consumption in RUN mode w/ execute from Flash on internal RC and 4.9mA

peripherals clock ON
Consumption in RUN mode w/ execute from Flash on PLL 24 MHz 36mA
(HSE : external clock = 8MHz) and peripherals clock ON
Consumption in RUN mode w/ execute from Flash on PLL 24 MHz 27mA
(HSE : external clock = 8MHz) and peripherals clock OFF
STOP w/ Voltage Regulator in low power 14µA
Low speed and high-speed internal RC oscillators and high-speed oscillator
OFF(no independent watchdog)
STANDBY w/ low-speed oscillator and RTC OFF 2µA
Low-speed internal RC oscillator and independent watchdog OFF
RTC on VBAT 1.4 µA

(*) : Typical values are measured at TA = 25 °C, VDD/VBAT = 3.3 V.

18
STM32F10x Minimum External Components
• Built-in Power Supply Supervisor reduces need for external components
• Filtered reset input, integrated POR/PDR circuitry, programmable Voltage Detector (PVD).

• Embedded 8 MHz High-Speed Internal (HSI) RC oscillator can be used as main

clock

• Optional main crystal drives entire system

• Inexpensive 4-16 MHz crystal drives CPU, all peripherals

• Optional 32.768 kHz crystal needed additionally for RTC, can run on 40KHz Low
Speed Internal (LSI) RC oscillator

• Only 7 mandatory external passive components for base

system on LQFP100 package!

Application Note is available from www.st.com/mcu

AN2586: STM32F10xxx Hardware development : getting started
19
CONTENTS
• Objectives

• STM32 Firm Library

20
★Objectives:

▪ Look through the STM32 Firm Library

21
Introduction
The STM32F10x Standard Peripherals Library is a complete
package, consisting of device drivers for all of the standard device
peripherals, for STM32 Value line(High, Medium and Low),
Connectivity line, XL-, High-, Medium- and Low- Density Devices 32-
bit Flash microcontrollers.
This library is a firmware package which contains a collection of
routines, data structures and macros covering the features of STM32
peripherals. It includes a description of the device drivers plus a set
of examples for each peripheral. The firmware library allows any
device to be used in the user application without the need for in-
depth study of each peripheral’s specifications.
22
Introduction

Using the Standard Peripherals Library has two advantages:

it saves significant time that would otherwise be spent in
coding, while simultaneously reducing application development
and integration costs.
The STM32F10x Standard Peripherals Library is full CMSIS
compliant.

23
Introduction

https://www.st.com/en/embedded-software/stsw-stm32054.html

24
STM32 Firmware Library User Manual

25
STM32 Firmware Library User Manual

26
STM32F10xxx standard peripheral library
architecture
- STM32 interrupt IRQ list/ Specific
options for the Cortex-M3 core User application
- STM32 peripheral memory mapping
and physical register address definition
- Configuration options
…

Cortex-M3 exceptions

Peripheral header file

Include NVIC and

SysTick drivers

Low-level & API functions to

Perform basic operations
offered by the peripheral
27
Coding conventions
• All firmware is coded in ANSI-C
• Strict ANSI-C for all library peripheral files
• Relaxed ANSI-C for projects & Examples files.
• PPP is used to reference any peripheral acronym, e.g. TIM for
Timer.
• Registers & Structures
• FW library registers have the same names as in STM32F10x Datasheet &
reference manual.
• All registers hardware accesses are performed through a C structures :
• Improve code re-use : e.g. the same structure to handle and initialize 3
USARTs.

28
Using the Library (1/4)
1) Before configuring a peripheral, you have to enable its clock by calling one of the
following functions:
• RCC_AHBPeriphClockCmd(RCC_AHBPeriph_PPPx , ENABLE);
• RCC_APB2PeriphClockCmd(RCC_APB2Periph_PPPx , ENABLE);
• RCC_APB1PeriphClockCmd(RCC_APB1Periph_PPPx , ENABLE);

2) PPP_DeInit(..) function can be used to set all PPP’s peripheral registers to their reset
values:
• PPP_DeInit(PPPx);

3) If after peripheral configuration, the user wants to modify one or more peripheral settings
he should proceed as following:
• PPP_InitStucture.memberX = valX;
• PPP_InitStructure.memberY = valY;
• PPP_Init(PPPx, &PPP_InitStructure);

29
Using the Library (2/4)
• At this stage the PPP peripheral is initialized and can be enabled by making a call
to PPP_Cmd(..) function: PPP_Cmd(PPPx, ENABLE);
Note: This function is used only for communication peripherals like UART,
SPI, …

• To access the functionality of the PPP peripheral, the user can use a set of
dedicated functions. These functions are specific to the peripheral and for more
details refer to STM32F10x Firmware Library User Manual.

Example of GPIO
Functions available

30
Using the Library (3/4)
• UART1 configuration example :
• /* Enable USART1 Clock */
• RCC_APB2PeriphClockCmd( USART1, ENABLE );
• /* set all UART1’s peripheral registers to their reset values */
• USART_DeInit( USART1 ) ;
• /* USART1 configuration ------------------------------------------------------*/
• /* USART1 configured as follow:
• - BaudRate = 19200 baud
• - Word Length = 8 Bits
• - One Stop Bit
• - Even parity
• - Hardware flow control disabled (RTS and CTS signals)
• - Receive and transmit enabled */
• USART_InitStructure.USART_BaudRate = 9600;
• USART_InitStructure.USART_WordLength = USART_WordLength_8b;
• USART_InitStructure.USART_StopBits = USART_StopBits_1;
• USART_InitStructure.USART_Parity = USART_Parity_Even;
• USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
• USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
• /* Configure USART1 */
• USART_Init( USART1, &USART_InitStructure);
• /* Enable USART1 */
• USART_Cmd( USART1, ENABLE ); USART 1 is ready now … 31
Using the Library (4/4)
• Files to be modified by the user:
▪ main.c
▪ stm32f10x.h #include "stm32f10x.h“
/* Uncomment the line below according to the target STM32 int main(void)
device used in your application */ {
#if !defined (STM32F10X_LD) && !defined ...
(STM32F10X_MD) && !defined (STM32F10X_HD) GPIO_WriteBit(GPIOD, GPIO_Pin_1, Bit_SET);
/* #define STM32F10X_LD */ /*!< STM32 Low density …
devices */… }
#endif
…
/* STM32F10x Interrupt Number Definition*/
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
▪ stm32f10x_It.c
#include "stm32f10x_it.h"

▪ stm32f10x_It.h
…
/* Exported functions --------------------------------------------
--- */ void EXTI1_IRQHandler(void)
void NMI_Handler(void); {
void HardFault_Handler(void); GPIO_WriteBit(GPIOD, GPIO_Pin_1, Bit_SET);
… }

32