Digital Logic Design 1

Unit 1 : Number Systems

01. Write about Binary number system. - 03

02. Write about Octal number system. - 04
03. Write about Hexa Decimal number system. - 06
04. Explain r’s & (r-1)’s complement. - 08
05. Write about Signed Binary Numbers. - 09
06. Explain Addition and Subtraction of unsigned and signed binary numbers. - 11
07. Write about Weighted and Non-Weighted Binary codes. - 13

Unit 2 : Logic Gates and Boolean Algebra

01. Write about Logic gates in Digital Electronics. [or]

Explain following gates : NOT, AND, OR, Universal gates (NAND, NOR), X-OR, X-NOR - 15
02. Write about Boolean Laws & Theorems. - 18
03. Explain : Dual & Complement of a Logic function. - 20
04. Explain : Min terms & Max terms, Canonical & Standard forms. - 21
05. Write about Two level realization of Logic functions. - 23
06. Explain about minimization of logic functions. - 27
07. Write about don’t care conditions in K-Maps. - 30

Unit 3 : Combinational Logic Circuits - I

01. What are combinational Logic circuits? Explain. - 31

02. Explain designing half adder & full adder. - 32
03. Explain designing half subtractor & full subtractor. - 36
04. Explain Ripple Adders and Subtractors. - 38

Digital Logic Design – Sudheer Kumar

 2
Unit 4 : Combinational Logic Circuits - II

01. Write about Encoders? - 41

02. What are ‘Priority Encoders’? Explain. - 43
03. Write about Decoders? - 44
04. What are ‘Higher Order Decoders’? Explain. - 45
05. Write about Multiplexers. - 46
06. Write about Demultiplexers. - 49
07. How to implement Boolean functions (realization of Boolean functions) using decoders? - 52
08. How to implement Boolean functions (realization of Boolean functions) using multiplexers? - 53

Unit 5 : Sequential Logic Circuits

01. Write about Classification of Sequential circuits. - 55

02. Explain : Latches & Flip-flops. - 56
03. Implementing SR Latch using NAND & NOR gates. - 58
04. Types of flip-flops (RS, JK, T and D flip-flops). - 61
05. Conversion of flip-flops. - 63
06. Explain about flip-flops with asynchronous inputs (preset and clear). - 65
07. Explain: Shift registers, Bi-directional shift registers, Universal shift register. - 66
08. Design of ripple counters. - 68
09. Explain: Synchronous counters and Variable modulus counters. - 69

Model Question Paper - 72

Digital Logic Design – Sudheer Kumar

 Unit 1 : Number Systems
3
01. Write about Binary number system.

Binary Number System:

 The ‘Binary number system’ is base 2 number system.

 In Binary number system, we use digits 0 and 1.
 In Binary number system, position values are powers of 2.

Converting Binary number to Decimal number:

 To convert Binary number to Decimal number, multiply each digit in binary number with its position value. Add
these products.
 Ex 1: Convert binary number 1101 to decimal number.

1 1 0 1  face values
23 22 21 20  position values

Decimal number = 1 x 23 + 1 x 22 + 0 x 21 +1 x 20
= 8 + 4 + 0 + 1 = 13

 Ex 2: Convert binary number 10101001 to decimal number.

1 0 1 0 1 0 0 1  face values
27 26 25 24 23 22 21 20  position values

Decimal number = 1 x 27 + 0 x 26 + 1 x 25 + 0 x 24 + 1 x 23 + 0 x 22 + 0 x 21 + 1 x 20
= 128 + 0 + 32 + 0 + 8 + 0 + 0 + 1 = 169

Converting Decimal number to Binary number:

 To convert Decimal number to Binary number, divide the decimal number by 2 & write the remainder.
 Repeat this process until the number can’t be divided by 2 anymore.

Ex 1: Convert decimal number 13 to binary Ex 2: Convert decimal number 169 to binary

number. number.

Digital Logic Design – Sudheer Kumar

02. Write about Octal number system.
4
Octal Number System:

 The ‘Octal number system’ is base 8 number system.

 In Octal number system, we use digits 0, 1, 2, 3, 4, 5, 6, 7.
 In Octal number system, position values are powers of 8.

Converting Octal number to Decimal number:

 To convert octal number to Decimal number, multiply each digit in octal number with its position value. Add
these products.
 Ex 1: Convert octal number 215 to decimal number.

2 1 5  face values
82 81 80  position values

Result = 2 x 82 + 1 x 81 + 5 x 80
= 2 x 64 + 1 x 8 + 5 x 1
= 128 + 8 +5
= 141

 Ex 2: Convert octal number 3571 to decimal number.

3 5 7 1  face values
83 82 81 80  position values

Result = 3 x 83 + 5 x 82 + 7 x 81 + 1 x 80
= 3 x 512 + 5 x 64 + 7 x 8 + 1 x 1
= 1536 + 320 + 56 + 1
= 1913

Converting Decimal number to Octal number:

 To convert Decimal number to octal number, divide the decimal number by 8 & write the remainder.
 Repeat this process until the number can’t be divided by 8 anymore.

Ex 1: Convert decimal number 143 to octal Ex 2: Convert decimal number 187 to octal number.
number.

Digital Logic Design – Sudheer Kumar

Converting Octal number to Binary number:
5
 To convert Octal number to Binary number, convert each digit of Octal umber to 3 digit binary number.
 Merge these binary numbers to get the result.

Ex 1: Convert the octal number 217 to binary Ex 2: Convert the octal number 653 to binary
number. number.

Converting Binary number to Octal number:

 To convert Binary number to octal number, separate the binary number to groups of 3 digits, starting from
right.
 Write octal number for each group, merge these groups to get the result.

Ex 1: Convert the binary number 110101011 to Ex 2: Convert the binary number

Octal number. 1111010001 to Octal number.

Digital Logic Design – Sudheer Kumar

03. Write about Hexa Decimal number system.
6
Hexa Decimal Number System:

 The ‘Hexa Decimal number system’ is base 16 number system.

 In Hexa Decimal number system, we use digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 & letters A, B, C, D, E, F.
 The letters A, B, C, D, E, F are used to represent 10, 11, 12, 13, 14, 15.
 In Hexa Decimal number system, position values are powers of 16.

Converting Hexa decimal to Decimal number:

 To convert Hexa decimal number to decimal number, multiply each digit in Hexa decimal number with its position
value. Add these products.
 Ex 1: Convert Hexa Decimal number 9C to decimal number.

9 C  face values
161 160  position values

Result = 9 x 161 + 12 x 160

= 9 x 16 + 12 x 1
= 144 + 12 = 156 base 10
 Ex 2: Convert Hexa Decimal number 1B7E to decimal number.
1 B 7 E  face values
163 162 161 160  position values

Result = 1 x 163 + 11 x 162 + 7 x 161 + 14 x 160

= 1 x 4096 + 11 x 256 + 7 x 16 + 14 x 1
= 4096 + 2816 + 112 + 14 = 7038

Converting Decimal number to Hexa decimal:

 To convert Decimal number to Hexa Decimal number, divide the decimal number by 16 & write the remainder.
 Repeat this process until the number can’t be divided by 16 anymore.

Ex 1: Convert the decimal number 156 to Hexa Ex 2: Convert the decimal number 125
Decimal number. to Hexa Decimal number.

Converting Hexa decimal to Binary number:

 To convert Hexa decimal number to Binary number, convert each digit of Hexa decimal number to 4 digit binary
number.
 Merge these binary numbers to get the result.

Digital Logic Design – Sudheer Kumar

 Ex 1: Convert the Hexa decimal number 6B2E to binary Ex 2: Convert the Hexa decimal number D8A to
number. binary number. 7

Converting Binary number to Hexa decimal:

 To convert Binary number to Hexa decimal, separate the binary number to groups of 4 digits., starting from right.
 Write Hexa decimal number for each group, merge these groups to get the result.

Ex 1: Convert the binary number 110101011 to Hexa Ex 2: Convert the binary number
decimal number. 100110111110 to Hexa decimal number.

Converting Hexa decimal to Octal number:

 Step 1: Convert Hexa decimal to Binary number.

 Step 2: Convert Binary number to Octal number.

Ex 1: Convert (9C)16 to Octal number. Step 2: Convert (10011100)2 to Octal number.

Step1: Convert (9C)16 to Binary number.

So (10011100)2 = (234)8
So (9C)16 = (10011100)2 So (9C)16 = (234)8

Converting Octal number to Hexa decimal number:

 Step 1: Convert Octal to Binary number.

 Step 2: Convert Binary number to Hexa decimal number.

Ex 1: Convert (177)8 to Hexa decimal number. Step 2: Convert (001111111)2 to Hexa Decimal
Step 1: Convert (177)8 to Binary number. number.

So (01111111)2 = (7F)16
So (177)8 = (7F)16.

Digital Logic Design – Sudheer Kumar

04. Explain r’s & (r-1)’s complement.
8
Types of Complement for a number system:
For a number system having its base/radix as r, we can define two types of complement for the corresponding
number system which are as follows:

1) (r-1)'s complement
The (r-1)'s complement of a number in any number system with base r can be found out by subtracting every single
digit of a number by r-1.

Example: In the binary number system, the base is 2. Hence, its (r-1)'s i.e., 2-1 =1. 1's complement can be obtained
by subtracting each bit from 1, i.e., 1's complement for 001 can also be calculated by subtracting 001 from 111 which
will be (111-001) = (110)2.

Similarly, in the octal number system, the base is 8 so its 7's complement can be calculated by subtracting each bit
by 7, i.e., 7's complement for 347 in octal number system can be calculated by subtracting 347 from 777 which will
be (777 – 347) = (430)8.

2) r's complement
The r's complement of a non-zero number in any number system with base r can be calculated by adding 1 to the
LSB (Least Significant Bit) of its (r-1)'s complement.

Example:
In binary number system, 2's complement of 001 can be calculated by adding 1 to the LSB of its 1'complement
(i.e., 110 + 1) = (111)2.

Similarly, in octal number system, 8's complement of 347 can be calculated by adding 1 to the LSB of its
7'complement (i.e., 430 + 1) = (431)8.

9's and 10's complement in Decimal Number System

The decimal number system has its base as 10. So 9's complement of decimal number can be found out by
subtracting its each digit by 9.

Example 1: Calculate 9's complement of (2457)10

Solution: 9999 – 2457 = (7542)10

Now, 10's complement of a decimal number can be calculated by adding 1 to the LSB of the 9's complement.

Example 2: Calculate 10's complement of (2457)10

Solution: 10's complement for (2457)10 is calculated by adding 1 to (7542)10 which is the 9's complement. Therefore,
10's complement of (2457)10 is (7543)10.

Digital Logic Design – Sudheer Kumar

05. Write about Signed Binary Numbers.
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Signed Binary Numbers:

Signed Binary Numbers use the MSB (Most Significant Bit) as a sign bit to display whether it is
positive number or negative number.

In mathematics, positive numbers (including zero) are represented as unsigned numbers. That is we
do not put the +ve sign in front of them to show that they are positive numbers. But when dealing
with negative numbers we use a -ve sign in front of the number to show that the number is negative
in value.
However, in digital circuits there is no provision made to put a plus or even a minus sign to a number,
since digital systems operate with binary numbers that are represented in terms of “0’s” and “1’s”.
An 8-bit binary number (a byte) can have a value ranging from 0 (00000000 2) to 255 (111111112),
that is 28 = 256 different combinations of bits forming a single 8-bit byte.
So, for example an unsigned binary number such as: 01001101 2 = 64 + 8 + 4 + 1 = 7710 in decimal.
But Digital Systems and computers must also be able to use and to manipulate negative numbers as
well as positive numbers.
Mathematical numbers are generally made up of a sign and a value (magnitude) in which the sign
indicates whether the number is positive ( + ) or negative ( – ) with the value indicating the size of the
number, for example 23, +156 or -274.
Presenting numbers in this fashion is called “sign-magnitude” representation since the left most
digit can be used to indicate the sign and the remaining digits the magnitude or value of the number.
For signed binary numbers the most significant bit (MSB) is used as the sign bit. If the sign bit is “0”,
this means the number is positive in value. If the sign bit is “1”, then the number is negative in value.
Then we can see that the Sign-and-Magnitude (SM) notation stores positive and negative values by
dividing the “n” total bits into two parts: 1 bit for the sign and n–1 bits for the value which is a pure
binary number. For example, the decimal number 53 can be expressed as an 8-bit signed binary
number as follows.
Positive Signed Binary Numbers

Digital Logic Design – Sudheer Kumar

Negative Signed Binary Numbers
10

Signed Binary Numbers Examples:

Convert the following decimal values into signed binary numbers using the sign-magnitude format:

-1510 as a 6-bit number ⇒ 1011112

+2310 as a 6-bit number ⇒ 0101112

-5610 as a 8-bit number ⇒ 101110002

+8510 as a 8-bit number ⇒ 010101012

-12710 as a 8-bit number ⇒ 111111112

Digital Logic Design – Sudheer Kumar

06. Explain Addition and Subtraction of unsigned and signed binary numbers.
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Unsigned Binary numbers – Addition:

Adding unsigned numbers in binary is quite easy. Addition is done exactly like adding decimal
numbers, except that you have only two digits (0 and 1). The only number facts to remember are that

0+0 = 0, with carry=0

1+0 = 1, with carry=0
0+1 = 1, with carry=0
1+1 = 0, with carry=1

To add the numbers 0610=01102 and 0710=01112 (answer=1310=11012) we can write out the
calculation (the results of any carry is shown along the top row).

Unsigned Binary numbers – Subtraction:

Binary subtraction is much easier than the decimal subtraction when you remember the following
rules:

 0 – 0 = 0
 0 – 1 = 1 ( with a borrow of 1)
 1 – 0 = 1
 1 – 1 = 0

Example:

Digital Logic Design – Sudheer Kumar

Signed Binary numbers – Addition:
12
Consider the two positive binary numbers A & B. We can perform the addition of these two numbers,
which is similar to the addition of two unsigned binary numbers.

Example 1

Let us perform the addition of two decimal numbers +7 and +4 as shown below.

The binary representations of +7 and +4 with 5 bits each are shown below.

+710 = 001112

+410 = 001002

The addition of these two numbers is

+710 + +410 = 001112 + 001002

⇒ +710 + +410 = 010112.

The resultant sum contains 5 bits. So, there is no carry out from sign bit. The sign bit ‘0’ indicates that
the resultant sum is positive. So, the magnitude of sum is 11 in decimal number system. Therefore,
addition of two positive numbers will give another positive number.

Example 2

Let us perform the addition of two decimal numbers -7 and -4 as shown below.
The binary representation of -7 and -4 with 5 bits each are shown below.

−710 = 101112
−410 = 101002

The addition of these two numbers is

−710 + −410 = 101112 + 101002

⇒ −710 + −410 = 1010112. ( MSB 1 represents negative number. So the result is -1110 in
decimal number system)

Signed Binary numbers – Subtraction:

Whenever we have to subtract a number B from number A, then take 2’s complement of B and add it
to A. So, mathematically we can write it as

A - B = A + 2′s complement of B

Similarly, if we have to subtract the number A from number B, then take 2’s complement of A and add
it to B. So, mathematically we can write it as

B - A = B + 2′s complement of A

So, the subtraction of two signed binary numbers is similar to the addition of two signed binary
numbers. But, we have to take 2’s complement of the number, which is supposed to be subtracted.

Digital Logic Design – Sudheer Kumar

 Example 1:
13
Let us perform the subtraction of two decimal numbers +7 and +4 using 2’s complement method.

The subtraction of these two numbers is

710 − 410 = 7 + 2’s complement of 4

= 0111 + 1100 = 0011 (carry has been ignored)

Here, the MSB (Most Significant Bit) is 0. It indicates that the resultant sum is positive.

Therefore, subtraction of two decimal numbers +7 and +4 is +3.

Example 2:

Let us perform the subtraction of two decimal numbers +4 and +7 using 2’s complement method.

The subtraction of these two numbers is

410 − 710 =4 + 2’s complement of 7

= 0100 + 1001 = 1101

Here, the MSB (Most Significant Bit) is 1. It indicates that the resultant sum is negative. So, by taking
2’s complement of it we will get the magnitude of resultant sum as 3 in decimal number system.

Therefore, subtraction of two decimal numbers +4 and +7 is -3.

07. Write about Weighted and Non-Weighted Binary codes.

Binary Code:

The digital data is represented, stored and transmitted as group of binary bits. This group is also called
as binary code.
These Binary codes are mainly categorized into two types: Weighted & Non Weighted codes.

Weighted Codes

Weighted binary codes are those binary codes which follows the positional weight principle. Each
position of the number represents a specific weight. Several systems of the codes are used to express
the decimal digits 0 through 9. In these codes each decimal digit is represented by a group of four bits.

Non-Weighted Codes

In this type of binary codes, the positional weights are not assigned. The examples of non-weighted
codes are Excess-3 code and Gray code.

Digital Logic Design – Sudheer Kumar

Excess-3 code
14
The Excess-3 code is also called as XS-3 code. It is non-weighted code used to express decimal
numbers. The Excess-3 code words are derived from the 8421 BCD code words adding (0011) 2 or
(3)10 to each code word in 8421. The excess-3 codes are obtained as follows −

Example :

Gray Code

It is the non-weighted code. That means there are no specific weights assigned to the bit position. It
has a very special feature that, only one bit will change each time the decimal number is incremented
as shown in the below figure. As only one bit changes at a time, the gray code is called as a unit
distance code. The gray code is a cyclic code. Gray code cannot be used for arithmetic operation.

Digital Logic Design – Sudheer Kumar

 Unit 2 : Logic Gates and Boolean Algebra
15
01. Write about Logic gates in Digital Electronics. [or]
Explain following gates : NOT, AND, OR, Universal gates (NAND, NOR),
X-OR, X-NOR

Logic Gates:

 A logic gate is a device that acts as a building block for digital circuits.
 They perform basic logical functions that are fundamental to digital circuits.
 Most electronic devices we use today will have some form of logic gates in them.
 For example, logic gates can be used in digital electronics such as smartphones, memory devices
(memory cards & pen drives).

 In a circuit, logic gates work based on a combination of digital signals coming from its inputs.
 Most logic gates have two inputs and one output, and they are based on Boolean algebra.
 At any given moment, every terminal is in one of the two binary conditions: True or False.
 False represents 0, and True represents 1.
 Logic gates are commonly used in integrated circuits (IC).

Types of Basic Logic Gates

 There are several basic logic gates used in performing operations in digital systems. The common ones
are

NOT Gate

AND Gate

OR Gate

XOR Gate

Additionally, these gates can also be found in a combination of one or two. Therefore, we get other
gates, such as NAND Gate, NOR Gate and XNOR Gate.

NOT Gate:

 A NOT gate is a logic gate that inverts the digital input signal. For this reason, a NOT gate is
sometimes is referred to as an inverter.
 A NOT gate always has high (logical 1) output when its input is low (logical 0).
 A NOT gate always has low (logical 0) output when the input is high (logical 1).
 The logical symbol for a NOT gate is shown below:

 ̅
The Boolean expression is Y = 𝐀
 It is read as Y equals NOT A.
 The truth table of NOT gate is as follows

Digital Logic Design – Sudheer Kumar

 AND Gate:
16
 In the AND gate, the output of an AND gate will be 1 if and only if all the inputs are 1.

 The Boolean expression of AND gate is Y = A.B

 The truth table of a two-input AND basic gate is given as

OR Gate:

 In an OR gate, the output of an OR gate will be 1 if one or more inputs are 1.

 The Boolean expression of the OR gate is Y = A + B, read as Y equals A ‘OR’ B.

 The truth table of a two-input OR basic gate is given as

XOR Gate:

 In an XOR gate, the output of a two-input XOR gate will be 1 if only one input is 1.

 ̅ .B + A.𝐁
The Boolean expression of the XOR gate is Y = 𝐀 ̅ or Y = A⊕B
 The truth table of an XOR gate is

Digital Logic Design – Sudheer Kumar

 NAND Gate:
17
 This basic logic gate is the combination of AND & NOT gates.

 The Boolean expression of the NAND gate is Y = ̅̅̅̅̅

𝐀. 𝐁
 The truth table of NAND gate is

NOR Gate:

 This gate is the combination of OR and NOT gates.

 The Boolean expression of the NAND gate is Y = ̅̅̅̅̅̅̅̅

𝐀+𝐁
 The truth table of NOR gate is

XNOR Gate:

 In the XNOR gate, the output is in state 1 when both inputs are the same, i.e. both 0 or both 1.

 The Boolean expression of the XNOR gate is Y = ̅̅̅̅̅̅̅̅̅

𝐀⊕𝐁
 The truth table of XNOR gate is

Digital Logic Design – Sudheer Kumar

02. Write about Boolean Laws & Theorems.
18
Boolean Laws:

There are six types of Boolean algebra laws. They are:

- Commutative law
- Associative law
- Distributive law
- AND law
- OR law
- Inversion law

- These six laws are explained in detail here.

Commutative Law

- Any binary operation which satisfies the following expression is referred to as a commutative operation.
Commutative law states that changing the sequence of the variables does not have any effect on the output of a
logic circuit.
A. B = B. A
A+B=B+A

Associative Law

- It states that the order in which the logic operations are performed is irrelevant as their effect is the same.
( A. B ). C = A . ( B . C )
( A + B ) + C = A + ( B + C)

Distributive Law

- Distributive law states the following conditions:

A. ( B + C) = (A. B) + (A. C)
A + (B. C) = (A + B) . ( A + C)

AND Law

- These laws use the AND operation. Therefore they are called AND laws.
A.0 = 0
A.1 = A
A.A = A
A.A’ = 0

OR Law

- These laws use the OR operation. Therefore they are called OR laws.
A+0 =A
A+1 =1
A+A =A
A + A’ = 1

Inversion Law

- In Boolean algebra, the inversion law states that double inversion of variable results in the original variable itself.
(A’)’ = A

Digital Logic Design – Sudheer Kumar

 19
Boolean Theorems:

- The two important theorems which are extremely used in Boolean algebra are De Morgan’s First law
and De Morgan’s second law.
- These two theorems are used to change the Boolean expression.
- This theorem basically helps to reduce the given Boolean expression in the simplified form.
- These two De Morgan’s laws are used to change the expression from one form to another form.

De Morgan’s First Law:

- De Morgan’s First Law states that (A.B)’ = A’+B’.
- The first law states that the complement of the product of the variables is equal to the sum of their
individual complements.
- The truth table that shows the verification of De Morgan’s First law is given as follows:

- The last two columns show that (A.B)’ = A’+B’.

- Hence, De Morgan’s First Law is proved.

De Morgan’s Second Law:

- De Morgan’s Second Law states that (A+B)’ = A’.B’.
- The Second law states that the complement of the sum of the variables is equal to the product of their
individual complements.
- The truth table that shows the verification of De Morgan’s Second law is given as follows:

- The last two columns show that (A+B)’ = A’.B’.

- Hence, De Morgan’s Second Law is proved.

Digital Logic Design – Sudheer Kumar

 20
03. Explain : Dual & Complement of a Logic function.

Steps in Finding the Dual of a Boolean Function (or) Expression:

- Interchange AND & OR operators.

- Interchange 0 & 1.
- Keep all literals as same.

- Example 1:
Boolean Expression : AB’C + A’BC + A’B’C’
Dual of the Above Expression : (A+B’+C).(A’+B+C).(A’+B’+C’)

Note : There is no change in complement

- Example 2:
Boolean Expression : (A+C).(A’+B)
Dual of the Above Expression : A.C + A’.B

- Example 3:
Boolean Expression : 01’ + 1’0 +10
Dual of the Above Expression : (1+0’).(0’+1).(0+1)

Steps in Finding the Complement of a Boolean Function (or) Expression:

- Interchange AND & OR operators.

- Interchange 0 & 1.
- Complement all literals.

- Example 1:
Boolean Expression : AB’C + A’BC + A’B’C’
Complement of the Above Expression : (A’+B+C’).(A+B’+C’).(A+B+C)

Note : There is change in complement

- Example 2:
Boolean Expression : (A+C).(A’+B)
Complement of the Above Expression : A’.C’ + A.B’

- Example 3:
Boolean Expression : 01’ + 1’0 +10
Complement of the Above Expression : (1+0’).(0’+1).(0+1)

Example: Convert following expression into Dual & Complement form : x’.y + x.y’

Given Expression : x’.y + x.y’ Dual form : (x’+y).(x+y’) Complement form : (x+y’).(x’+y)

Digital Logic Design – Sudheer Kumar

 21
04. Explain : Min terms & Max terms, Canonical & Standard forms.

Min terms & Max terms:

- We will get four Boolean product terms by combining two variables x and y with logical AND operation.
- These Boolean product terms are called as min terms or standard product terms.
- The min terms are x’y’, x’y, xy’ and xy.

- Similarly, we will get four Boolean sum terms by combining two variables x and y with logical OR operation.
- These Boolean sum terms are called as Max terms or standard sum terms.
- The Max terms are x + y, x + y’, x’ + y and x’ + y’.

- The following table shows the representation of min terms and MAX terms for 2 variables.

 If the binary variable is ‘0’, then it is represented as complement of variable in min term and as the variable itself
in Max term. Similarly, if the binary variable is ‘1’, then it is represented as complement of variable in Max term
and as the variable itself in min term.

 From the above table, we can easily notice that min terms and Max terms are complement of each other.

 If there are ‘n’ Boolean variables, then there will be 2n min terms and 2n Max terms.

Canonical SoP forms:

- Canonical SoP form means Canonical Sum of Products form.

- In this form, each product term contain all literals.
- So, these product terms are nothing but the min terms.
- Hence, canonical SoP form is also called as sum of min terms form.
- First, identify the min terms for which, the output variable is one and then do the logical OR of those min terms in
order to get the Boolean expression function corresponding to that output variable.
- This Boolean function will be in the form of sum of min terms.
- Follow the same procedure for other output variables also, if there are more than one output variables.

- Example :
Consider the following truth table:

 Here, the output f is 1 for two combinations of input.

 The corresponding min terms are p’q’, pq’. By doing logical OR of these two min terms, we will get the Boolean
function of output f.
 Therefore, the Boolean function of output is, f = p’q’ + pq’. This is the canonical SoP form of output, f.
 We can also represent this function in following two notations.

f = m0 + m2
f = Σm(0,2)

Digital Logic Design – Sudheer Kumar

 Canonical PoS forms:
22
- Canonical PoS form means Canonical Product of Sums form.
- In this form, each sum term contain all literals.
- So, these sum terms are nothing but the MAX terms.
- Hence, canonical PoS form is also called as product of Max terms form.
- First, identify the Max terms for which, the output variable is zero and then do the logical AND of those Max terms
in order to get the Boolean expression function corresponding to that output variable.
- This Boolean function will be in the form of product of Max terms.
- Follow the same procedure for other output variables also, if there are more than one output variables.

- Example :
Consider the following truth table:

 Here, the output f is 0 for two combinations of input.

 The corresponding Max terms are p+q’, p’+q’. By doing logical AND of these two Max terms, we will get the
Boolean function of output f.
 Therefore, the Boolean function of output is, f = (p+q’).(p’+q’). This is the canonical PoS form of output, f.
 We can also represent this function in following two notations.

f = M1.M3
f = ΠM(1,3)

Standard SoP forms:

- Standard SoP form means Standard Sum of Products form.

- In this form, each product term need not contain all literals.
- Therefore, the Standard SoP form is the simplified form of canonical SoP form.
- We will get Standard SoP form of output variable in two steps.
o Get the canonical SoP form of output variable
o Simplify the above Boolean function, which is in canonical SoP form.
- Follow the same procedure for other output variables also, if there is more than one output variable.

- Example:
Convert the following Boolean function into Standard SoP form.

f = p’q + pq’ + pq
 The given Boolean function is in canonical SoP form. Now, we have to simplify this Boolean function in order to get
standard SoP form.

 Step 1 − Use the Boolean OR law, x + x = x. That means, the Logical OR operation with any Boolean variable ‘n’
times will be equal to the same variable. So, we can write the last term pq one more time.
 f = p’q + pq’ + pq + pq

 Step 2 − Use Distributive law for 1st and 3rd terms, 2nd and 4th terms.
 f = q(p’+p) + p(q’+q)

 Step 3 − Use Boolean law, x + x’ = 1 for simplifying the terms present in each parenthesis.
 f = q.1 + p.1

 Step 4 − Use Boolean postulate, x.1 = x for simplifying above two terms.
 f=q+p

 This is the simplified Boolean function. Therefore, the standard SoP form corresponding to given canonical SoP
form is f = p+q

Digital Logic Design – Sudheer Kumar

 Standard PoS forms:
23
- Standard PoS form means Standard Product of Sums form.
- In this form, each sum need not contain all literals.
- Therefore, the Standard PoS form is the simplified form of canonical PoS form.
- We will get Standard PoS form of output variable in two steps.
o Get the canonical PoS form of output variable
o Simplify the above Boolean function, which is in canonical PoS form.
- Follow the same procedure for other output variables also, if there is more than one output variable.

- Example:
Convert the following Boolean function into Standard PoS form.

f = (p+q).(p’+q).(p+q’)
 The given Boolean function is in canonical PoS form. Now, we have to simplify this Boolean function in order to get
standard PoS form.

 Step 1 − Use the Boolean AND law, x.x = x. That means, the Logical AND operation with any Boolean variable ‘n’
times will be equal to the same variable. So, we can write the term p+q one more time.

f = (p+q).(p+q).(p’+q).(p+q’)

 Step 2 − Use Distributive law for 1st and 3rd terms, 2nd and 4th terms.

 f = (pp’+q).(p+qq’)

 Step 3 − Use Boolean law, x.x’ = 0 for simplifying the terms present in each parenthesis.
 f = (0+q).(p+0)

 Step 4 − Use Boolean postulate, x+0 = x for simplifying above two terms.
 f = q.p

This is the simplified Boolean function. Therefore, the standard PoS form corresponding to given canonical PoS
form is f = p.q

05. Write about Two level realization of Logic functions.

Two level realization of Logic functions:

The maximum number of levels that are present between inputs and output is two in two level logic. That
means, irrespective of total number of logic gates, the maximum number of different types of logic gates is two in
two level logic. Here, the outputs of first level Logic gates are connected as inputs of second level Logic gates.

Consider the four Logic gates AND, OR, NAND & NOR. Since, there are 4 Logic gates, we will get 16 possible ways
of realizing two level logic.

Those are AND-AND, AND-OR, AND-NAND, AND-NOR, OR-AND, OR-OR, OR-NAND, OR-NOR, NAND-AND, NAND-
OR, NAND-NAND, NAND-NOR, NOR-AND, NOR-OR, NOR-NAND, NOR-NOR.

These two level logic realizations can be classified into the following two categories.

 Degenerative form
 Non-degenerative form

Digital Logic Design – Sudheer Kumar

Degenerative Form
24
If the output of two level logic realization can be obtained by using single Logic gate, then it is called
as degenerative form.

Obviously, the number of inputs of single Logic gate increases. This is an advantage of degenerative form.

Only 6 combinations of two level logic realizations out of 16 combinations come under degenerative form. Those
are AND-AND, AND-NAND, OR-OR, OR-NOR, NAND-NOR, NOR-NAND.

AND-AND Logic

In this logic realization, AND gates are present in both levels. Below figure shows an example for AND-AND
logic realization.

We will get the outputs of first level logic gates as Y1=AB and Y2=CD

These outputs, Y1 and Y2 are applied as inputs of AND gate that is present in second level. So, the output of this
AND gate is

Y=Y1Y2

Substitute Y1 and Y2 values in the above equation.

Y=(AB)(CD)=ABCD

Therefore, the output of this AND-AND logic realization is ABCD. This Boolean function can be implemented by
using a 4 input AND gate. Hence, it is degenerative form.

AND-NAND Logic

In this logic realization, AND gates are present in first level and NAND gates are present in second level.

The following figure shows an example for AND-NAND logic realization.

We got the outputs of first level logic gates as Y1=AB and Y2=CD

These outputs,Y1 and Y2 are applied as inputs of NAND gate that is present in second level. So, the output of this
NAND gate is Y=(Y1Y2)′

Substitute Y1 and Y2 values in the above equation. Y=((AB)(CD))′ = (ABCD)’

Therefore, the output of this AND-NAND logic realization is (ABCD)′. This Boolean function can be implemented by
using a 4 input NAND gate. Hence, it is degenerative form.

Digital Logic Design – Sudheer Kumar

OR-OR Logic
25
In this logic realization, OR gates are present in both levels. The following figure shows an example for OR-OR
logic realization.

We will get the outputs of first level logic gates as Y1=A+B and Y2=C+D.

These outputs, Y1 and Y2 are applied as inputs of OR gate that is present in second level. So, the output of this
OR gate is Y=Y1+Y2

Substitute Y1 and Y2 values in the above equation. Y=(A+B)+(C+D) = A+B+C+D

Therefore, the output of this OR-OR logic realization is A+B+C+D. This Boolean function can be implemented by
using a 4 input OR gate. Hence, it is degenerative form.

Similarly, OR-NOR, NAND-NOR, NOR-NAND are also degenerative forms.

Non-degenerative Form

If the output of two level logic realization can’t be obtained by using single logic gate, then it is called as non-
degenerative form.

The remaining 10 combinations of two level logic realizations come under non degenerative form. Those are
AND-OR, AND-NOR, OR-AND, OR-NAND, NAND-AND, NAND-OR, NAND-NAND, NOR-AND, NOR-OR, NOR-NOR.

AND-OR Logic

In this logic realization, AND gates are present in first level and OR gates are present in second level. Below figure
shows an example for AND-OR logic realization.

Previously, we got the outputs of first level logic gates as Y1=AB and Y2=CD.

These outputs, Y1 and Y2 are applied as inputs of OR gate that is present in second level. So, the output of this
OR gate is Y = Y1+Y2

Substitute Y1 and Y2 values in the above equation Y=AB+CD

Therefore, the output of this AND-OR logic realization is AB+CD. This Boolean function is in Sum of
Products form. Since, we can’t implement it by using single logic gate, this is a non-degenerative form.

Digital Logic Design – Sudheer Kumar

AND-NOR Logic
26
In this logic realization, AND gates are present in first level and NOR gates are present in second level. The
following figure shows an example for AND-NOR logic realization.

We know the outputs of first level logic gates as Y1=AB and Y2=CD

These outputs, Y1 and Y2 are applied as inputs of NOR gate that is present in second level. So, the output of this
NOR gate is Y = (Y1+Y2)′

Substitute Y1 and Y2 values in the above equation. Y=(AB+CD)′

Therefore, the output of this AND-NOR logic realization is (AB+CD)′. This Boolean function is in AND-OR-
Invert form. Since, we can’t implement it by using single logic gate, this is a non-degenerative form.

OR-AND Logic

In this logic realization, OR gates are present in first level & AND gates are present in second level. The following
figure shows an example for OR-AND logic realization.

We got the outputs of first level logic gates as Y1=A+B and Y2=C+D.

These outputs, Y1 and Y2 are applied as inputs of AND gate that is present in second level. So, the output of this
AND gate is Y=Y1Y2

Substitute Y1 and Y2 values in the above equation. Y=(A+B)(C+D)

Therefore, the output of this OR-AND logic realization is (A+B)(C+D). This Boolean function is in Product of
Sums form. Since, we can’t implement it by using single logic gate, this is a non-degenerative form.

Digital Logic Design – Sudheer Kumar

06. Explain about minimization of logic functions. 27
Minimization of Logic functions:

- The process of simplifying the algebraic expression of a Boolean function is called minimization.
Minimization is important since it reduces the cost and complexity of the associated circuit.

- For example, the function F= x’y’z + x’yz + xy’ can be minimized to F= xy’ + x’z. The circuits
associated with above expressions is –

 It is clear from the above image that the minimized version of the expression takes a less number of logic
gates and also reduces the complexity.
 Minimization is important to find the most economic representation of a Boolean function.
 Minimization can be done using Algebraic Manipulation or K-Map method.

Minimization using Algebraic Manipulation:

 This method is the simplest of all methods used for minimization. It is suitable for medium sized
expressions involving 4 or 5 variables. Algebraic manipulation is a manual method, hence there is a
chance for human error.

 Following are the common Laws used in algebraic manipulation :

 A + A’ =1 & A.A’ = 0
 A + 1 =1 & A.1 = A
 A + A’B =A+B
 A + AB =A

Example 1: Minimize the following Boolean function using algebraic manipulation.

F = x’y’z + x’yz + xy’
= x’z(y’+y) + xy’
= x’z + xy’

Example 2: Minimize the following Boolean function using algebraic manipulation.

F = p’q’rs + p’q’r’s + p’qr’s + p’q’r’s + p’sq + p’sr
= p’q’s(r+r’) + p’r’s(q+q’) + p’s(q+r)
= p’q’s + p’r’s + p’s(q+r)
= p’s(q’+r’) + p’s(q+r)
= p’s(q’+r’+q+r)
= p’s

Digital Logic Design – Sudheer Kumar

Minimization using K-Maps (Karnaugh Maps):
28
 A Karnaugh map or a K-map refers to a pictorial method that is utilized to minimize various Boolean
expressions without using the Boolean algebra laws & theorems.
 A Karnaugh map can be a special version of the truth table. We can easily minimize various expressions that
have 2 to 4 variables using a K-map.

Solving an Expression Using K-Map

 Here are the steps that are used to solve an expression using the K-map method:
 Select a K-map according to the total number of variables.
 Identify maxterms or minterms as given in the problem.
 For SOP, put the 1’s in the blocks of the K-map with respect to the minterms (elsewhere 0’s).
 For POS, putting 0’s in the blocks of the K-map with respect to the maxterms (elsewhere 1’s).
 Making rectangular groups that contain the total terms in the power of two, such as 2,4,8...(except 1) and try
to cover as many numbers of elements as we can in a single group.
 From the groups that have been created in previous step, find the product terms and then sum them up for
the SOP form.

SoP form:

Example 1:
3 variables K-Map : F(A,B,C) = Σ A,B,C (1,3,6,7)

From 1st row 2nd & 3rd columns, product term will be : A’C
From 2nd row 3rd & 4th columns, product term will be : AB
If we sum these product terms, we will get the final expression : A’C + AB

Example 2:
4 variables K-Map : F(P,Q,R,S) = Σ P,Q,R,S (0,2,5,7,8,10,13,15)

From the middle square, the product term will be : QS

From the edge squares, the product term will be : Q’S’
If we sum these product terms, we will get the final expression : QS + Q’S’

Digital Logic Design – Sudheer Kumar

PoS form:

Example 1:
29
3 variables K-Map : F(A,B,C) = Π A,B,C (0,3,6,7)

From the 2nd row & 3rd 4th columns group, the term will be : A’+B’
From the 1st 2nd rows & 3rd column group, the term will be : B’+C’
From the 1st row & 1st column group, the term will be : A+B+C

If we take the product of these three terms, then we will get this final expression – (A’+B’)(B’+C’)(A+B+C)

Example 2:
4 variables K-Map : F(A,B,C,D) = Π (3,5,7,8,10,11,12,13)

From the 3rd 4th rows & 1st column group, the term will be : A’+C+D
From the 2nd 3rd rows & 2nd column group, the term will be : B’+C+D’
From the 1st 2nd rows & 3rd column group, the term will be : A+C’+D’
From the 4th row & 3rd 4th columns group, the term will be : A’+B+C’

If we take the product of these four terms, we will get this final expression :

F = (A’+C+D)(B’+C+D’)( A+C’+D’)(A’+B+C’)

Digital Logic Design – Sudheer Kumar

07. Write about don’t care conditions in K-Maps. 30
don’t care conditions in K-Maps:

- One of the very significant and useful concepts in simplifying the output expression using K -Map is the concept
of “Don’t Care”.
- The “Don’t Care” conditions allow us to replace the empty cell of a K-Map to form a grouping of the variables.
- While forming groups of cells, we can consider a “Don’t Care” cell as 1 or 0 or we can also ignore that cell.
- A Don’t Care cell can be represented by a cross(X) or minus(-) or phi(Φ) in K-Maps representing an invalid
combination.

Example-1:

Minimise the following function in SOP minimal form using K-Maps:

f = m(1, 5, 6, 11, 12, 13, 14) + d(4)

The SoP K-Map for the given expression is:

Therefore, the SoP minimal is : f = BC' + BD' + A'C'D + AB'CD

Example-2:

Minimise the following function in PoS minimal form using K-Maps:

F(A,B,C,D) = m(0,1,2,3,4,5) + d(10,11,12,13,14,15)

Writing the given expression in PoS form:

F(A,B,C,D) = M(6,7,8,9) + d(12,13,14,15)

The PoS K-Map for the given expression is:

Therefore, the PoS minimal is :F = (A’+C)(B’+C’)

Digital Logic Design – Sudheer Kumar

 Unit 3 : Combinational Logic Circuits - I
31
01. What are Combinational Logic circuits? Explain.

Combinational Logic Circuits:

- The combinational logic circuits are the circuits that contain different types of logic gates.
- Simply, a circuit in which different types of logic gates are combined is known as a combinational logic circuit.
- The output of the combinational circuit is determined from the present combination of inputs, regardless of the
previous input.
- The input variables, logic gates, and output variables are the basic components of the combinational logic circuit.
- There are different types of combinational logic circuits, such as Adder, Subtractor, Decoder, Encoder, Multiplexer,
and De-multiplexer.
- Following are the characteristics of combinational logic circuits:

 At any instant of time, the output of the combinational circuits depends only on the present input terminals.
 The combinational circuit doesn't have any backup or previous memory. The present state of the circuit is not
affected by the previous state of the input.
 The n number of inputs and m number of outputs are possible in combinational logic circuits.

 The 'n' input variable comes from the external source while the 'm' output variable goes to the external
destination.
 In many applications, the source or destinations are storage registers.

Half Adder

 The half adder is a basic building block having two inputs and two outputs.
 The adder is used to perform OR operation of two single bit binary numbers.
 The carry and sum are two output states of the half adder.

Full Adder

 The half adder is used to add only two numbers.

 To overcome this problem, the full adder was developed.
 The full adder is used to add three 1-bit binary numbers A, B, and carry C.
 The full adder has three input states and two output states i.e., sum and carry.

Half Subtractors

 The half subtractor is also a building block of subtracting two binary numbers.
 It has two inputs and two outputs.
 This circuit is used to subtract two single bit binary numbers A and B. The 'diff' and 'borrow' are the two output
states of the half adder.

Full Subtractors

 The Half Subtractor is used to subtract only two numbers.

 To overcome this problem, full subtractor was designed.
 The full subtractor is used to subtract three 1-bit numbers A, B, and C, which are minuend, subtrahend,
and borrow.
 The full subtractor has three input states and two output states i.e., diff and borrow.

Digital Logic Design – Sudheer Kumar

 Multiplexers
32
 The multiplexer is a combinational circuit that has n-data inputs and a single output.
 It is also known as the data selector which selects one input from the inputs and routes it to the output.
 With the help of the selected inputs, one input line from the n-input lines is selected.
 The enable input is denoted by E.

De-multiplexers

 A De-multiplexer performs the reverse operation of a multiplexer.

 The de-multiplexer has only one input, which is distributed over several outputs.
 One output line is selected at a time by selecting lines.
 The input is transmitted to the selected output line.

Decoder

 A decoder is a combinational circuit having n inputs and to a maximum of m = 2 n outputs.

 The decoder is the same as the de-multiplexer.
 The only difference between de-multiplexer and decoder is that in the decoder, there is no data input.
 The decoder performs an operation that is completely opposite of an encoder.

Encoder

 The encoder is used to perform the reverse operation of the decoder.

 An encoder having n number of inputs and m number of outputs is used to produce m-bit binary code which is
related to the digital input number.
 The encoder takes the digital word and converts it into another digital word.

02. Explain designing half adder & full adder.

Half Adder:

- The Half-Adder is a basic building block of adding two numbers as two inputs and produce two outputs. The adder
is used to perform OR operation of two single bit binary numbers. The augend and addend bits are two input
states, and 'carry' and 'sum' are two output states of the half adder.

- Block diagram

Truth Table

Digital Logic Design – Sudheer Kumar

 In the above table,
33
1. 'A' and' B' are the input states, and 'sum' and 'carry' are the output states.
2. The carry output is 0 in case where both the inputs are not 1.
3. The least significant bit of the sum is defined by the 'sum' bit.

The SOP form of the sum and carry are as follows:

Sum = A'.B + A.B'

Carry = A.B

Construction of Half Adder Circuit:

In the block diagram, we have seen that it contains two inputs and two outputs. The augend and addend bits are
the input states, and carry and sum are the output states of the half adder. The half adder is designed with the
help of the following two logic gates:
 2-input Exclusive-OR Gate or XOR Gate.
 2-input AND Gate.

2-input Exclusive-OR Gate or XOR Gate

The Sum bit is generated with the help of the Exclusive-OR or XOR Gate.

The above is the symbol of the XOR gate. In the above diagram, 'A' and 'B' are the inputs, and the 'SUMOUT' is
the final outcome after performing the XOR operation of both numbers.

The truth table of the EX-OR gate is as follows:

From the above table, it is clear that the XOR gate gives the result 1 when both of the inputs are different. When
both of the inputs are the same, the XOR gives the result 0.

2-input AND Gate:

The XOR gate is unable to generate the carry bit. For this purpose, we use another gate called AND Gate. The AND
gate gives the correct result of the carry.

Digital Logic Design – Sudheer Kumar

 The above is the symbol of the AND gate. In the above diagram, 'A' and 'B' are the inputs, and 'OUT' is the final
outcome after performing AND operation of both numbers. 34
There is the following truth table of AND Gate:

From the above table, it is clear that the AND gate gives the result 1 when both of the inputs are 1. When both of
the inputs are different and 0, the AND gates gives the result 0.

Half-Adder logical circuit:

So, the Half Adder is designed by combining the 'XOR' and 'AND' gates and provide the sum and carry.

There is the following Boolean expression of Half Adder circuit:

Sum = A XOR B (A⊕B)
Carry = A AND B (A.B)

Full Adder:

 Full Adder is the adder that adds three inputs and produces two outputs.
 The first two inputs are A and B and the third input is an input carry as C-IN.
 The output carry is designated as C-OUT and the normal output is designated as S which is SUM.
 The C-OUT is also known as the majority 1’s detector, whose output goes high when more than one input is
high.
 We use a full adder because when a carry-in bit is available, another 1-bit adder must be used since a 1-bit
half-adder does not take a carry-in bit. A 1-bit full adder adds three operands and generates 2-bit results.

Digital Logic Design – Sudheer Kumar

Full Adder Truth table:
35

Logical Expression for SUM:

A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’ + A B C-IN = C-IN (A’ B’ + A B) + C-IN’ (A’ B + A B’)
= C-IN ⊕ (A ⊕ B)
= (1,2,4,7)

Logical Expression for C-OUT:

A’BC-IN + AB’C-IN + ABC-IN’ + ABC-IN = AB + C-IN(A’B + AB’) = AB+C-IN(A⊕B)
= (3,5,6,7)

Full Adder Logic Circuit:

Implementation of Full Adder using Half Adders:

2 Half Adders and an OR gate is required to implement a Full Adder.

With this logic circuit, two bits can be added together, taking a carry from the next lower order of magnitude,
and sending a carry to the next higher order of magnitude.

Digital Logic Design – Sudheer Kumar

03. Explain designing half subtractor & full subtractor.
36
Half Subtractor:

- A half subtractor is a digital logic circuit that performs binary subtraction of two single -bit binary numbers.
- It has two inputs, A and B, and two outputs, DIFFERENCE and BORROW.
- The DIFFERENCE output is the difference between the two input bits, while the BORROW output indicates
whether borrowing was necessary during the subtraction.
- The half subtractor can be implemented using basic gates such as XOR and NOT gates. The DIFFERENCE output
is the XOR of the two inputs A and B, while the BORROW output is the NOT of input A and the AND of inputs A
and B.
- It produces the difference between the two binary bits at the input and also produces an output (Borrow) to
indicate if a 1 has been borrowed.
- In the subtraction (A-B), A is called a Minuend bit and B is called a Subtrahend bit.

Truth Table:

The SOP form of the Difference and Borrow is as follows:

Difference = A'B+AB'
Borrow = A'B

Implementation:

Logical Expression:

Difference =A⊕B
Borrow = A’.B

Digital Logic Design – Sudheer Kumar

 Full Subtractor:
37
 A full subtractor is a combinational circuit that performs subtraction involving three bits.
 It accepts three inputs: A (minuend), B (subtrahend) and a Bin (borrow bit) and it produces two outputs:
D (difference) and Bout (borrow out). The logic symbol and truth table are shown below.

Truth table for Full Subtractor:

From the above Truth table, we can find following Boolean expressions:

D = A’B’Bin + A’BBin’ + AB’Bin’ + ABBin

= Bin(A’B’+AB) + Bin’(A’B+AB’)
= Bin(A⊕B)’ + Bin’(A⊕B)
= A⊕B⊕Bin

Bout = A’B’ Bin + A’B Bin’ + A’B Bin +AB Bin

= Bin(A’B’+AB) + A’B (Bin’+ Bin)
= Bin(A⊕B)’ + A’B

Implementation:
From the above Boolean expressions, We can draw the full subtractor circuit as shown below:

Circuit diagram of Full Subtractor

Digital Logic Design – Sudheer Kumar

04. Explain Ripple Adders and Subtractors.
38
Ripple Adders (or) Ripple Carry Adders (or) Ripple Parallel Adders :

- In digital electronics, adding two bits can be possible by using half adder.
- If the input sequence has three bits, then the addition process can be completed by using a full adder.
- A ripple carry adder is a digital circuit that produces the arithmetic sum of two binary numbers of n number of
bits.
- It can be constructed with full adders connected in cascaded, with the carry output from each full adder
connected to the carry input of the next full adder in the chain.
- One of the most important point to be considered in this carry adder is the final output is known only after the
carry outputs are generated by each full adder stage and forwarded to its next stage. So there will be a delay to
get the result with using of this carry adder.
- There are various types in ripple-carry adders. They are:
4-bit ripple-carry adder
8-bit ripple-carry adder
16-bit ripple-carry adder

4-bit ripple-carry adder:

- The below diagram represents the 4-bit ripple-carry adder.

- In this adder, four full adders are connected in cascade. Co is the carry input bit and it is zero always.
- When this input carry ‘Co’ is applied to the two input sequences A1 A2 A3 A4 and B1 B2 B3 B4 then output
represented with S1 S2 S3 S4 and output carry C4.

Working of 4-bit Ripple Carry Adder

- Let’s take an example of two input sequences 0101 and 1010. These are representing the A4 A3 A2 A1 and
B4 B3 B2 B1.
- As per this adder concept, input carry C0 is 0.
- At 1st full adder : A1 =1 ; B1=0 ; C0=0
- Sum (S1) and carry (C1) will be generated as per the Sum and Carry equations of this adder.
- As per equations, for 1st full adder S1 =1 and Carry output i.e., C1=0.
- Same like for next input bits A2 and B2, output S2 = 1 and C2 = 0. Here the important point is the second stage
full adder gets input carry i.e., C1 which is the output carry of initial stage full adder.
- Like this we will get the final output sequence (S4 S3 S2 S1) = (1 1 1 1) and Output carry C4 = 0

8-bit ripple-carry adder:

- The below diagram represents the 8-bit ripple-carry adder.

- In this adder, eight full adders are connected in cascade. Co is the carry input bit and it is zero always.
- When this input carry ‘Co’ is applied to the two input sequences A1 A2 A3 A4 A5 A6 A7 A8 and
B1 B2 B3 B4 B5 B6 B7 B8 then output represented with S1 S2 S3 S4 S5 S6 S7 S8 and output carry C8.
- The addition process in an 8-bit ripple-carry-adder is the same principle which is used in a 4-bit ripple-carry-adder
i.e., each bit from two input sequences are going to added along with input carry.

Digital Logic Design – Sudheer Kumar

 39

Advantages of Ripple Carry Adders:

- Using this adder, we can perform addition process for n-bit sequences to get accurate results.
- The designing of this adder is not a complex process.
- Ripple adders are used in many applications where speed is not important.

Disadvantages:

- The first disadvantage is that ripple adders are slower than other types of adders.
- This is due to the carry “rippling” through the stages of the adder. The carry must propagate through all of the
logic gates in the ripple adder before the final sum is produced.
- This takes a significant amount of time, which can impact the performance of the overall system.
- Ripple adders are also more likely to produce errors when there is a large number of bits to be added.

Ripple Subtractors (or) Ripple Borrow Subtractors (or) Ripple Parallel Subtractors:

- Subtractors use two N-bit operands to produce an N-bit result and a borrow out signal.
- Subtractor circuits are rarely encountered in digital systems.
- Like adders, the simplest subtracting circuits perform subtraction bit-by-bit from the LSB to the MSB.
- The design process closely follows adder design, in that sample subtraction problems can be studied to gain
insight into subtractor requirements, a truth table can be prepared based on the observations, and then a circuit
can be designed from the truth table.
- Once a bit-slice subtractor circuit has been designed, it can be replicated N time to create an N-bit subtractor.
- The full-subtractor circuit differs only slightly from the full-adder, in that the subtractor requires two inverters that
are not needed by the adder.

- The full-subtractor can be used to build Ripple Borrow Subtractor (RBS) that can subtract any two N-bit
numbers, but RBS circuits suffer from the same slow operation as Ripple Carry Adder (RCA) circuits.

Digital Logic Design – Sudheer Kumar

 Example:
40
- Consider subtracting two 4-bit binary numbers, 1110 – 0111, as shown in example.
- In the first column, A1 is less than B1 (0 < 1), thus we must borrow from the second column A2
resulting 2 – 1 = 1.
- In the second column, A2 = 0 because of the previously mentioned borrow. So we must borrow from the third
column A3 resulting 2 – 1 = 1.
- In the third column, A3 = 0, resulting from the borrow operation generated by the second column. So we must
borrow from the fourth column A4 resulting 2 – 1 = 1.
- Lastly, in the fourth column, A4 = 0 resulting 0 – 0 = 0.

Ripple Subtractor circuit using Full Adders:

- Constructing Ripple Subtractor is also possible by making a slight modification to an adder circuit, and then to use
the modified adder as a subtractor.
- Following this method, if the number to be subtracted is made negative, then it can simply be added to the first
number.
- As an example, the operation ‘5 - 3’ can be written as ‘5 + (-3)’. This, of course, requires a method of
representing negative numbers in a digital circuit.
- We know that A-B = A+(2’s complement of B).
- 2’s Complement of B = 1’s Complement of B + 1.
- In the circuit, 1’s complement of B is obtained with the NOT gate & 1 can be added to the sum through the input
carry.

Digital Logic Design – Sudheer Kumar

 Unit 4 : Combinational Logic Circuits - II
41
01. Write about Encoders.

Encoders:

- The combinational circuits that change the binary information into N output lines are known as Encoders.
- The binary information is passed in the form of 2N input lines.
- The output lines define the N-bit code for the binary information.
- For example, in 4X2 encoder, if we give 4 inputs it produces only 2 outputs.
- In simple words, the Encoder performs the reverse operation of the Decoder.
- At a time, only one input line is activated for simplicity. The produced N-bit output code is equivalent to the binary
information.
- The schematic diagram for encoder is shown below:

1 1
2 MxN 2
3 Encoder 3
….. …..
M N

- In the above diagram, the number of inputs is M i.e. 2N & the number of outputs is N.

4 x 2 Encoder:

 The 4 to 2 Encoder consists of four inputs I3, I2, I1 & I0, and two outputs Y1 & Y0. At any time, only one
of these 4 inputs can be ‘1’ in order to get the respective binary code at the output. The figure below shows the
logic symbol of the 4 to 2 encoder.

I3 4x2 Y1
I2
Encoder
I1
Y0
I0

The Truth table of 4x2 encoders will be as shown below:

Logical expressions: Y1 = I3 + I2 Y0 = I1 + I3
These two Boolean functions can be implemented using two input OR gates as shown below:

Digital Logic Design – Sudheer Kumar

 8 x 3 Encoder:
42
 The 8 to 3 Encoder consists of eight inputs I7, I6, I5, I4, I3, I2, I1 & I0, and three outputs Y2, Y1 & Y0.
At any time, only one of these 8 inputs can be ‘1’ in order to get the respective binary code at the output. The
figure below shows the logic symbol of the 8 to 3 encoder.

I7
I6
8x3 Y2
I5
I4 Encoder Y1
I3 Y0
I2
I1
I0

The Truth table of 4x2 encoders will be as shown below:

Logical expressions: Y2 = I7+I6+I5+I4

Y1 = I7+I6+I3+I2
Y0 = I7+I5+I3+I1

These three Boolean functions can be implemented using four input OR gates as shown below:

Application of Encoders:

 Encoders are very common electronic circuits used in all digital systems.
 Encoders are used to translate the decimal values to the binary in order to perform binary functions such as
addition, subtraction, multiplication, etc.
 Other applications especially for Priority Encoders may include detecting interrupts in microprocessor
applications.

Digital Logic Design – Sudheer Kumar

02. What are ‘Priority Encoders’? Explain.
43
Priority Encoders:

- In case of an ordinary encoder, one and only one decimal input can be activated at any given time. But in the case
of some practical digital systems, two or more decimal inputs can unintentionally become active at the same time
that might cause a confusion.
- These problems can be solved with the help of priority encoder.
- In digital electronics, a combinational logic circuit which produces outputs in response to only one input among all
those that may be activated at the same time is called a priority encoder.
- According to the priority system, the decimal input having largest magnitude among all the simultaneous inputs is
encoded.
- Hence, as per this priority encoding system, the priority encoder would encode 4 if both 4 and 2 are active at the
same time.

4 input Priority Encoder:

 It has three outputs designated by A, B, and V. Where, A and B are the ordinary outputs and V is the output that
acts as a valid bit indicator.
 This third output V is set to 1 when one or more inputs are equal to 1. In the case, when all the inputs to the
encoder are equal to 0, there is no any valid input, and thus the output V is set to 0.
 The other two outputs, i.e. A and B of the encoder are not determined when V is equal to 0. Therefore, when, V is
equal to 0, the outputs A and B are specified as "don’t care conditions".
 The truth table of the 4-input priority encoder is shown below.

 From this truth table, it can be observed that the higher the subscript number of the input, the higher the priority
of the input. Thus, the input I3 has the highest priority. Therefore, regardless of the values of other inputs, when
the input I3 is equal to 1, the output for AB is 11, i.e. 3. The input I2 has the next lower priority, and then I1, and
finally I0 has the lowest priority.

 We can write the Boolean expression for outputs A, B, and V from the above table as follows,

 A = I3+I3’ I2 = I3 +I2

 B = I3+I3’ I2’ I1 = I3 +I2’ I1 And V = I3+ I2+ I1+ I0

 Hence, the condition for the output V is an OR operation of all the input variables.

The logic circuit of the 4-input priority encoder is shown below:

Digital Logic Design – Sudheer Kumar

03. Write about Decoders.
44
Decoders:

- Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2n output lines. One of these outputs
will be active High based on the combination of inputs present, when the decoder is enabled.
- The outputs of the decoder are nothing but the min terms of ‘n’ input variables, when it is enabled.

2 x 4 Decoder

In the 2x4 decoder, two inputs are A1 & A0 and four outputs are Y3, Y2, Y1 & Y0.
The block diagram of 2 to 4 decoder is shown in the following figure.

One of these four outputs will be ‘1’ for each combination of inputs when enable, E is ‘1’.

The Truth table of 2 to 4 decoder is shown below.

From Truth table, we can write the Boolean functions for each output as
Y3 = E.A1.A0
Y2 = E.A1.A0′
Y1 = E.A1′.A0
Y0 = E.A1′.A0′

Each output is having one product term. So, there are four product terms in total. We can implement these four
product terms by using four AND gates having three inputs each & two inverters.

The circuit diagram of 2x4 decoder is shown in the following figure.

 Therefore, the outputs of 2 to 4 decoder are nothing but the min terms of two input variables A1 & A0, when
enable, E is equal to one. If E is zero, then all the outputs of decoder will be equal to zero.
 Similarly, 3 to 8 decoder produces eight min terms of three input variables A2, A1 & A0 and 4 to 16 decoder
produces sixteen min terms of four input variables A3, A2, A1 & A0.

Digital Logic Design – Sudheer Kumar

04. What are ‘Higher Order Decoders’? Explain.
45
Implementation of Higher Order Decoders:

let us implement the following two higher-order decoders using lower-order decoders.
- 3 x 8 decoder
- 4 x 16 decoder

3x8 Decoder:
 We can implement 3x8 decoder using 2x4 decoders.
 We know that 2x4 Decoder has two inputs, A1 & A0 and four outputs, Y3 Y2 Y1 and Y0. Whereas, 3x8 Decoder has
three inputs A2, A1 & A0 and eight outputs, Y7 Y6 Y5 Y4 Y3 Y2 Y1 & Y0.
 We can find how many lower order decoders required for implementing higher order decoder using the following
formula:

Required number of Lower order decoders = m2/m1

Here, m1 is the number of outputs of lower order decoder & m2 is the number of outputs of higher order decoder.
So, to implement 3x8 decoder, required number of 2x4 decoders = 8/4 = 2
The block diagram of 3x8 using 2x4 decoders is shown below:

 The parallel inputs A1 & A0 are applied to each 2x4 decoder. The complement of input A2 is connected lower 2x4
decoder in order to get the outputs, Y3 to Y0. These are the lower four min terms. The input, A2 is directly
connected to upper 2x4 decoder in order to get the outputs, Y7 to Y4. These are the higher four min terms.

4x16 Decoder:
 We can implement 4x16 decoder using 3x8 decoders.
 We know that 3x8 Decoder has three inputs, A2 A1 & A0 and eight outputs, Y7 Y6 Y5 Y4 Y3 Y2 Y1 and Y0. Whereas,
4x16 Decoder has four inputs A3 A2 A1 & A0 and sixteen outputs, Y15 to Y0.
 We can find how many lower order decoders required for implementing higher order decoder using the following
formula:

Required number of Lower order decoders = m2/m1

Here, m1 is the number of outputs of lower order decoder & m2 is the number of outputs of higher order decoder.
So, to implement 4x16 decoder, required number of 3x8 decoders = 16/8 = 2

The block diagram of 4x16 using 3x8 decoders is shown below:

Digital Logic Design – Sudheer Kumar

 46

 The parallel inputs A2, A1 & A0 are applied to each 3x8 decoder. The complement of input, A3 is connected to lower
3x8 decoder in order to get the outputs, Y7 to Y0. These are lower eight min terms. The input, A3 is directly
connected to upper 3x8 decoder in order to get the outputs, Y15 to Y8. These are higher eight min terms.

05. Write about Multiplexers.

Multiplexers:

 In electronics, a multiplexer (or mux) is a device that selects one of many analog or digital input signals and
forwards the selected input into a single line.
 A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output.
 A multiplexer is also called a data selector. Multiplexers can also be used to implement Boolean functions of
multiple variables.
 An electronic multiplexer makes it possible for several signals to share one device or resource, for example, one
communication line, instead of having one device per each input signal.
 In the following diagram, 4X1 MUX is used to selects one of four inputs (I0, I1, I2, I3) and forwards into a single
output (Y).

 In the above diagram, S0 and S1 are called selectors (or) select lines. S0 is the LSB (Least significant Bit) & S1 is
the MSB (Most Significant Bit).

Advantages of Multiplexers:

 Reduces number of wires.

 Reduces circuit complexity and cost.
 It simplifies logic design.
 We can implement various combinational circuits using MUX.
 Multiplexers does not need Karnaugh Maps (K-Maps) and simplification.

Types of Multiplexers:
 There are many types of multiplexers based on the number of input lines.
Ex: 2X1 MUX, 4X1 MUX, 8X1 MUX, 16X1 MUX, 32X1 MUX etc.
 The relation between the number of input lines & the number of selectors will be as shown below. m = log2n
Here ‘n’ is number of input lines & ‘m’ is number of selectors.
 In a 2X1 Mux, we need 1 selector. [log22 = 1]
 In a 4X1 Mux, we need 2 selectors. [log24 = 2]
 In a 8X1 Mux, we need 3 selectors. [log28 = 3]
 In a 16X1 Mux, we need 4 selectors. [log216 = 4]
 In a 32X1 Mux, we need 5 selectors. [log232= 5]

Digital Logic Design – Sudheer Kumar

 2X1 MUX:
47
 In these multiplexers, there will be 2 input lines & one output line.
 The number of selectors will be log22 = 1.
 The design will be as shown below.

I0 2X1
Y
I1 MUX

E
S0

 In the above diagram, I0 and I1 are the two input lines.

 S0 is the selector.
 Y is the output line.
 E is the Enable line. When the value of E = 0, then the circuit will not work.
 The Truth table for 2X1 MUX will be as shown below.

E S Y

0 X 0
1 0 I0
1 1 I1

 The logical expression for the above Truth table is

Y = E . 𝐒̅ . I0 + E . S . I1

Implementation of 2X1 MUX:

We can implement the 2X1 MUX using two AND gates & one OR gate as shown below.

4X1 MUX:
 In these multiplexers, there will be 4 input lines & one output line.
 The number of selectors will be log24 = 2.
 The design will be as shown below.

Digital Logic Design – Sudheer Kumar

 In the above diagram, I0,I1,I2 and I3 are the four input lines.
 S0, S1 are the selectors. 48
 Y is the output line.
 E is the Enable line. When the value of E = 0, then the circuit will not work.
 The Truth table for 4X1 MUX will be as shown below.

 The logical expression for the above Truth table is

Y = E . 𝐒̅ 1 . 𝐒̅ 0 . I0 + E . 𝐒̅ 1 . S0 . I1 + E . S1 . 𝐒̅ 0 . I2 + E . S1 . S0 . I3

Implementation of 4X1 MUX:

 We can implement the 4X1 MUX using four AND gates & one OR gate as shown below.

Disadvantages of Multiplexers:
 Added delays in switching ports.
 Added delays in I/O signals propagating through the multiplexer.
 Limitations on which ports can be used simultaneously.
 Added firmware complexity to handle switching ports.
 Extra I/O ports required to control the multiplexer.

Digital Logic Design – Sudheer Kumar

06. Write about Demultiplexers.
49
Demultiplexers:
 Demultiplexer (or DEMUX) is a device taking a single input signal and selecting one of many data-output-lines, which
is connected to the single input.
 Demultiplexers are also called as data distributors.
 Demultiplexers take one data input and a number of selection inputs, and they have several outputs.
 They forward the data input to one of the outputs depending on the values of the selection inputs.
 Demultiplexers are sometimes convenient for designing general purpose logic, because if the demultiplexer's input is
always true, the demultiplexer acts as a decoder.
 In 1x2 DEMUX, If I is the input and S is the selector, and A and B are the outputs:
A = I . s̅
B=I.s
The schematic diagram to represent demultiplexers will be as shown below.

 In the above demultiplexer, I is the Input & S0, S1 are the selectors. Y0, Y1, Y2, Y3 are the output lines.

Types of Demultiplexers:
 There are many types of demultiplexers based on the number of output lines.
Ex: 1X2 DEMUX, 1X4 DEMUX, 1X8 DEMUX, 1X16 DEMUX, 1X32 DEMUX etc.
 The relation between the number of output lines & the number of selectors will be as shown below.
m = log2n
Here ‘n’ is number of output lines & ‘m’ is number of selectors.
 In a 1X2 DEMUX, we need 1 selector. [log22 = 1]
4
 In a 1X4 DEMUX, we need 2 selectors. [log2 = 2]
 In a 1X8 DEMUX, we need 3 selectors. [log28 = 3]
 In a 1X16 DEMUX, we need 4 selectors. [log216= 4]
 In a 1X32 DEMUX, we need 5 selectors. [log232= 5]

1X2 DEMUX:
 In these demultiplexers, there will be 1 input line & two output lines.
 The number of selectors will be log22 = 1.
 The design will be as shown below.

Y0
I 1X2
DEMUX Y1

E S0

Digital Logic Design – Sudheer Kumar

 In the above diagram, I is the input line.
 S0 is the selector. 50
 Y0 and Y1 are the output lines.
 E is the Enable line. When the value of E = 0, then the circuit will not work.
 The Truth table for 1X2 DEMUX will be as shown below.

 The logical expression for the above Truth table is

Y0 = E . 𝐒̅0. I
Y 1 = E . s0 . I

Implementation of 1X2 DEMUX:

We can implement the 1X2 DEMUX using two AND gates as shown below.

1X4 DEMUX:
 In these demultiplexers, there will be 1 input line & four output lines.
 The number of selectors will be log24 = 2.
 The design will be as shown below.

Y0
I 1X4 Y1
DEMUX Y2
Y3

E
S1 S0
 In the above diagram, I is the input line.
 S0 and S1 are the selectors.
 Y0,Y1, Y2, and Y3 are the output lines.
 E is the Enable line. When the value of E = 0, then the circuit will not work.
 The Truth table for 1X4 DEMUX will be as shown below.

Digital Logic Design – Sudheer Kumar

 51

 The logical expression for the above Truth table is

Y0 = E . 𝐒̅0 . 𝐒̅1 .I
Y1 = E . 𝐒̅0 . 𝐒1 .I
Y2 = E . S0 . 𝐒̅1 .I
Y3 = E . 𝐒0 . 𝐒1 .I

Implementation of 1X4 DEMUX:

 We can implement the 1X4 DEMUX using four AND gates as shown below.

Digital Logic Design – Sudheer Kumar

07. How to implement Boolean functions (realization of Boolean functions) using 52
decoders?

Boolean functions (or) Combinational Circuits implementation using Decoders:

- Since decoders produce 2n minterms of n-input variables, an external OR gates can be used to form a logical function
in SOP form.
- To implement a given function with decoder and external gates:
 express the function as canonical SOP.
 select decoder that has number of inputs equal to the number of input variables in the given functions.
 select the proper external gate.

- Example: Implement full adder circuit whose outputs are given as:
S(x,y,z) = Σ(1, 2, 4, 7) & C(x,y,z) = Σ(3, 5, 6, 7) With a suitable decoder and external gates.

- If the number of minterms > 2n /2 then express function as F’ and use NOR gate in the external gate to obtain the
function F.

- Example: Implement following Boolean function using decoder:

S(x,y,z) = Σ(0, 2, 4, 5, 7)
Here, number of minterms = 5 i.e. more than 23/2, so we need to complement the function.
S’(x,y,z) = Σ(1,3,6)
To obtain the function, we use NOR gate as external gate.

Digital Logic Design – Sudheer Kumar

08. How to implement Boolean functions (realization of Boolean functions) using
multiplexers? 53

Implement Boolean functions using Multiplexers:

 Implementing logical functions is a basic part of designing digital logic.

 The sum-of-products (SOP) form, which defines a logical function as the sum of various product terms, is one
common representation.
 Multiplexers can be used to effectively implement SOP functions.
 A Boolean expression known as a sum-of-products (SOP) function represents a logical function as the addition
(OR) of many product terms. The literals in each product word are either variables or their opposites. The
canonical form or the minterm form are other names for the SOP form.
 Here is an example of a SOP function with three A, B, and C input variables −
F(A, B, C) = Σ(0, 2, 5, 6)

Four product terms—m0, m2, m5, and m6—are represented by the logical OR of the function F in this instance.
Each minterm (m) represents a particular set of values for the input variables where the function evaluates to 1.

The example's minterms are represented in binary as follows −

 m0 − 000 (corresponds to the decimal value 0)

 m2 − 010 (corresponds to the decimal value 2)
 m5 − 101 (corresponds to the decimal value 5)
 m6 − 110 (corresponds to the decimal value 6)

Logic gates or a multiplexer can be used to accomplish the SOP function.

There are certain steps involved in it:

Step 1: Draw the truth table for the given number of variable function.

Step 2: Consider one variable as input and remaining variables as select lines.

Step 3: Form a matrix where input lines of MUX are columns and input variable and its complement are rows.

Step 4: Find AND between both rows on the basis of the truth table.

Step 5: Hence whatever is found is considered as input of MUX.

We will illustrate it with an example:

Example: Given SOP function f(A, B, C) = m(0, 1, 4, 6, 7) and MUX is

Digital Logic Design – Sudheer Kumar

For 3 variable function, the truth table is
54

Let A and B are the select lines and C be the input,

Thus, for the implementation of given logical function, required is one 4×1 MUX and inverter.

From the derived input, 4x1 MUX can be drawn as follows:

Digital Logic Design – Sudheer Kumar

 Unit 5 : Sequential Logic Circuits
55
01. Write about Classification of Sequential circuits.

Classification of Sequential circuits:

 The sequential circuits can be event driven, clock driven and pulse driven. There are two main types of
sequential circuits: (a) Synchronous and (b) Asynchronous.

Asynchronous Sequential circuits :

 Asynchronous circuits do not synchronize with positive edge or negative edge of the clock signal, that means,
the outputs of asynchronous sequential circuits do not change or affect at the same time and change their
state immediately when there is a change in the input signal.
 So, these circuits are faster and independent of the internal clock pulses. But these circuits have uncertainty
in the outputs and are difficult to design.

Synchronous Sequential circuits :

 Synchronous circuits synchronize with either positive edge or negative edge of the clock signal, that means,
the outputs of synchronous sequential circuits change or affect at the same time.
 These circuits use clock signal and level input (or pulsed with restrictions on pulse width and circuit
propagation).
 Since they wait for the next clock pulse to arrive to perform the next operation, so these circuits are a bit
slower compared to asynchronous.
 Level output changes state at the start of an input pulse and remains in that until the next input or clock
pulse.
 The synchronous sequential circuit can be locked or unlocked (or pulsed).

 Counters & flip-flops are examples of synchronous sequential circuits.

Digital Logic Design – Sudheer Kumar

 Difference between Synchronous and Asynchronous Sequential Circuits
56
The following table highlights all the important differences between Synchronous and Asynchronous Sequential
Circuits −

Key Synchronous Sequential Asynchronous Sequential Circuits

Circuits

Synchronous sequential circuits Asynchronous sequential circuits are digital

are digital sequential circuits in sequential circuits in which the feedback to the input
Definition which the feedback to the input for next output generation is not governed by clock
for next output generation is signals.
governed by clock signals.

In Synchronous sequential Unclocked flip flop or time delay is used as memory

Memory circuits, the memory unit which element in case of Asynchronous sequential circuits.
Unit is being get used for governance
is clocked flip flop.

The states of Synchronous There are chances for the Asynchronous circuits to
sequential circuits are always enter into a wrong state because of the time
State
predictable and thus reliable. difference between the arrivals of inputs. This is
called "race condition".

It is easy to design Synchronous The presence of feedback among logic gates causes
Complexity sequential circuits instability issues making the design of Asynchronous
sequential circuits difficult.

Due to the propagation delay of Since there is no clock signal delay, these are fast
clock signal in reaching all compared to the Synchronous Sequential Circuits
Performance elements of the circuit the
Synchronous sequential circuits
are slower in its operation speed

Synchronous circuits are used Asynchronous circuits are used in low power and
in counters, shift high speed operations such as
Example registers, memory units. simple microprocessors, digital signal
processing units and in communication systems for
email applications, internet access and networking.

02. Explain : Latches & Flip-flops.

Latches & Flip-flops:

 Latches and flip-flops are the basic elements for storing information.
 One latch or flip-flop can store one bit of information.
 The main difference between latches and flip-flops is that for latches, their outputs are constantly affected by their
inputs as long as the enable signal is asserted. In other words, when they are enabled, their content changes
immediately when their inputs change.
 Flip-flops have their content change only either at the rising or falling edge of the enable signal. This enable signal is
usually the controlling clock signal.
 After the rising or falling edge of the clock, the flip-flop content remains constant even if the input changes.
 There are basically four main types of latches and flip-flops: SR, D, JK, and T.
 The major differences in these flip-flop types are the number of inputs they have and how they change state. For
each type, there are also different variations that enhance their operations.

Digital Logic Design – Sudheer Kumar

 Flip-Flop : 57
 Flip-flop is a basic digital memory circuit, which stores one bit of information.
 Flip flops are the fundamental blocks of most sequential circuits.
 It is also known as a bistable multivibrator or a binary or one-bit memory.
 Flip-flops are used as memory elements in sequential circuit.
 The output is obtained in a sequential circuit from combinational circuit or flip-flop or both.
 The state of flip-flop changes at active state of clock pulses and remains unaffected when the clock pulse is not
active.
 In particular, clocked flip flops serve as memory elements in synchronous sequential Circuits and
unclocked flip-flops (i.e., latches) serve as memory elements in asynchronous sequential circuits.

Latch :

 Latch is an electronic device, which changes its output immediately based on the applied input.
 Flip flops are the fundamental blocks of most sequential circuits.
 It is used to store either 1 or 0 at any specified time. It consists of two inputs namely “ SET” and RESET and
two outputs, which are complement to each other.

Differences between Flip-flop and Latch:

S.No Flip-flop Latch

Flip-flop is a bistable device i.e., it has two stable Latch is also a bistable device whose
1 states that are represented as 0 and 1. states are also represented as 0 and 1.

It checks the inputs but changes the output only at It checks the inputs continuously and
times defined by the clock signal or any other responds to the changes in inputs
2 control signal. immediately.

3 It is a edge triggered device. It is a level triggered device.

4 Flip-flop always have a clock signal. Latches doesn’t have a clock signal

They are classified into asynchronous or

5 synchronous flipflops. There is no such classification in latches.

6 Flip-flop can be build from Latches. Latches can be build from gates.

7 Ex: D Flip-flop, JK Flip-flop Ex: SR Latch, D Latch

Digital Logic Design – Sudheer Kumar

03. Implementing SR Latch using NAND & NOR gates.
58
SR Latch using NAND gates:
The SR latch is a sequential circuit that is used in digital logic and electronics. The SR latch has two stable states
and can store a single bit of information; the two stable states are known as set and reset, hence the name SR.
The latch also provides two outputs, namely Q and Q-bar (the inverse of Q).

The circuit diagram

Below, we can see the circuit diagram for the SR latch.

As we see in the diagram, the SR latch comprises two cross-coupled NAND gates, where the output of one gate is
connected to the input of the other and vice versa. The latch takes two binary inputs, S and R, and produces two
binary outputs, Q and Q-bar.

Formation of the truth table

Now that we have looked at the circuit diagram for the SR latch, we will now look at how the truth table is formed
by looking at the different input values of S and R.

Case 1: When S = 1 and R = 0 (SET)

So the Q values will be 1, and the value of Q-bar will be 0 showing that we set the value of the output Q as 1.

Case 2: When S = 0 and R = 1 (RESET)

So the Q value will be 0, and Q-bar would be 1 showing that we have reset the output bit Q.
Digital Logic Design – Sudheer Kumar
Case 3: When S = 0 and R = 0 (INVALID) 59

In this case, we can see that one of the inputs to both NAND gates is 0; this means that the output of both gates
will always be 1 regardless of the 2nd input to the NAND gates. Since the value of Q and Q-bar is the same, we
call this SR latch state invalid.

Case 4: When S = 1 and R = 1 (HOLD)

This case is a bit tricky to solve as none of the inputs is 0, which means that the output depends on the 2nd input
to the NAND gates. We will try to solve this using Boolean algebra, as seen in the diagram. We see that there will
be no change in already stored bits for Q and Q’ upon solving the equation; hence we call this state the hold state
since none of the values of the output change.

Truth table

Now that we have gone through all the different states of an SR latch, we can see the final truth table below that
shows the values of Q and Q-bar against the input bits S and R.

Digital Logic Design – Sudheer Kumar

 SR Latch using NOR gates:
60
This circuit consists of :
- 2 cross coupled NOR gates
- 2 inputs (S for Set & R for Reset)
- 2 outputs (Q & Q’)

The SR latch using NOR gates is shown below:

Truth table for NOR gate latch:

 While the S and R inputs are both low, the SR latch maintains the Q and Q’ outputs in a constant state.
 If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high until S
returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low until
R returns to low.
 The R = S = 1 combination is called invalid state because, as both NOR gates produce output zeros, it breaks the
logical equation as Q can’t be equal to Q’.

Timing diagram of NOR gate latch:

Digital Logic Design – Sudheer Kumar

04. Types of flip-flops (RS, JK, T and D flip-flops).
61
What are Flip-Flops?

The flip-flops are basically the circuits that maintain a certain state unless and until directed by the input for
changing that state. We can construct a basic flip-flop using four-NOR and four-NAND gates.

Types of Flip-Flops
The flip-flops are of the following types:

1. S-R Flip Flop 2. J-K Flip Flop 3. T Flip Flop 4. D Flip Flop

S-R Flip Flop

This flip-flop circuit has a set input (S) and a reset input (R). In this circuit, when you Set “S” as active, the output
Q would be high, and Q‘ would be low. When you reset “R” as active, the output Q would be low, and Q’ would be
high.

K-map for above truth table:

Characteristic Equation : Q(N+1) = S + R’Q(N)

Digital Logic Design – Sudheer Kumar

J-K Flip Flop
62
Due to the undefined state in the SR flip-flops, another flip-flop is required in electronics. The JK flip-flop is an
improvement on the SR flip-flop where S=R=1 is not a problem. When J=1 & K=1 the output will be toggle of the
previous state.

K-map for above truth table:

Characteristic Equation: Q(N+1) = J Q’(N) + K’ Q(N)

T Flip Flop

A T flip-flop or Toggle flip-flop is like a JK flip-flop. These are basically single-input versions of JK flip-flops. This
modified form of the JK is obtained by connecting inputs J and K together. It has only one input along with the
clock input.

K-map for above truth table:

Characteristic Equation : Q(N+1) = T’ Q(N) + Q’(N) T

Digital Logic Design – Sudheer Kumar

 D Flip Flop
63
D Flip flops or data flip flops or delay flip flops can be designed using SR flip flops by connecting a not gate in
between S and R inputs. D flip flops can be used in place of SR flip flops where you need only SET and RESET
state.

K-map for above truth table:

Characteristic Equation : Q(N+1) = D

05. Conversion of flip-flops.

Conversion of Flip-Flops:

We can convert one flip-flop into the remaining three flip-flops by including some additional logic. So, there will be
total of twelve flip-flop conversions.

Follow these steps for converting one flip-flop to the other.

 Consider the characteristic table of desired flip-flop.
 Fill the excitation values inputs of given flip-flop for each combination of present state and next state.
The excitation table for all flip-flops is shown below.

Present Next SR flip-flop D flip-flop JK flip-flop T flip-flop

State State inputs input inputs input

Qt Qt+1 S R D J K T

0 0 0 x 0 0 x 0

0 1 1 0 1 1 x 1

1 0 0 1 0 x 1 1

1 1 x 0 1 x 0 0

 Get the simplified expressions for each excitation input. If necessary, use K-maps for simplifying.
 Draw the circuit diagram of desired flip-flop according to the simplified expressions using given flip-flop
and necessary logic gates.
 For example, SR flip flop to D flip flop conversion is given below:

Digital Logic Design – Sudheer Kumar

i) Conversion of SR to D Flip-Flop:
64
Here, the given flip-flop is SR flip-flop and the desired flip-flop is D flip-flop. Therefore, consider the
following characteristic table of D flip-flop.

D flip-flop input Present State Next State

D Qt Qt+1

0 0 0

0 1 0

1 0 1

1 1 1

We know that SR flip-flop has two inputs S & R. So, write down the excitation values of SR flip-flop for each
combination of present state and next state values. The following table shows the characteristic table of D flip-flop
along with the excitation inputs of SR flip-flop.

D flip-flop input Present State Next State SR flip-flop inputs

D Qt Qt+1 S R

0 0 0 0 x

0 1 0 0 1

1 0 1 1 0

1 1 1 x 0

From the above table, we can write the Boolean functions for each input as below.

S=m2+d3

R=m1+d0

We can use 2 variable K-Maps for getting simplified expressions for these inputs. The k-Maps for S & R are shown
below.

So, we got S = D & R = D' after simplifying. The circuit diagram of D flip-flop is shown in the following figure.

Digital Logic Design – Sudheer Kumar

 65

This circuit consists of SR flip-flop and an inverter. This inverter produces an output, which is complement of input,
D. So, the overall circuit has single input, D and two outputs Qt & Qt'. Hence, it is a D flip-flop. Similarly, you can
do other two conversions.

06. Explain about flip-flops with asynchronous inputs (preset and clear).

Asynchronous Flip-Flop Inputs

The normal data inputs to a flip flop (D, SR, or JK) are referred to as synchronous inputs because they have an
effect on the outputs (Q and Q’) only in sync, with the clock signal transitions.

The extra inputs shown below are called asynchronous because they can set or reset the flip-flop regardless of
the status of the clock signal. Typically, they’re called preset and clear:

When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of any of the synchronous
inputs or the clock. When the clear input is activated, the flip-flop will be reset (Q=0, not-Q=1), regardless of any
of the synchronous inputs or the clock.

So, what happens if both preset and clear inputs are activated? Surprise, surprise: we get an invalid state on the
output, where Q and not-Q go to the same state, the same as our old friend, the S-R latch! Preset and clear inputs
find use when multiple flip-flops are ganged together to perform a function on a multi-bit binary word, and a single
line is needed to set or reset them all at once.

Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high or active-low. If they’re
active-low, there will be an inverting bubble at that input lead on the block symbol, just like the negative edge-
trigger clock inputs.

Digital Logic Design – Sudheer Kumar

 66

Sometimes the designations “PRE” and “CLR” will be shown with inversion bars above them, to further denote the
negative logic of these inputs:

REVIEW:

 Asynchronous inputs on a flip-flop have control over the outputs (Q and not-Q) regardless of clock input
status.
 These inputs are called the preset (PRE) and clear (CLR). The preset input drives the flip-flop to a set state
while the clear input drives it to a reset state.
 It is possible to drive the outputs of a J-K flip-flop to an invalid condition using the asynchronous inputs,
because all feedback within the multivibrator circuit is overridden.

07. Explain: Shift registers, Bi-directional shift registers, Universal shift registers.

Registers:
 In order to store multiple bits of data, we need multiple flip-flops. N flip flops are to be connected in order to
store N bits of data.
 A Register is a device that is used to store such information. It is a group of flip-flops connected in series used
to store multiple bits of data. The information stored within these registers can be transferred with the help
of shift registers.
 The bits stored in shift registers can be made to move within the registers and in/out of the registers by
applying clock pulses.
 An n-bit shift register can be formed by connecting n flip-flops where each flip-flop stores a single bit of data.
The registers which will shift the bits to the left are called “Shift left registers”. The registers which will shift
the bits to the right are called “Shift right registers”.
 Shift registers are basically of following types.

 Serial In Serial Out shift register

 Serial In parallel Out shift register
 Parallel In Serial Out shift register
 Parallel In parallel Out shift register
 Bidirectional Shift Register
 Universal Shift Register
 Shift Register Counter

Digital Logic Design – Sudheer Kumar

 Structure of a Bidirectional Shift Register
 A bidirectional shift register is a sequential circuit that can shift data both leftwards and rightwards. 67
 It consists of a series of flip-flops connected in a chain, allowing the data to be shifted in either direction.
 The number of flip-flops used determines the size of the shift register and its data storage capacity.

Bidirectional Shift Register Circuit Diagram

 A bidirectional shift register is a versatile circuit used for shifting data either to the right or left based on an
input signal.
 It can be implemented using D flip-flops and logic gates, enabling the transfer of data from one stage to the
next stage in the desired direction determined by a mode control signal.
 This flexible functionality makes bidirectional shift registers an essential component in various digital systems.

Universal Shift Registers:

 Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode
(either serial or parallel) by shifting it either towards right or towards left.
 In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO,
PISO, PIPO) and bidirectional shift register along with parallel load provision is referred to as universal shift
register.
 Such a shift register capable of storing 4 input bits is shown below:

Digital Logic Design – Sudheer Kumar

08. Design of ripple counters.
68
What is a Counter?
Counter is basically used to count the number of clock pulses applied to a flip-flop. It can also be used for
Frequency divider, time measurement, frequency measurement, distance measurement, and also for generating
square waveforms. In this, the flip-flops are asynchronous counters and are supplied with different clock
signals, there may be a delay in producing output. Also, a few numbers of logic gates are needed to design
asynchronous counters. So they are elementary in design and also are less expensive.

What is a Ripple counter?

Ripple counter is a cascaded arrangement of flip-flops where the output of one flip-flop drives the clock input of
the following flip-flop. The number of flip flops in the cascaded arrangement depends upon the number of
different logic states that it goes through before it repeats the sequence a parameter known as the modulus of
the counter. A n-bit ripple counter can count up to 2n states. It is also known as MOD n counter. It is known as
ripple counter because of the way the clock pulse ripples its way through the flip-flops. Some of the features of
ripple counter are:

 It is an asynchronous counter.
 Different flip-flops are used with a different clock pulse.
 All the flip-flops are used in toggle mode.
 Only one flip-flop is applied with an external clock pulse and another flip-flop clock is obtained from the
output of the previous flip-flop.
 The flip-flop applied with an external clock pulse act as LSB (Least Significant Bit) in the counting
sequence.

A counter may be an up counter that counts upwards or can be a down counter that counts downwards or can
do both i.e. Count up as well as count downwards depending on the input control.
The sequence of counting usually gets repeated after a limit.
When counting up, for the n-bit counter the count sequence goes from 000, 001, 010, … 110, 111, 000, 001, …
etc. When counting down the count sequence goes in the opposite manner: 111, 110, … 010, 001, 000, 111,
110, … etc.

A 3-bit Ripple counter using a JK flip-flop is as follows:

In the circuit shown in the above figure, Q0(LSB) will toggle for every clock pulse because JK flip-flop works in
toggle mode when both J and K are applied 1, 1, or high input. The following counter will toggle when the
previous one changes from 1 to 0.
Truth Table is as follows:

The 3-bit ripple counter used in the circuit above has eight different states, each one of which represents a
count value. Similarly, a counter having n flip-flops can have a maximum of 2 to the power n states.

Digital Logic Design – Sudheer Kumar

Timing diagram 69
Let us assume that the clock is negative edge triggered so the above the counter will act as an up counter
because the clock is negative edge triggered and output is taken from Q.

Counters are used very frequently to divide clock frequencies and their uses mainly involve digital clocks and in
multiplexing.

09. Explain: Synchronous counters and Variable modulus counters.

Synchronous counters:

Synchronous generally refers to something which is coordinated with others based on time. Synchronous signals
occur at same clock rate and all the clocks follow the same reference clock.
In synchronous counter, the clock input across all the flip-flops use the same source and create the same clock
signal at the same time. So, a counter which is using the same clock signal from the same source at the same
time is called Synchronous counter.

Synchronous Up Counter

In the above image, the basic Synchronous counter design is shown which is Synchronous up counter. A 4-bit
Synchronous up counter start to count from 0 (0000 in binary) and increment or count upwards to 15 (1111 in
binary) and then start new counting cycle by getting reset. Its operating frequency is much higher than the same
range Asynchronous counter. Also, there is no propagation delay in the synchronous counter just because all
flip-flops or counter stage is in parallel clock source and the clock triggers all counters at the same time.

The external clock is directly provided to all J-K Flip-flops at the same time in a parallel way. If we see the
circuit, the first flip-flop, FFA which is the least significant bit in this 4-bit synchronous counter, is connected to a
Logic 1 external input via J and K pin. Due to this connection, HIGH logic across the Logic 1 signal, change the
state of first flip-flop on every clock pulse.

Next stage, the second flip-flop FFB, input pin of J and K is connected across the output of the first Flip-flop. For
the case of FFC and FFD, two separate AND gate provide the necessary logic across them. Those AND gates create
logic using the input and output from the previous stage flip-flops.

Digital Logic Design – Sudheer Kumar

We can create the same counting sequence used in the Asynchronous counter by making a situation where each
flip-flops change its state depending on whether or not all preceding flip-flops output is HIGH in logic. But in this 70
scenario, there will be no ripple effect just because all flip-flops are clocked at the same time.

Synchronous Down Counter

Slight changes in AND section, and using the inverted output from J-K flip-flop, we can create Synchronous
Down Counter. A 4-bit Synchronous down counter start to count from 15 (1111 in binary) and decrement or
count downwards to 0 or 0000 and after that it will start a new counting cycle by getting reset. In synchronous
down counter, the AND Gate input is changed. First Flip-flop FFA input is same as we used in previous
Synchronous up counter. Instead of directly feeding the output of the first flip-flop to the next subsequent flip-flop,
we are using inverted output pin which is used to give J and K input across next flip-flop FFB and also used as
input pin across the AND gate. Same as like the previous circuit, two AND gates are providing necessary logic to
the next two Flip-flops FFC and FFD.

Variable Modulus counters:

A variable modulus counter is a counter that will count to a predetermined number and then reset itself to start a
new count. A conventional binary or BCD (binary coded decimal) counter may be connected to perform variable
modulus counting in a number of ways. One way is to gate the output so that the count following the highest
number of the sequence resets the counter to zero.

Modulus Counters, or simply MOD counters, are defined based on the number of states that the counter will
sequence through before returning back to its original value. For example, a 2-bit counter that counts from 002 to
112 in binary, that is 0 to 3 in decimal, has a modulus value of 4 ( 00 → 01 → 10 → 11, and return back to 00 ) so
would therefore be called a modulo-4, or mod-4, counter. Note also that it has taken four clock pulses to get from
00 to 11.

As in this simple example there are only two bits, ( n = 2 ) then the maximum number of possible output states
(maximum modulus) for the counter is: 2n = 22 or 4. However, counters can be designed to count to any number
of 2n states in their sequence by cascading together multiple counting stages to produce a single modulus or MOD-
N counter.

Therefore, a “Mod-N” counter will require “N” number of flip-flops connected together to count a single data bit
while providing 2n different output states, (n is the number of bits). Note that N is always a whole integer value.

The we can see that MOD counters have a modulus value that is an integral power of 2, that is, 2, 4, 8, 16 and so
on to produce an n-bit counter depending on the number of flip-flops used, and how they are connected,
determining the type and modulus of the counter.
MOD-4 Counter

Technically as well as being a 1-bit storage device, a single flip-flop on its own could be thought of as a MOD-2
counter, as it has a single output resulting in a count of two, either a 0 or 1, on the application of the clock signal.
But a single flip-flop on its own produces a limited counting sequence, so by connecting together more flip-flops to
form a chain, we can increase the counting capacity and construct a MOD counter of any value.

If a single flip-flop can be considered as a modulo-2 or MOD-2 counter, then adding a second flip-flop would give
us a MOD-4 counter allowing it to count in four discrete steps. The overall effect would be to divide the original
clock input signal by four. Then the binary sequence for this 2-bit MOD-4 counter would be: 00, 01, 10, and 11 as
shown.
Digital Logic Design – Sudheer Kumar
MOD-4 Counter and Timing Diagram
71

Note that for simplicity, the switching transitions of QA, QB and CLK in the above timing diagram are shown to be
simultaneous even though this connection represents an asynchronous counter. In reality there would be a very
small switching delay between the application of the positive going clock (CLK) signal, and the outputs at QA and
QB.

We can show visually the operation of this 2-bit asynchronous counter using a truth table and state diagram.

MOD-4 Counter State Diagram

Present
Next State State Diagram
State
Clock Pulse

QB QA QB QA

0 (start) 0 0 ⇒ 0 1

1 0 1 ⇒ 1 0

2 1 0 ⇒ 1 1

3 1 1 ⇒ 0 0

4 (repeat) 0 0 ⇒ 0 1

We can see from the truth table of the counter, and by reading the values of QA and QB, when QA = 0 and QB =
0, the count is 00. After the application of the clock pulse, the values become QA = 1, QB = 0, giving a count of
01. After the arrival of the next clock pulse, the values change and become QA = 0, QB = 1, giving a count of 10.
Finally the values become QA = 1, QB = 1, giving a count of 11. The application of the next clock pulse causes the
count to return back to 00, and thereafter it counts continuously up in a binary sequence of: 00, 01, 10, 11, 00,
01 … etc.

Then we have seen that a MOD-2 counter consists of a single flip-flop and a MOD-4 counter requires two flip-flops,
allowing it to count in four discrete steps. We could easily add another flip-flop onto the end of a MOD-4 counter to
produce a MOD-8 counter giving us a 23 binary sequence of counting from 000 up to 111, before resetting back to
000. A fourth flip-flop would make a MOD-16 counter and so on, in fact we could go on adding extra flip-flops for
as long as we wanted.
Digital Logic Design – Sudheer Kumar
 72
B.Sc (Honours) Computer Science
(Examination at the end of Second Semester)
Digital Logic Design
(Regulation : 2023-24) – Model paper 1

Time : Three hours Maximum : 70 marks

SECTION A – (5 x 4 = 20 marks)
Answer any FIVE of the following questions.

1. Explain r’s & (r-1)’s complement.

2. Weighted and Non-Weighted Binary codes.
3. Write about Boolean Laws.
4. Explain don’t care conditions in K-Maps.
5. Explain Ripple Adders.
6. Priority Encoders.
7. Higher order decoders.
8. Differences between Latches & Flip-flops.

SECTION B – (5 x 10 = 50 marks)
Answer following questions.

UNIT 1 UNIT IV

09. a) Write about octal number system. 12. a) Write about Multiplexers.
(or) (or)
b) Explain addition & subtraction of unsigned & b) How to implement Boolean functions using
signed binary numbers. decoders?

UNIT II UNIT V

10. a) Explain : Dual & Complement of a 13. a) Write about Classification of Sequential
Logic function. circuits.
(or) (or)
b) Explain Two level realization of Logic b) Explain: Shift registers, Bi-directional shift
functions. registers, Universal shift register.

UNIT III

11. a) Explain designing half adder & full adder.

(or)
b) Explain Ripple Adders and Subtractors.

Digital Logic Design – Sudheer Kumar