BEETECH FEB2025
Binary representation of data and numbers, Integer Representation, Data storage units
bits, bytes, kilobytes, etc., ASCII and Unicode, CPU Architecture and Instruction Set:
Basic CPU architecture ALU, registers, control unit, Instruction format and assembly
language (basics only) Fetch- execute cycle and instruction execution.
Introduction to the subject :- https://youtu.be/Ae63V43DLv8
Part 1:-https://youtu.be/8HFNfiQ__w4
Part 2:-https://youtu.be/34c_cqEy86M
Part 3:-
N
IO
AT
C
U
ED
E
IV
Binary Representation of Data and Numbers
H
What is Binary?
EE
● Binary is a number system with a base of 2.
● It uses only two digits: 0 and 1.
● It is the foundation of all computer operations because computers use
B
transistors that have two states: ON (1) and OFF (0).
Why Do Computers Use Binary (Base 2)?
1. Simplicity in Hardware Design
1
BEETECH FEB2025
● Transistors: The core components of digital circuits operate in two
states:
○ ON: High voltage, represented by 1.
○ OFF: Low voltage, represented by 0.
● Designing circuits with two states is much simpler than handling
multiple states (like decimal systems with 10 states).
2. Reliability
N
● Error Reduction:
IO
○ Binary signals are less prone to distortion compared to analog
signals or systems with multiple states.
AT
○ Example: A signal can either be high (1) or low (0), making it
easier to detect and correct errors.
● Noise Immunity: Binary systems are more resistant to electrical
C
noise because small fluctuations in voltage won't affect the
U
interpretation of 0 or 1.
ED
3. Cost-Effectiveness and Scalability
● Circuit Design:
○ Digital circuits (e.g., logic gates like AND, OR, NOT) are built
E
using simple binary operations.
○ Reduces manufacturing complexity and cost.
IV
● Memory and Storage: Binary representation allows efficient use of
memory, with each bit (binary digit) representing a single state.
H
EE
4. Universality
● Binary is the universal language of computers, enabling
standardization across all digital devices.
B
2
BEETECH FEB2025
N
IO
AT
C
U
ED
Representation of Negative Integers
E
IV
H
EE
B
3
BEETECH FEB2025
N
IO
AT
C
U
ED
2. Data Storage Units
E
IV
H
EE
B
b. Practical Examples:
4
BEETECH FEB2025
Binary Representation in Data Storage
N
● Text: Characters are encoded as binary numbers using standards
IO
like ASCII or Unicode.
Example:
AT
○ A=01000001 in binary (ASCII).
● Images: Stored as a grid of pixels, each represented in binary (e.g.,
grayscale uses 8 bits per pixel).
C
● Audio: Sampled and quantized into binary values during
U
analog-to-digital conversion.
ED
ASCII (American Standard Code for Information Interchange)
What is ASCII?
● A 7-bit encoding standard for representing characters.
E
● Encodes 128 characters, including:
IV
○ Uppercase letters (A-Z).
○ Lowercase letters (a-z).
H
○ Numbers (0-9).
○ Symbols (*, %, @).
EE
Representation of Characters:
B
● Example:
○ A=65, B=66.
○ a=97, b=98.
○ Space = 32.
c. Limitations of ASCII:
5
BEETECH FEB2025
● Limited to 128 characters.
● Cannot represent non-English characters or symbols (e.g., €, ₹, or
Chinese characters).
Unicode
How Unicode Solves ASCII Limitations
N
● Provides a universal encoding system for all languages and symbols.
● Supports over 1.1 million characters.
IO
UTF-8, UTF-16, and UTF-32:
AT
● UTF-8: Variable-length encoding (1-4 bytes). Compatible with ASCII.
Most common.
● UTF-16: Uses 2-4 bytes per character.
C
● UTF-32: Uses 4 bytes per character (fixed).
U
Importance in Multilingual Systems:
ED
● Enables the representation of languages like Hindi, Chinese, Arabic,
etc.
● Essential for web applications, text processing, and global software.
E
IV
H
EE
B
6
BEETECH FEB2025
N
IO
AT
C
U
ED
E
IV
H
EE
B
7
BEETECH FEB2025
N
IO
AT
C
U
ED
E
IV
H
EE
B
8
BEETECH FEB2025
N
IO
AT
C
U
ED
E
IV
H
EE
B
9
BEETECH FEB2025
N
IO
AT
C
U
ED
E
IV
H
EE
B
10
BEETECH FEB2025
N
IO
AT
C
U
ED
CPU Architecture and Instruction Set
1. Introduction to CPU Architecture
E
IV
The Central Processing Unit (CPU) is the brain of a computer. It executes
instructions, processes data, and controls hardware operations. A CPU
consists of three main components:
H
EE
1. Arithmetic and Logic Unit (ALU)
2. Control Unit (CU)
3. Registers
B
11
BEETECH FEB2025
A simple diagram of CPU architecture:
N
IO
AT
C
2. Main Components of a CPU
U
ED
a) Arithmetic and Logic Unit (ALU)
● Performs all mathematical operations (addition, subtraction,
multiplication, division).
E
● Performs logical operations (AND, OR, NOT, XOR) used in
IV
decision-making.
● Acts as the calculator of the CPU.
H
b) Registers
EE
Registers are small, high-speed memory units inside the CPU that
temporarily store data and instructions. Types of registers include:
B
● Accumulator (ACC): Stores intermediate results of arithmetic and
logic operations.
● Program Counter (PC): Holds the address of the next instruction to
be executed.
● Instruction Register (IR): Stores the currently executing instruction.
● Stack Pointer (SP): Points to the top of the stack in memory.
12
BEETECH FEB2025
c) Control Unit (CU)
● Fetches, decodes, and executes instructions.
● Directs the flow of data between memory, ALU, and input/output
devices.
● Uses a clock signal to synchronize operations.
Instruction Set Architecture (ISA)
N
The Instruction Set is a collection of machine-level commands that a CPU
IO
understands. Each CPU family (Intel, ARM, etc.) has its own ISA.
Types of Instructions
AT
1. Data Transfer Instructions
○ MOV (Move data)
C
○ LOAD (Load data from memory)
U
○ STORE (Store data in memory)
2. Arithmetic Instructions
ED
○ ADD (Addition)
○ SUB (Subtraction)
○ MUL (Multiplication)
○ DIV (Division)
E
3. Logical Instructions
IV
○ AND (Bitwise AND)
○ OR (Bitwise OR)
H
○ XOR (Exclusive OR)
○ NOT (Negation)
EE
4. Control Flow Instructions
○ JMP (Jump to another instruction)
○ CALL (Call a subroutine)
B
○ RET (Return from a subroutine)
5. I/O Instructions
○ IN (Read data from an input device)
○ OUT (Send data to an output device)
13
BEETECH FEB2025
N
IO
AT
There are two main types of ISAs based on instruction complexity:
C
U
ED
E
IV
Instruction Format
H
An instruction in assembly language consists of an operation code
EE
(opcode) and operands. The structure of an instruction can vary
depending on the computer architecture.
B
General Format:
14
BEETECH FEB2025
● Label (optional): Used for marking a location in the program.
● Opcode: The operation to be performed (e.g., MOV, ADD, SUB).
● Operand(s): The data or memory locations involved in the operation.
● Comment (optional): Notes to explain the code (denoted by ; in
most assemblers).
Types of Instruction Formats:
N
1. Zero-Address Instructions (Stack-Based):
IO
○ No operands (e.g., PUSH, POP).
○ Used in stack-based architectures.
2. One-Address Instructions:
AT
○ One operand (e.g., INC AL).
○ Usually operates on an accumulator register.
C
3. Two-Address Instructions:
○ Two operands (e.g., MOV AX, BX).
U
○ First operand is usually the destination, second is the source.
ED
4. Three-Address Instructions:
○ Three operands (e.g., ADD R1, R2, R3).
○ Used in RISC architectures.
E
IV
2. Basics of Assembly Language
H
Assembly language is a low-level programming language specific to a
EE
computer’s architecture. It uses mnemonics (short names) for instructions.
Common Assembly Instructions:
B
15
BEETECH FEB2025
N
IO
AT
C
U
ED
E
3. Registers in Assembly
IV
Registers are small storage locations inside the CPU for fast operations.
H
EE
B
16
BEETECH FEB2025
N
IO
AT
4. Addressing Modes (Ways to Access Data)
C
U
ED
E
IV
5. Assembler, Linker, and Loader
H
EE
● Assembler: Converts assembly code to machine code (e.g., NASM,
MASM, TASM).
● Linker: Combines multiple object files and resolves addresses.
B
● Loader: Loads the program into memory for execution.
17
BEETECH FEB2025
Fetch-Execute Cycle
Every instruction follows a Fetch-Decode-Execute cycle:
1. Fetch – Retrieve the next instruction from memory.
2. Decode – Interpret the instruction.
3. Execute – Carry out the operation.
4. Store (Write Back) – Save the result back to memory or a register.
N
Example: Adding two numbers
IO
1. Fetch: CPU fetches ADD A, B from memory.
AT
2. Decode: CPU identifies this as an addition instruction.
3. Execute: ALU performs A + B, and stores the result in A
C
U
ED
E
IV
H
EE
B
18
BEETECH FEB2025
N
IO
AT
C
U
ED
E
IV
H
Steps in the Fetch-Execute Cycle
EE
Step 1: Fetch the Instruction
B
● The Program Counter (PC) holds the address of the next instruction.
● The instruction is fetched from memory (RAM) and loaded into the
Instruction Register (IR).
● The PC is updated to point to the next instruction.
19
BEETECH FEB2025
📌 Example:
If the instruction at memory address 1000 is ADD A, B, it is fetched into
the Instruction Register (IR).
Step 2: Decode the Instruction
● The Control Unit (CU) decodes the instruction in the IR.
● It identifies the operation (e.g., addition, subtraction, move).
N
● It determines the operands (data on which the operation will be
IO
performed).
📌 Example:
AT
The control unit decodes ADD A, B, identifying it as an addition
operation.
C
Step 3: Execute the Instruction
U
● The Arithmetic and Logic Unit (ALU) or registers execute the
ED
instruction.
● The operation is performed on the specified data.
📌 Example:
E
The ALU adds values in register A and B and stores the result in A.
IV
Step 4: Store the Result (Write Back)
● The result is stored in a register or written back to memory if
H
needed.
EE
● The cycle repeats with the next instruction.
📌 Example:
B
After addition, register A now holds the sum of A and B.
3. Instruction Execution
Each instruction follows this three-step process:
20
BEETECH FEB2025
1. Operand Fetch – Load data if needed.
2. Operation Execution – Perform ALU or control operation.
3. Result Storage – Save the result.
N
IO
AT
C
U
ED
E
IV
H
EE
B
21
