DIGITAL ELECTRONICS

Combinational Logic Circuits

Syllabus:

• Boolean functions & standard canonical forms, simplification using Boolean algebra & K-
map, Minimization of logical expression using K- map (2, 3, 4 variables), POS & SOP.
• Truth Table, K –map, simplified logical expression and logical circuit of Half Adder & Full
Adder, Half Subtractor & Full Subtractor.
• Block diagram and Truth Table of Encoders, priority Encoder ICs and Decoder, Decoder-
Driver.
• Block diagram, Truth Table, working principle, Application, PIN functions of Decimal to BCD
Encoder (IC 74147) and BCD to & Segment Decoder.

Questions:

1. Draw the logic circuit for the POS expression. (2)

2. What do you mean by SOP and min terms? (2)
3. What do you mean by the following terms: (6)
(a) Max and Min terms, and
(b) Canonical SOP and POS form?
4. Design a full adder circuit by using NAND gates only. (6)
5. How you should implement full adder by using 2 half adder and an OR gate? (4)
6. Design a full adder circuit using logic gates. (6)
7. Design a adder/subtractor by using 4-bit Binary Parallel Adder. (6)
8. Design a BCD adder by using 4-bit Binary Parallel Adder. (5)
9. Draw the circuit diagram of a 4-bit BCD adder and explain the operation. (7)
10. What is meant by priority encoder? (2)
11. What is encoder? Give examples. (2)
12. Describe the operation of 4:2 encoder and design the logic diagram. (3)
13. Show that we can implement any Boolean function by using suitable decoder and OR gates
only (with suitable example). (6)
14. A decoder with enable input can act as a Demultiplexer – explain. (4)
15. Design a 3:8 decoder with enable input. Show that you can implement full adder circuit by
using this decoder. (6+4)
16. Design a logic circuit of a 2 bit magnitude comparator. (4)
17. Design 4-bit comparator which can compare two 4-bits number. (8)
̅̅̅̅̅
18. Simplify: 𝑝 = (𝑥̅ 𝑦̅𝑧) + 𝑧 + 𝑥𝑦 + 𝑤𝑥. (3)
̅ ̅ ̅ ̅ ̅
19. Simplify using Boolean algebra: 𝐴𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶. (3)
20. Convert AC+B into standard canonical form. (4)
21. Simplify the following using K-maps and implement it using basic gates only:
𝑓(𝑎, 𝑏, 𝑐, 𝑑) = ∑ 𝑚(0,1,3,4,5,7,10,13,14,15) (5)
22. Simplify the following using K-maps and implement it using basic gates only:
𝑓(𝑃, 𝑄, 𝑅, 𝑆) = Π𝑀(1,3,8,10,12,13,14,15) (5)
23. Simplify the following expression using K-map and implement the simplified expression
using NAND gates only: 𝑓(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(0,1,4,6,7,10,11,12,13,15) + ∑ 𝑑(2,5,9,14) (10)
24. Simplify the following by using K-map: (4+4)
∑
(a) 𝑓(𝐴, 𝐵, 𝐶, 𝐷) = 𝑚(3,4,5,7,9,13,14,15) + 𝑑(0,2,8,11)
(b) 𝑓(𝐴, 𝐵, 𝐶, 𝐷) = Π𝑀(0,2,4,6,8,11) + 𝑑(5,14)

1
 DIGITAL ELECTRONICS
Combinational Logic Circuits

25. Simplify the following by using K-map: 𝑓(𝐴, 𝐵, 𝐶, 𝐷) = Π𝑀(0,1,2,3,5,6,7,8,12) (5)

26. Simplify the following by using K-map: (4+4)
(c) 𝑓 = ∑(1,4,5,6,7,8,11,12,13,15)
(d) 𝑓 = Π(2,5,4,7,8,11,12,14)

2
 DIGITAL ELECTRONICS
Combinational Logic Circuits

Minterm:

A logical product term containing all the variables of the function in either complemented or
uncomplemented form is called minterm.

• The AND function is referred to as a product.

• ̅ 𝐵̅, 𝐴̅. 𝐵, 𝐴. 𝐵̅ and 𝐴. 𝐵.
A 2-variable function (A, B) has four possible combinations, viz, 𝐴.
• ‘n’ variables have 2𝑛 possible combinations.
• 𝐴̅ = 0 and 𝐴 = 1 for any variable A in case of minterm.

Sum of Product (SOP):

Any Boolean function can be expressed as a sum of minterms (products) which is known as SOP.
Example: 𝑌 = 𝐴. 𝐵. 𝐶 + 𝐴̅. 𝐵. 𝐶 + 𝐴. 𝐵̅. 𝐶. It is basically an OR operations of AND operations.
Minterms representations of three variables (A, B and C):

Minterms A B C Representation
𝐴̅. 𝐵̅. 𝐶̅ 0 0 0 𝑚0
𝐴̅. 𝐵. 𝐶̅ 0 1 0 𝑚2
𝐴. 𝐵̅. 𝐶̅ 1 0 0 𝑚4
𝐴. 𝐵. 𝐶 1 1 1 𝑚7

• For ‘n’ variables, there is 2𝑛 minterms, starting from 𝑚0 to 𝑚2𝑛 −1.

• Example: for 3 – variables, there is 8 minterms, starting from 𝑚0 to 𝑚7 .

Canonical form of SOP:

It is defined as the logical sum of all the minterms for which the value of the function is 1. It is also
called minterm canonical form.

Example: 𝑌(𝐴, 𝐵, 𝐶) = ∑ 𝑚(0,5,6) = 𝑚0 + 𝑚5 + 𝑚6 = 𝐴̅. 𝐵̅. 𝐶̅ + 𝐴. 𝐵̅. 𝐶 + 𝐴. 𝐵. 𝐶̅

Any logical function can be converted into canonical SOP using following rules:

1. Examine variables that are missing in each product which is not a minterm. Multiply the
product by (𝑋 + 𝑋̅), for each variable X that is missing.
2. Multiply all the products and omit the redundant terms.

Example: 𝑌(𝐴, 𝐵, 𝐶) = 𝐴 + 𝐵. 𝐶 = 𝐴. (𝐵 + 𝐵̅). (𝐶 + 𝐶̅ ) + 𝐵. 𝐶. (𝐴 + 𝐴̅) = 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶̅ +

𝐴. 𝐵̅. 𝐶 + 𝐴. 𝐵̅. 𝐶̅ + 𝐴. 𝐵. 𝐶 + 𝐴̅. 𝐵. 𝐶 = 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶̅ + 𝐴. 𝐵̅. 𝐶 + 𝐴. 𝐵̅. 𝐶̅ + 𝐴̅. 𝐵. 𝐶 = 𝑚7 + 𝑚6 +
𝑚5 + 𝑚4 + 𝑚3 = ∑ 𝑚(3,4,5,6,7).

Maxterm:

A sum term containing all variables of a function either in complemented or uncomplemented form
is called a maxterm.

• The OR function is referred to as sum term.

3
 DIGITAL ELECTRONICS
Combinational Logic Circuits

• A 2-variable function (A, B) has four possible combinations, viz, (𝐴̅ + 𝐵̅), (𝐴̅ + 𝐵), (𝐴 +
𝐵̅ )and (𝐴 + 𝐵).
• ‘n’ variables have 2𝑛 possible combinations.
• 𝐴̅ = 1 and 𝐴 = 0 for any variable A in case of maxterm.

Product of Sum (POS):

Any Boolean function can be expressed as a product of maxterms (sum) which is known as POS.
Example: 𝑌 = (𝐴 + 𝐵). (𝐴̅ + 𝐵). It is basically AND operations of OR operated variables. Maxterms
representations of three variables (A, B and C):

Minterms A B C Representation
𝐴̅. 𝐵̅. 𝐶̅ 1 1 1 𝑚7
𝐴̅. 𝐵. 𝐶̅ 1 0 1 𝑚5
𝐴. 𝐵̅. 𝐶̅ 0 1 1 𝑚3
𝐴. 𝐵. 𝐶 0 0 0 𝑚0

• For ‘n’ variables, there is 2𝑛 minterms, starting from 𝑀0 to 𝑀2𝑛 −1 .

• Example: for 3 – variables, there is 8 minterms, starting from 𝑀0 to 𝑀7 .

Canonical POS:

This is defined as the logical product of all the maxterms for which the value of function is ‘0’. It is
also known as the maxterm canonical form.

Example: 𝑌(𝐴, 𝐵, 𝐶) = ∏(0,2,4,7) = 𝑀0 . 𝑀2 . 𝑀4 . 𝑀7 = (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵̅ + 𝐶). (𝐴̅ + 𝐵 +

𝐶). (𝐴̅ + 𝐵̅ + 𝐶̅ ).

Any Boolean function can be converted into canonical maxterm by using the following rules:

1. Examine the variables that are missing in each sum, which is not a maxterm. Add 𝑋. 𝑋̅ to the
sum term, for each variable 𝑋 that is missing.
2. Expand the expression using distributive property and eliminate the redundant terms.

Example: 𝑌(𝐴, 𝐵, 𝐶) = (𝐴 + 𝐵̅). (𝐵 + 𝐶). (𝐴 + 𝐶̅ ) = (𝐴 + 𝐵̅ + 𝐶. 𝐶̅ ). (𝐵 + 𝐶 + 𝐴. 𝐴̅). (𝐴 + 𝐶̅ +

𝐵. 𝐵̅) = (𝐴 + 𝐵̅ + 𝐶). (𝐴 + 𝐵̅ + 𝐶̅ ). (𝐴 + 𝐵 + 𝐶). (𝐴̅ + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶̅ ). (𝐴 + 𝐵̅ + 𝐶̅ ) =
(𝐴 + 𝐵̅ + 𝐶). (𝐴 + 𝐵̅ + 𝐶̅ ). (𝐴 + 𝐵 + 𝐶). (𝐴̅ + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶̅ ) = 𝑀2 . 𝑀3 . 𝑀0 . 𝑀4 . 𝑀1 =
∏𝑀(0,1,2,3,4).

Conversion from canonical SOP to canonical POS and vice versa:

1. Evaluate each product term in the canonical SOP expression, i.e. determine the binary
numbers which represent the product terms.
2. Determine all the binary numbers not included in the evaluation in step 1.
3. Write the equivalent sum term for each binary number from step 2 and express in canonical
POS form.
4. A similar procedure can be used to convert a standard POS expression to a standard SOP
expression.

4
 DIGITAL ELECTRONICS
Combinational Logic Circuits

Example: 𝑌 = ∑ 𝑚(1,4,5,6,7) = ∏𝑀(0,2,3).

Karnaugh Map (K-Map):

The simplification of the Boolean functions using Boolean laws and theorems becomes complex with
the increase in the number of variables and terms. The K-map technique provides a systematic
method for simplifying the Boolean functions.

• In an n – variable K – map, there are 2𝑛 cells. Each cell corresponds to one combination of n
– variables (Minterms/Maxterms).
• For SOP expressions, each cell represents the Minterms. In SOP expression, put 1s in those
cells corresponding to the combinations for which function value is 1.
• For POS expressions, each cell represents the Maxterms. In POS expression, put 0s in those
cells corresponding to the combinations for which function value is 0.

2 – variable K – map

3 – variable K – map

4 – variable K – map

• In the adjacent (physically neighbour) cells, only one variable can change (either from 0 to 1
or vice versa). That is why 11 is followed by 01 not 10.

Adjacent rules:

1. All physically cells are adjacent.

2. Left – most and right – most cells are adjacent.
3. Top – most and bottom – most cells are adjacent.
4. Each corner cells are adjacent.

Procedure to construct K – map in SOP form:

1. Construct the K – map of required number of variables.

(a) Convert the Boolean expression in canonical Minterm (e.g., ∑ 𝑚(0,2,4,7)).
(b) Find the maximum Minterm (𝑚7 ).
(c) Number of variables (bits) required to write maximum Minterm ( 3 bits require to write
7 i.e., 111)

5
 DIGITAL ELECTRONICS
Combinational Logic Circuits

(d) Number of variables = number of variables in K – map (3 variable, eg., A, B, C, so, we

need 3 – variable K – map).
2. Put 1s in those cells corresponding to the combinations for which function value is 1.
3. Try to group of 2𝑛 cells (for n – variables) with adjacent 1s to cover all 1s in the map. If not
possible then try to group 2𝑛−1 , 2𝑛−2, ..., 21 , 20 cells with adjacent 1s.
4. For each group, examine which variables are fixed. Represent the fixed variables for specific
group through product terms ( 0 → 𝐴̅ 𝑎𝑛𝑑 1 → 𝐴).
5. All the product terms are logically added and the added expression is the minimized form of
SOP.

Example: 𝑌 = ∑ 𝑚(1,3,5,7,8,9,12,13)

𝑌 = 𝐴. 𝐶̅ + 𝐴̅. 𝐷

Procedure to construct K – map in POS form:

1. Construct the K – map of required number of variables.

(e) Convert the Boolean expression in canonical Maxterm (e.g.,∏𝑀(0,2,4,7)).
(f) Find the maximum Minterm (𝑚7 ).
(g) Number of variables (bits) required to write maximum Maxterm ( 3 bits require to write
7 i.e., 111)
(h) Number of variables = number of variables in K – map (3 variable, eg., A, B, C, so, we
need 3 – variable K – map).
2. Put 0s in those cells corresponding to the combinations for which function value is 0.
3. Try to group of 2𝑛 cells (for n – variables) with adjacent 0s to cover all 0s in the map. If not
possible then try to group 2𝑛−1 , 2𝑛−2, ..., 21 , 20 cells with adjacent 0s.
4. For each group, examine which variables are fixed. Represent the fixed variables for specific
group through sum terms ( 1 → 𝐴̅ and 0 → 𝐴).
5. All the sum terms are ANDed and the ANDed expression is the minimized form of POS.

Example: 𝑌 = ∏(0,1,4,5,6,8,9,12,13,14)

𝑌 = 𝐶. (𝐵̅ + 𝐷)

Prime Implicant (PI):

6
 DIGITAL ELECTRONICS
Combinational Logic Circuits

The group of 1s/0s are called PI. There are two types of PIs.

1. Essential PI:
The essential PIs are those which included at least one such 1/0 which is not covered by any
other PI.
2. Non-essential PI:
The non-essential PIs are those where all the 1s/0s are covered by some other PI.

Rules for PI:

1. Find out all PIs.

2. Each essential PIs must be present in the final expression.
3. If all essential PIs do not cover all 1s/0s, then use non-essential PI should be present in the
final expression.

Example:

x, y, z → PIs
x and z → essential PIs
y → non-essential PI
𝑌 = 𝑥 + 𝑧 = 𝐴. 𝐵 + 𝐴̅. 𝐵

p, q, r, s → PIs
p & s → essential PIs
r & q → non-essential PIs
As p & s do not cover all 1s, one of the non-
essential PI should be present in the final
expression.
𝑌 = 𝑝 + 𝑠 + 𝑞 or 𝑝 + 𝑠 + 𝑟
= 𝐴. 𝐵. 𝐶̅ + 𝐴̅. 𝐶. 𝐷 + 𝐵. 𝐶̅ . 𝐷 OR
𝐴. 𝐵. 𝐶̅ + 𝐴̅. 𝐶. 𝐷 + 𝐴̅. 𝐵. 𝐷

Don’t care combinations:

In certain digital systems, some input combinations never occur during the process of a normal
operation because those input conditions are guaranteed never to occur. Such input combinations
are don’t care combinations.

We don’t care what the function output is for such combinations. These combinations can be
plotted on K – map to provide further simplification of the function.

Rule of don’t care combinations:

It is not necessary to cover all the ‘d’s (don’t care terms), but it helps to form bigger group.

Example: 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(1,3,7,11,15) + ∑ 𝑑(0,2,5)

7
 DIGITAL ELECTRONICS
Combinational Logic Circuits

𝑌 = 𝐴̅. 𝐵̅ + 𝐶. 𝐷

Combinational logic circuit:

Combinational logic circuits are circuits in which the output at any time depends upon the
combination of the input signals present at that time instant only, and does not depend upon any
past conditions.

Most important combinational circuits (which are also available in IC packages):

1. Adder
2. Subtractor
3. Comparator
4. Decoder & Encoder
5. Multiplexer
6. Demultiplexer
7. Parity generator/checker
8. Code converter

Procedure for the design of combinational circuits:

1. From the word description of the problem, identify the inputs and outputs and draw a block
diagram.
2. Draw a truth table such that it completely describes the operation of the circuit for different
combinations of inputs.
3. Write down the switching expression(s) for the output(s).
4. Simplify the switching expressions using either algebraic or K-map method.
5. Implement the simplified expression using logic gates.

Half adder:

It performs the arithmetic addition of two binary digits. It has two inputs and two outputs. The two
inputs are the two 1-bit numbers A and B, and the two outputs are the sum (S) of A and B and the
carry bit (C).

Block diagram Truth table

8
 DIGITAL ELECTRONICS
Combinational Logic Circuits

Inputs Outputs
Augend Addend Sum Carry
(A) (B) (S) (C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Switching expression for the outputs:

𝑆 = 𝐴̅. 𝐵 + 𝐴. 𝐵̅ = 𝐴⨁𝐵

𝐶 = 𝐴. 𝐵

Implementation using gates:

A half adder has only two inputs and there is no provision to add a carry coming from the lower
order bits when multi-bit addition is performed.

Full adder:

It is a combinational circuit that performs the arithmetic sum of three input bits and produces a sum
(S) output and a carry (𝐶𝑜𝑢𝑡 ). The two input variables denoted by A (Augend bit) and B (Addend bit)
represent the two significant bits to be added. The third input 𝐶𝑖𝑛 represents the carry from the
previous lower significant position.

Block diagram Truth table

9
 DIGITAL ELECTRONICS
Combinational Logic Circuits

Inputs Outputs
Augend Addend Carry Sum Carry
(A) (B) (𝐶𝑖𝑛 ) (s) (𝐶𝑜𝑢𝑡 )
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Switching expressions for the outputs:

𝑆 = 𝐴̅. 𝐵̅. 𝐶𝑖𝑛 + 𝐴.

̅ 𝐵. 𝐶𝑖𝑛
̅ + 𝐴. 𝐵̅. 𝐶𝑖𝑛
̅ + 𝐴. 𝐵. 𝐶𝑖𝑛 = 𝐴̅. (𝐵̅. 𝐶𝑖𝑛 + 𝐵. 𝐶𝑖𝑛
̅ ) + 𝐴. (𝐵̅. 𝐶𝑖𝑛
̅ + 𝐵. 𝐶𝑖𝑛 )
= 𝐴̅. (𝐵⨁𝐶𝑖𝑛 ) + 𝐴. (𝐵⨁𝐶
̅̅̅̅̅̅̅̅̅
𝑖𝑛 ) = 𝐴⨁𝐵⨁𝐶𝑖𝑛

𝐶𝑜𝑢𝑡 = 𝐴̅. 𝐵. 𝐶𝑖𝑛 + 𝐴. 𝐵̅. 𝐶𝑖𝑛 + 𝐴. 𝐵. 𝐶𝑖𝑛

̅ + 𝐴. 𝐵. 𝐶𝑖𝑛 =
∑ 𝑚(3,5,6,7)

𝐶𝑜𝑢𝑡 = 𝐴. 𝐵 + 𝐵. 𝐶𝑖𝑛 + 𝐴. 𝐶𝑖𝑛

Implementation using gates:

Half Subtractor:

It is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X
(minuend) and Y (subtrahend) and two outputs D (difference) and 𝐵𝑜𝑢𝑡 (borrow out).

Block diagram Truth table

10
 DIGITAL ELECTRONICS
Combinational Logic Circuits

inputs Outputs
Minuend Subtrahend Difference Borrow
(X) (Y) (D) (𝐵𝑜𝑢𝑡 )
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Switching expressions and implementation using gates:

𝐷 = 𝑋̅. 𝑌 + 𝑋. 𝑌̅ = 𝑋⨁𝑌

𝐵𝑜𝑢𝑡 = 𝑋̅. 𝑌

Full Subtractor:

It is a combinational circuit that performs subtraction involving three bits, namely minuend bit (X),
subtrahend bit (Y) and borrow (𝐵𝑖𝑛 ) from the previous stage.

Block diagram Truth table

Inputs Outputs
Minuend Subtrahend Borrow Difference Borrow
(X) (Y) (𝐵𝑖𝑛 ) (D) out
(𝐵𝑜𝑢𝑡 )
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Switching expression for the outputs:

𝐷 = 𝑋̅. 𝑌̅. 𝐵𝑖𝑛 + 𝑋̅. 𝑌. 𝐵̅𝑖𝑛 + 𝑋. 𝑌̅. 𝐵̅𝑖𝑛 + 𝑋. 𝑌. 𝐵𝑖𝑛 = 𝑋̅. (𝑌̅. 𝐵𝑖𝑛 + 𝑌. 𝐵̅𝑖𝑛 ) + 𝑋. (𝑌̅. 𝐵̅𝑖𝑛 + 𝑌. 𝐵𝑖𝑛 ) =
𝑋̅. (𝑌⨁𝐵𝑖𝑛 ) + 𝑋. (𝑌⨁𝐵
̅̅̅̅̅̅̅̅̅
𝑖𝑛 ) = 𝑋⨁𝑌⨁𝐵𝑖𝑛

11
 DIGITAL ELECTRONICS
Combinational Logic Circuits

𝐵𝑜𝑢𝑡 = 𝑋̅. 𝑌̅. 𝐵𝑖𝑛 + 𝑋̅. 𝑌. 𝐵̅𝑖𝑛 + 𝑋̅. 𝑌. 𝐵𝑖𝑛

+ 𝑋. 𝑌. 𝐵𝑖𝑛 = ∑ 𝑚(1,2,3,7)

𝐵𝑜𝑢𝑡 = 𝑋̅. 𝑌 + 𝑋̅ . 𝐵𝑖𝑛 + 𝑌. 𝐵𝑖𝑛

Implementation using gates:

Decoder:

A decoder is similar to DMUX but without any data input. Most digital systems require the decoding
of data. Decoding is necessary in application such as –

1. Data demultiplexing,
2. Digital display,
3. Digital to analog converters and
4. Memory addressing.

A decoder is a combinational logic circuit that converts n – bit binary input code (data) into 2n
output lines; (n to 2n decoder) such that each output line will be activated for only one of the
possible combinations of inputs.

[N.B.: Decoder is not a converter because in digital converter, number of inputs = number of
outputs.]

2 to 4 Decoder:

12
 DIGITAL ELECTRONICS
Combinational Logic Circuits

Inputs Outputs
𝑒𝑛
A B 𝑓0 𝑓1 𝑓2 𝑓3
0 0 1 1 0 0 0
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 1

When 𝑒𝑛 is 1 i.e., enable input is high then only

the decoder works.
𝑓0 = 𝑒𝑛 . 𝐴̅. 𝐵̅ ,
𝑓1 = 𝑒𝑛 . 𝐴̅. 𝐵,
𝑓2 = 𝑒𝑛 . 𝐴. 𝐵̅ ,
𝑓3 = 𝑒𝑛 . 𝐴. 𝐵.

3 to 8 Decoder:

Inputs Outputs
𝑒𝑛
A B C 𝑓0 𝑓1 𝑓2 𝑓3 𝑓4 𝑓5 𝑓6 𝑓7
0 0 0 1 1 0 0 0 0 0 0 0
0 0 1 1 0 1 0 0 0 0 0 0
0 1 0 1 0 0 1 0 0 0 0 0
0 1 1 1 0 0 0 1 0 0 0 0
1 0 0 1 0 0 0 0 1 0 0 0
1 0 1 1 0 0 0 0 0 1 0 0
1 1 0 1 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 1

Implementation of 3 to 8 decoder using 2 to 4 decoder:

13
 DIGITAL ELECTRONICS
Combinational Logic Circuits

𝐼2 𝐼1 𝐼0 f
0 0 0 𝑓0
0 0 1 𝑓1
0 1 0 𝑓2
0 1 1 𝑓3
1 0 0 𝑓4
1 0 1 𝑓5
1 1 0 𝑓6
1 1 1 𝑓7

Implementation of Boolean expression using decoders:

1. Convert the expression in canonical minterms.

2. Choose proper decoder.
(Number of variables in the expression = inputs in the decoder = x ⇒ requirements: x to 2𝑥
decoder)
3. Variables are connected to the inputs of the decoder.
4. Corresponding outputs according to the minterms of the expression are connected to an OR
gate. The output of the OR gate is the required expression.

Example: 𝑓 = ∑ 𝑚(0,3,4,5) ⇒ number of variables = 3 (A, B, C) ⇒ 3 to 8 decoder is required.

Example: 𝑓1 = ∑ 𝑚(0,2,7) & 𝑓2 = ∑ 𝑚(0,2,3,4,6) ⇒ 3 to 8 decoder is required.

BCD to seven segment Decoder/Driver:

14
 DIGITAL ELECTRONICS
Combinational Logic Circuits

A seven segment display is normally used for displaying any one of the decimal digits, 0 through 9. A
BCD to seven segment decoder accepts a decimal digit in BCD and generates the corresponding
seven segment code.

Following figure shows a seven segment display composed of seven elements or segments. Each
segment is made up of a material that emits light when current is passed through it. Most commonly
used displays are LEDs and incandescent filaments. Letters a, b, c d, e, f and g run clockwise from the
top of each segment. For instance, to display a 1, the segments b and c have to be illuminated; to
display a 0, the segments a, b, c, d, e and f have to be illuminated by properly forward biasing the
LEDs in the selected segments.

Design of BCD to seven segment decoder:

A BCD to seven segment decoder can be designed using logic gates. A block diagram of BCD to seven
segment decoder with four BCD inputs (A, B, C, D) and seven outputs (a, b, c, d, e, f and g),
corresponding to seven segments of a display, is shown in the following figure. The truth table of the
BCD to seven segment decoder is shown in following table.

Block diagram of BCD to seven-segment decoder

BCD inputs Seven segment outputs
A B C D a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1

Since only BCD inputs are valid combination, the other input combination of four variables
corresponding to 10, 11, 12, 13, 14 and 15 can be termed as don’t care combination to aid the

15
 DIGITAL ELECTRONICS
Combinational Logic Circuits

simplification of logic expressions. Now, the logic expressions corresponding to seven segment can
be written from the truth table:

𝑎 = ∑ 𝑚(0,2,3,5,6,7,8,9) + ∑ 𝑑(10,11,12,13,14,15)

The above expression can be simplified using K-map method as shown in the following figure:

From the above K-map, 𝑎 = 𝐴 + 𝐵 + 𝐵. 𝐷 + 𝐵̅. 𝐷

̅ = 𝐴 + 𝐶 + ̅̅̅̅̅̅̅
𝐵⨁𝐷

Similarly, 𝑏 = ∑ 𝑚(0,1,2,3,4,7,8,9) + ∑ 𝑑(10,11,12,13,14,15) = 𝐵̅ + 𝐶. 𝐷 + 𝐶̅ . 𝐷

̅ = 𝐵̅ + ̅̅̅̅̅̅̅
𝐶⨁𝐷

𝑐 = ∑ 𝑚(0,1,3,4,5,6,7,8,9) + ∑ 𝑑(10,11,12,13,14,15) = 𝐵 + 𝐶̅ + 𝐷

𝑑 = ∑ 𝑚(0,2,3,5,6,8,9) + ∑ 𝑑(10,11,12,13,14,15) = 𝐴 + 𝐵̅. 𝐷 ̅ + 𝐵̅. 𝐶 + 𝐵. 𝐶̅ . 𝐷 = 𝐴 +

̅ + 𝐶. 𝐷
̅ + 𝐵.
𝐶. 𝐷 ̅ ) + 𝐵. 𝐶̅ . 𝐷 = 𝐴 + 𝐶. 𝐷
̅ (𝐶 + 𝐷 ̅ + 𝐵⨁(𝐶 + 𝐷
̅)

𝑒 = ∑ 𝑚(0,2,6,8) + ∑ 𝑑(10,11,12,13,14,15) = 𝐵̅. 𝐷

̅ + 𝐶. 𝐷
̅=𝐷
̅ . (𝐵̅ + 𝐶)

𝑓 = ∑ 𝑚(0, ,4,5,6,8,9) + ∑ 𝑑(10,11,12,13,14,15) = 𝐴 + 𝐶̅ . 𝐷

̅ + 𝐵. 𝐶̅ + 𝐵. 𝐷
̅ = 𝐴 + 𝐶̅ . 𝐷
̅+
𝐵. (𝐶̅ + 𝐷
̅)

̅ + 𝐵. 𝐶̅ + 𝐵̅. 𝐶 = 𝐴 + 𝐶. 𝐷
𝑔 = ∑ 𝑚(2,3,4,5,6,8,9) + ∑ 𝑑(10,11,12,13,14,15) = 𝐴 + 𝐶. 𝐷 ̅ + 𝐵⨁𝐶

Now, using the above simplified expressions for seven segment outputs, the BCD to seven segment
decoder can be implemented using logic gates as shown in the following figure:

16
 DIGITAL ELECTRONICS
Combinational Logic Circuits

IC 7446/7447 and IC 7448/7449 – BCD to seven segment decoders:

ICs 7446 and 7447 are BCD to seven segment decoders with active LOW open collector outputs
designed for driving common anode seven-segment displays. ICs 7448 and 7449 are with active
HIGH outputs for driving common cathode seven-segment displays.

Following figure shows a BCD to seven-segment decoder/driver (TTL 7446 or 7447) used to drive a
common anode 7-segment LED display. Each segment consists of one LED and the anodes of all LEDs
are connected to +VCC (5 V). The cathodes of the LEDs are connected through current-limiting
resistors to the appropriate outputs of the decoder/driver. By forward-biasing different LRDs, the
digits 0 through 9 can be displayed.

17
 DIGITAL ELECTRONICS
Combinational Logic Circuits

BCD to 7-segment decoder driving a common anode 7-segment LED display

Application of Decoder:

1. Decoders are used in counter systems.

2. They are used in analog to digital converters.
3. Decoder outputs can be used to drive a display system.

Encoder:

An encoder is a digital circuit that performs the inverse operation of a decoder. Hence, the opposite
of the decoding process is called encoding. An encoder is a combinational logic circuit that converts
an active input signal into a coded output signal.

It has n input lines, only one of which

is active at any time and m output
lines. It encodes one of the active
inputs to a coded binary output with
m bits. In an encoder, the number of
outputs is less than the number of
inputs. The block diagram of an
encoder is shown in the figure. Block diagram of an encoder

Octal to Binary Encoder:

It accepts eight inputs and produces a 3 – bit output code corresponding to the activated input. The
truth table for the octal to binary encoder is shown below:

Inputs Outputs
𝐷0 𝐷1 𝐷2 𝐷3 𝐷4 𝐷5 𝐷6 𝐷7 𝑌2 𝑌1 𝑌0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

18
 DIGITAL ELECTRONICS
Combinational Logic Circuits

Above truth table shows that 𝑌0 (LSB of output code) must be 1 whenever the input 𝐷1 OR 𝐷3 OR 𝐷5
OR 𝐷7 is HIGH. Thus, 𝑌0 = 𝐷1 + 𝐷3 + 𝐷5 + 𝐷7. Similarly, 𝑌1 = 𝐷2 + 𝐷3 + 𝐷6 + 𝐷7 and 𝑌2 = 𝐷4 +
𝐷5 + 𝐷6 + 𝐷7 .

Using the above expressions, the octal to

binary encoder can be implemented using
three 4 – input OR gates as shown in the figure.
The circuit is designed in such a way that, when
𝐷0 is HIGH, the binary code 000 is generated;
when 𝐷1is HIGH, the binary code 001 is
generated, and so on.

Octal to binary encoder

Decimal to BCD Encoder:

A decimal to BCD encoder is one with ten inputs corresponding to ten decimal digits (0 to 9) and four
outputs (A, B, C, D) representing the BCD value of input decimal digit. The truth table for a decimal
to BCD encoder is shown below:

Decimal inputs BCD outputs

0 1 2 3 4 5 6 7 8 9 A B C D
1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 0 0 0 0 1 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 1
0 0 0 0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 1 0 0 1

From the above truth table, it is clear that the output A is HIGH whenever the input 8 OR 9 is HIGH.
Therefore, A = 6 + 9.
The output B is HIGH whenever the input 4 OR 5 OR 6 OR 7 is HIGH. Therefore, B = 4 + 5 + 6 + 7.
Similarly, C = 2 + 3 + 6 + 7 and D = 1 + 3 + 5 + 7 + 9.
Now the above expression for BCD outputs can be implemented as shown in the following figure
using four OR gates. Here, the inputs are ten push button type switches, each representing one of
the decimal digits.

19
 DIGITAL ELECTRONICS
Combinational Logic Circuits

Decimal to BCD encoder

Priority encoder:

A priority encoder is an encoder that includes the priority function. The operation of the priority
encoder is such that if two or more inputs are equal to 1 at the same time, the input having the
highest priority will take precedence. The truth table of a four input priority encoder is given in the
following table:

Inputs Outputs
D0 D1 D2 D3 Y2 Y1 V
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1

The Xs are don’t care conditions that designate the fact that the binary values they represent may be
equal to 0 or 1. Input D3 has the highest priority; so regardless of the values of the other inputs,
when this input is 1, the output Y2 Y1 is 11 (i.e., 3). D2 has the next priority level. The output is 10 if
D2 = 1 and D3 = 0, irrespective of the values of the other two lower-priority inputs. The output for
D1 is generated only if higher priority inputs are 0, and so on down the priority level. A valid output
indicator, V, is set to 1 only when one or more of the inputs are equal to 1. If all the inputs are 0, V is
equal to 0, and the other two outputs of the circuit are not used. IC 74147 and IC 74148 are some of
the priority encoder ICs.

IC 74148 – 8 to 3 Priority Encoder:

IC 74148 encodes 8 data lines to 3 – bit binary (octal). It is also a priority encoder because it gives
priority to the highest order input. Here, both the data inputs and outputs are active LOW. In
addition, an enable input (EI) and an enable output (EO) are provided to cascade 74148 ICs. This
allows octal expansion without the need for an external circuitry. The enable input must be asserted
to LOW state to enable the chip while the enable output goes to LOW state only when all inputs are
inactive (i.e. in HIGH state). Also, there is one more output, namely GS, which goes LOW whenever

20
 DIGITAL ELECTRONICS
Combinational Logic Circuits

one of its inputs is active (i.e. in LOW state). Its operation is explained in the following truth table
and its logic symbol is shown below.

Inputs Outputs
EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO
1 X X X X X X X X 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0
0 X X X X X X X 0 0 0 0 0 1
0 X X X X X X 0 1 0 0 1 0 1
0 X X X X X 0 1 1 0 1 0 0 1
0 X X X X 0 1 1 1 0 1 1 0 1
0 X X X 0 1 1 1 1 1 0 0 0 1
0 X X 0 1 1 1 1 1 1 0 1 0 1
0 X 0 1 1 1 1 1 1 1 1 0 0 1
0 0 1 1 1 1 1 1 1 1 1 1 0 1

Logic symbol of IC 74148 – 8 to 3 priority encoder

IC 74147 – Decimal to BCD Priority Encoder:

The PIN diagram of IC 74147, a decimal to BCD priority encoder is shown in the following figure (a)
and its logic symbol is shown in figure (b). Its truth table is given in the following table. It has 9 active
LOW inputs representing the decimal digits, 1 through 9 and produces the inverted BCD code
corresponding to the highest order activated input.

Inputs Outputs
X1 X2 X3 X4 X5 X6 X7 X8 X9 A B C D
1 1 1 1 1 1 1 1 1 1 1 1 1
X X X X X X X X 0 0 1 1 0
X X X X X X X 0 1 0 1 1 1
X X X X X X 0 1 1 1 0 0 0
X X X X X 0 1 1 1 1 0 0 1
X X X X 0 1 1 1 1 1 0 1 0
X X X 0 1 1 1 1 1 1 0 1 1
X X 0 1 1 1 1 1 1 1 1 0 0
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0

21
 DIGITAL ELECTRONICS
Combinational Logic Circuits

Logic symbol of 74147

PIN diagram of 74147

When all inputs (X1 − X 9 ) are HIGH, all the outputs are HIGH (i.e. 1111) which is the inverse of 0000,
the BCD code for 0. When X 9 is LOW, the ABCD output is 0110, which is the inverse 1001, the BCD
code for 9; when X 8 is LOW, the ABCD output is 0111, the inverse of 1000, the BCD code for 8.
Hence, the outputs of IC 74147 will normally be HIGH when none of the inputs is activated. This
corresponds to the decimal 0 input condition. Since there is no X 0 input, the encoder assumes the
decimal 0 input state when the all inputs are HIGH.

The 74147 is called a priority encoder because it gives priority to the highest-order input. For
example, at a particular instant, if both the inputs X 3 and X 5 are activated, then the highest priority
of these two inputs (i.e. X 5) is encoded as 1010 which is the inverse of 0101.

22