Functional Blocks

ECSE 1104
Digital Circuits and Systems
Presentation Outline

❖ Decoders And Encoders

❖ Multiplexers

❖ Design Example And Assignment

 Functional Blocks
❖ A functional block is a combinational circuit
❖ We will study blocks, such as decoders and multiplexers
❖ Functional blocks are very common and useful in design
❖ In the past, functional blocks were integrated circuits
SSI: Small Scale Integration = tens of gates
MSI: Medium Scale Integration = hundreds of gates
LSI: Large Scale Integration = thousands of gates
VLSI: Very Large Scale Integration = millions of gates
❖ Today, functional blocks are part of a design library
❖ Tested for correctness and reused in many projects
 Binary Decoders
❖ Given a n-bit binary code, there are 2n possible code values

❖ The decoder has an output for each possible code value

❖ The n-to-2n decoder has n inputs and 2n outputs

❖ Depending on the input code, only one output is set to logic 1

❖ The conversion of input to output is called decoding

2n Outputs A decoder can have less

n Inputs

n to 2n
than 2n outputs if some




Decoder
input codes are unused
 Examples of Binary Decoders
Inputs Outputs
0 d0 a1 a0 d0 d1 d2 d3

4 Outputs
2 Inputs

a1 1 2-to-4 1 d1 0 0 1 0 0 0
Truth
a0 0 2 d2 0 1 0 1 0 0
Decoder Tables
3 d3 1 0 0 0 1 0
1 1 0 0 0 1

Inputs Outputs
0 d0
a2 a1 a0 d0 d1 d2 d3 d4 d5 d6 d7
1 d1
0 0 0 1 0 0 0 0 0 0 0
2 d2 8 Outputs 0 0 1 0 1 0 0 0 0 0 0
a2
3 Inputs

2
3-to-8 3 d3 0 1 0 0 0 1 0 0 0 0 0
a1 1
Decoder 4 d4 0 1 1 0 0 0 1 0 0 0 0
a0 0
5 d5 1 0 0 0 0 0 0 1 0 0 0
6 d6 1 0 1 0 0 0 0 0 1 0 0
d7 1 1 0 0 0 0 0 0 0 1 0
7
1 1 1 0 0 0 0 0 0 0 1
 Decoder Implementation
Inputs Outputs 𝑎2
a1 a0 d0 d1 d2 d3 3-to-8 Decoder
0 0 1 0 0 0
𝑎1
0 1 0 1 0 0 𝑎0 𝑑0 = 𝑎2′ 𝑎1′ 𝑎0′
1 0 0 0 1 0
1 1 0 0 0 1
𝑑1 = 𝑎2′ 𝑎1′ 𝑎0
2-to-4
𝑎1
Decoder 𝑑2 = 𝑎2′ 𝑎1 𝑎0′

𝑎0 𝑑0 = 𝑎1′ 𝑎0′ 𝑑3 = 𝑎2′ 𝑎1 𝑎0

𝑑1 = 𝑎1′ 𝑎0 𝑑4 = 𝑎2 𝑎1′ 𝑎0′
𝑑2 = 𝑎1 𝑎0′ 𝑑5 = 𝑎2 𝑎1′ 𝑎0
𝑑3 = 𝑎1 𝑎0 𝑑6 = 𝑎2 𝑎1 𝑎0′
𝑑7 = 𝑎2 𝑎1 𝑎0
Each decoder output is a minterm
 Using Decoders to Implement Functions
❖ A decoder generates all the minterms
❖ A Boolean function can be expressed as a sum of minterms
❖ Any function can be implemented using a decoder + OR gate
Note: the function must not be minimized
❖ Example: Full Adder sum = ∑(1, 2, 4, 7), cout = ∑(3, 5, 6, 7)
Inputs Outputs
d0
a b cin cout sum
d1
0 0 0 0 0 sum
0 0 1 0 1 d2
a 2
0 1 0 0 1 3-to-8 d3
b 1
0 1 1 1 0 Decoder d4
1 0 0 0 1 cin 0 cout
d5
1 0 1 1 0 d6
1 1 0 1 0
1 1 1 1 1 d7
 Using Decoders to Implement Functions
❖ Good if many output functions of the same input variables
❖ If number of minterms is large ➔ Wider OR gate is needed
❖ Use NOR gate if number of maxterms is less than minterms
❖ Example: f = ∑(2, 5, 6), g = ∏(3, 6) ➔ g' = ∑(3, 6), h = ∑(0, 5)
Inputs Outputs
a b c f g h d0
0 0 0 0 1 1 d1 f
0 0 1 0 1 0 d2
a 2
0 1 0 1 1 0 3-to-8 d3
b 1 g
0 1 1 0 0 0
c 0 Decoder d4
1 0 0 0 1 0 d5
1 0 1 1 1 1 d6 h
1 1 0 1 0 0 d7
1 1 1 0 1 0
 2-to-4 Decoder with Enable Input
Truth Table
0 d0
Inputs Outputs a1 1
2-to-4 1 d1
a0 0
d2
EN a1 a0 d0 d1 d2 d3 Decoder 2
EN 3 d3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0 𝑎1
1 1 0 0 0 1 0
𝑎0 𝑑0 = 𝐸𝑁 𝑎1′ 𝑎0′
1 1 1 0 0 0 1
𝑑1 = 𝐸𝑁 𝑎1′ 𝑎0

If EN input is zero then 𝑑2 = 𝐸𝑁 𝑎1 𝑎0′

all outputs are zeros, 𝑑3 = 𝐸𝑁 𝑎1 𝑎0
regardless of a1 and a0 𝐸𝑁
 Building Larger Decoders
❖ Larger decoders can be build using smaller ones
❖ A 3-to-8 decoder can be built using:
Two 2-to-4 decoders with Enable and an inverter (1-to-2 decoder)
Inputs Outputs a2
0 d0
a2 a1 a0 d0 d1 d2 d3 d4 d5 d6 d7 a1 1 Top 1 d1
0 0 0 1 0 0 0 0 0 0 0 a0 0 2-to-4
Decoder
2 d2
0 0 1 0 1 0 0 0 0 0 0 EN 3 d3
0 1 0 0 0 1 0 0 0 0 0

1-to-2 Decoder
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
0 d4
1 Bottom
1 0 1 0 0 0 0 0 1 0 0
1 d5
0 2-to-4
Decoder
2 d6
1 1 0 0 0 0 0 0 0 1 0
EN 3 d7
1 1 1 0 0 0 0 0 0 0 1
 Building Larger Decoders
a1 1 0 d0
2-to-4
1 d1
A 4-to-16 a0 0 Decoder
2 d2
0
EN 3 d3
decoder with
enable can be 1 0 d4
2-to-4
1 d5
built using five 0 Decoder
2 d6
0 1
a3 1 EN 3 d7
2-to-4 decoders 2-to-4 1
a2 0
Decoder 2 d8
with enables 1 2-to-4
0
EN EN 3 1 d9
0 Decoder
2 d10
2
EN 3 d11

Larger decoders can be built 1 0 d12

2-to-4
1 d13
hierarchically in a similar way 0 Decoder
2 d14
3
EN 3 d15
 BCD to 7-Segment Decoder
❖ Seven-Segment Display:
 Made of Seven segments: light-emitting diodes (LED)
 Found in electronic devices: such as clocks, calculators, etc.

a
I3 BCD to b
I2 c
❖ BCD to 7-Segment Decoder I1
7-Segment d
e
 Called also a decoder, but not a binary decoder I0 Decoder f
g
 Accepts as input a BCD decimal digit (0 to 9)
 Generates output to the seven LED segments to display the BCD digit
 Each segment can be turned on or off separately
 BCD to 7-Segment Decoder
Specification: Truth Table
 Input: 4-bit BCD (I3, I2, I1, I0) BCD input 7-Segment Output
I3 I2 I1 I0 a b c d e f g
 Output: 7-bit (a, b, c, d, e, f, g)
0 0 0 0 1 1 1 1 1 1 0
 Display should be OFF for Non-BCD 0 0 0 1 0 1 1 0 0 0 0
input codes. 0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
Implementation can use: 0 1 0 0 0 1 1 0 0 1 1
 A binary decoder 0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
 Additional gates
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
1010 to 1111 0 0 0 0 0 0 0
 Implementing a BCD to 7-Segment Decoder
Truth Table
a
I3 I2 I1 I0 a b c d e f g
0
b 0 0 0 0 1 1 1 1 1 1 0
1
2 0 0 0 1 0 1 1 0 0 0 0
c
I3 3 0 0 1 0 1 1 0 1 1 0 1
4-to-10
I2 4 0 0 1 1 1 1 1 1 0 0 1
d
Binary 5 0 1 0 0 0 1 1 0 0 1 1
I1
I0 Decoder 6 e 0 1 0 1 1 0 1 1 0 1 1
7 0 1 1 0 1 0 1 1 1 1 1
8 0 1 1 1 1 1 1 0 0 0 0
9 f 1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
𝐼3(𝐼2 + 𝐼1 ) g 1010 – 1111 0 0 0 0 0 0 0
Input > 9
NOR gate is used for 0's
 Encoders
❖ An Encoder has 2n binary inputs and n
outputs.

❖ The output is a binary encoding of one of

the asserted input of the 2 n inputs. The
binary encoder output is unpredictable if
multiple inputs are asserted at the same
time.

❖ The conversion of input to output is

called encoding.
 Priority Encoders
❖ A priority encoder overcomes the limitation of the binary
encoder with regards to handling multiple input assertion.

❖ The encoding of the input with higher priority assignment is

outputted over a lower priority input if both are asserted.

❖ This achieved by defining a set of intermediary outputs that will

force lower priority inputs to logic low if an higher priority input
is selected. Final output Logic – same as
binary encoder but uses the
Intermediary outputs as inputs
Intermediary output Logic

The IDLE out is set to high

when no input is asserted.
 Next . . .

❖ Decoders and Encoders

❖ Multiplexers

❖ Design Example And Assignment

 Multiplexers
❖ Selecting data is an essential function in digital systems

❖ Functional blocks that perform selecting are called multiplexers

❖ A Multiplexer (or Mux) is a combinational circuit that has:

d0
 Multiple data inputs (typically 2n) to select from d1

2n Inputs
d2

Mux
. Y
 An n-bit select input S used for control .
.
d2n–1
 One output Y n
S
❖ The n-bit select input directs one of the data inputs to the output
 Examples of Multiplexers
❖ 2-to-1 Multiplexer Inputs Output
d0 0
if (S == 0) Y = d0 ; S d0 d1 Y

Mux
Y
else Y = d1; 0 0 X 0 = d0
d1 1
0 1 X 1 = d0
Logic expression: 1 X 0 0 = d1
S 1 X 1 1 = d1
𝑌 = 𝑑0 𝑆 ′ + 𝑑1 𝑆
❖ 4-to-1 Multiplexer d0 0 Inputs Output
d1 1 S1 S0 d0 d1 d2 d3 Y

Mux
if (S1S0 == 00) Y = d0 ; 𝑌 0 0 0 X X X 0 = d0
d2 2
else if (S1S0 == 01) Y = d1; 0 0 1 X X X 1 = d0
d3 3
else if (S1S0 == 10) Y = d2; 0 1 X 0 X X 0 = d1
S1S0 0 1 X 1 X X 1 = d1
else Y = d3; 1 0 X X 0 X 0 = d2
1 0 X X 1 X 1 = d2
Logic expression:
1 1 X X X 0 0 = d3
𝑌 = 𝑑0 𝑆1′ 𝑆0′ + 𝑑1 𝑆1′ 𝑆0 + 𝑑2 𝑆1 𝑆0′ + 𝑑3 𝑆1 𝑆2 1 1 X X X 1 1 = d3
 Implementing Multiplexers
d0
d0 0
Mux
𝑌 = 𝑑0 𝑆 ′ + 𝑑1 𝑆 Y
d1
d1 1
Enabling
S AND Gates
S

d0
d0 0
d1
d1 1
Mux

𝑌 = 𝑑0 𝑆1′ 𝑆0′ + 𝑑1 𝑆1′ 𝑆0 d2 Y

d2 2
d3 3 + 𝑑2 𝑆1 𝑆0′ + 𝑑3 𝑆1 𝑆0
d3
S1S0
Enabling
S1 AND Gates
S0
 3-State Gate
❖Logic gates studied so far have two outputs: 0 and 1
❖Three-State gate has three possible outputs: 0, 1, Z
 Z is the Hi-Impedance output
 Z means that the output is disconnected from the input
 Gate behaves as an open switch between input and output

❖Input c connects input to output c x f

 c is the control (enable) input 𝑐 0 0 Z
0 1 Z
 If c is 0 then f = Z 𝑥 𝑓 1 0 0
 If c is 1 then f = input x 3-state gate 1 1 1
 Variations of the 3-State Gate
❖ Control input c and output f can be inverted
❖ A bubble is inserted at the input c or output f
𝑐 𝑐 𝑐

𝑥 𝑓 𝑥 𝑓 𝑥 𝑓
inverted c inverted f inverted c, f
c x f c x f c x f
0 0 0 0 0 Z 0 0 1
0 1 1 0 1 Z 0 1 0
1 0 Z 1 0 1 1 0 Z
1 1 Z 1 1 0 1 1 Z
 Wired Output
Logic gates with 0 and 1 𝑎 This will result in a
𝑏
outputs cannot have their 𝑓 short circuit that
𝑐
outputs wired together 𝑑 will burn the gates

𝑐1 c1 c2 c3 f
3-state gates can wire 0 0 0 Z
their outputs together 𝑥1 1 0 0 x1
𝑐2 0 1 0 x2
At most one 3-state gate 0 0 1 x3
𝑥2 𝑓
can be enabled at a time 0 1 1 Burn
𝑐3 1 0 1 Burn
Otherwise, conflicting 1 1 0 Burn
𝑥3
outputs will burn the circuit 1 1 1 Burn
Implementing Multiplexers with 3-State Gates

A Multiplexer can also d0 0

be implemented using: d1 1

Mux
𝑌
d2 2 3-State
1. A decoder Gates
d3 3
2. Three-state gates d0
S1S0

3-State
d1
Gates Y
d0 0 d0 d2
Mux

Y Y
d1 1 d1 d3

S 0 1 2 3
S S1 1 2-to-4
1-to-2
Decoder S0 0 Decoder
 Building Larger Multiplexers
Larger multiplexers can be built hierarchically using smaller ones

d0 0 d0 0
d0 0 d1 1 d1 1

Mux
Mux

d2 d2 2

8-to-1 Mux
d1 1 2
0 d3 3
d3
Mux
3 Y
S0 Y
1 0 d4 4

Mux
d2 0 S1S0 Y d5 5
Mux

S1 1
d3 1 d4 0 d6 6
S2 d7 7
d5 1

Mux
S0
d6 2 S2S1S0
d7 3

Building 4-to-1 S1S0 Building 8-to-1 Mux

Mux using three using two 4-to-1 Muxes
2-to-1 Muxes and a 2-to-1 Mux
 Multiplexers with Vector Input and Output
The inputs and output of a multiplexer can be m-bit vectors

A [m–1:0] 0
A [m–1:0] 0 m
m B [m–1:0]
Mux
1

Mux
Y [m–1: 0] m Y [m–1: 0]
B [m–1:0] m C [m–1:0] 2 m
1 m
m D [m–1:0] 3
m
S
S1S0

2-to-1 Multiplexer with m bits 4-to-1 Multiplexer with m bits

Inputs and output are m-bit vectors Inputs and output are m-bit vectors
Using m copies of a 2-to-1 Mux Using m copies of a 4-to-1 Mux
Implementing a Function with a Multiplexer
❖ A Multiplexer can be used to implement any logic function
❖ The function must be expressed using its minterms
❖ Example: Implement F(a, b, c) = ∑(1, 2, 6, 7) using a Mux
❖ Solution:
Inputs Output
0 0
a b c F
1 1
The inputs are 0 0 0 0
1 2

8-to-1 Mux
used as select 0 0 1 1
0 3
lines to a Mux.
0 1 0 1 F
0 1 1 0 0 4
An 8-to-1 1 0 0 0 0 5
Mux is used 1 0 1 0 1 6

because there 1 1 0 1 1 7 1
0
2
1 1 1 1
are 3 variables
S2 S1 S0 = a b c
 Better Solution with a Smaller Multiplexer
❖ Re-implement F(a, b, c) = ∑(1, 2, 6, 7) using a 4-to-1 Mux
❖ We will use the two select lines for variables a and b
❖ Variable c and its complement are used as inputs to the Mux

Inputs Output Comment

a b c F F
0 0 0 0
F=c c 0
0 0 1 1

4-to-1 Mux
0 1 0 1
F = c' c' 1
0 1 1 0 F
1 0 0 0 0 2
F=0
1 0 1 0
1 1 0 1 1 3 1 0
F=1
1 1 1 1
S1 S0 = a b
 Implementing Functions: Example 2
Implement F(a, b, c, d) = ∑(1,3,4,11,12,13,14,15) using 8-to-1 Mux
Inputs Output Comment
a b c d F F
0 0 0 0 0 d 0
0 0 0 1 1
F=d
0 0 1 0 0 1
0 0 1 1 1
F=d
2

8-to-1 Mux
0 1 0 0 1
0 1 0 1 0
F = d'
0 3
0 1 1 0 0 F
0 1 1 1 0
F=0 4
1 0 0 0 0 5
1 0 0 1 0
F=0
1 0 1 0 0 1 6
1 0 1 1 1
F=d
0
1 1 0 0 1
72 1

1 1 0 1 1
F=1
1 1 1 0 1
F=1 S2 S1 S0 = a b c
1 1 1 1 1
 Next . . .

❖ Decoders

❖ Multiplexers

❖ Design Example And Assignment

 2-by-2 Crossbar Switch
❖ A 2×2 crossbar switch is a combinational circuit that has:
Two m-bit Inputs: A and B
if (S == 0) { X = A; Y = B; }
Two m-bit outputs: X and Y
else { X = B; Y = A; }
1-bit select input S
❖ Implement the 2×2 crossbar switch using multiplexers
❖ Solution: Two 2-input multiplexers are used

m m A[m–1:0] 0 m

Mux
A[m-1:0] X [m-1:0] m X [m-1:0]
2×2 1
B[m–1:0]
Crossbar m
m m S
B[m-1:0] Switch Y [m-1:0]
0 m

Mux
Y [m-1:0]
1
S
BINARY CODED HEXADECIMAL 7 SEGMENT
DECODER
Truth Table
Specification:
BCD input 7-Segment Output
 Input: 4-bit BCD (I3, I2, I1, I0) I3 I2 I1 I0 a b c d e f g
 Output: 7-bit (a, b, c, d, e, f, g) 0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
 1. Use a 4 to 16 Decoder to implement
0 0 1 0 1 1 0 1 1 0 1
a Hexadecimal Display Decoder that
0 0 1 1 1 1 1 1 0 0 1
will display the letters A b C d E F for 0 1 0 0 0 1 1 0 0 1 1
non-BCD 0 1 0 1 1 0 1 1 0 1 1
 2. Using basic logic gates implement 0 1 1 0 1 0 1 1 1 1 1

the BCD decoder for the given truth 0 1 1 1 1 1 1 0 0 0 0

1 0 0 0 1 1 1 1 1 1 1
table. X – represent don’t care
1 0 0 1 1 1 1 1 0 1 1
condition.
1010 to 1111 X X X X X X X
 Due date: October 21st 2024