UNIT: MICROPROCESSOR SYSTEMS

TOPIC 4: INTERRUPTS

INTRODUCTION
In the context of the 8085 microprocessor, an interrupt is a signal or event that halts the normal program execution
and directs the processor to temporarily stop its current activities to attend to a specific task or event that requires
immediate attention. When an interrupt occurs, the processor saves the current state of the program being executed,
transfers control to a specific interrupt service routine (ISR), and after completing the ISR, resumes the normal
program execution.

THE NEEDS FOR AN INTERRUPTS IN MICROPROCESSOR

Interrupts play a vital role in the operation of a microprocessor-based system by fulfilling various needs and
enhancing the efficiency of the system. Here are some key needs for interrupts in a microprocessor:

Efficient Handling of External Events:

 Real-Time Response: Interrupts allow the microprocessor to respond promptly to external events or signals
from devices without delaying critical operations.
 Priority Handling: By assigning different priorities to interrupts, the system can manage and prioritize tasks
based on their importance.
Multitasking and Task Switching:
 Concurrency: Interrupts enable the microprocessor to handle multiple tasks concurrently by switching
between different tasks based on interrupt requests.
 Context Switching: The ability to save and restore the state of the processor allows for seamless switching
between tasks.
Input/Output Operations:
 I/O Operations: Interrupts are essential for managing input/output operations efficiently, allowing the
processor to communicate with external devices and handle data transfer.
 Asynchronous Operations: By using interrupts, the processor can handle asynchronous events from
external devices without waiting for synchronous responses.
Time-Critical Operations:
 Real-Time Systems: Interrupts are crucial for real-time systems where timely responses to events are
essential, such as in embedded systems, control systems, and communication systems.
 Synchronization: Interrupts help synchronize the operation of the microprocessor with external events or
devices, ensuring accurate timing and coordination.
Error Handling and Exception Handling:
 Error Detection: Interrupts can be used to detect and handle errors or exceptional conditions that may occur
during program execution.
 Fault Tolerance: By using interrupts for error handling, the system can recover from faults or unexpected
events gracefully.
Power Management and Energy Efficiency:
 Power Saving: Interrupts can be used to wake the processor from low-power states or sleep modes only
when necessary, conserving energy and extending battery life in portable devices.
 Dynamic Power Management: Interrupts facilitate dynamic power management by allowing the processor
to adjust its performance based on workload and external events.
By addressing these needs, interrupts enhance the responsiveness, scalability, reliability, and performance
of microprocessor-based systems, enabling them to handle a diverse range of tasks efficiently and effectively.

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TOPIC 4: INTERRUPTS

MICROPROCESSOR 8085 INTERRUPT PINS

In the 8085 microprocessor, an interrupt is a signal that temporarily suspends the normal execution of a program and
redirects the control to a specific interrupt service routine (ISR). Interrupts allow the microprocessor to respond to
external events, such as user input, system events, or hardware signals, without the need for constant polling.

There are five interrupt signals in the 8085 microprocessor:

1. TRAP: The TRAP interrupt is a non-maskable interrupt that is generated by an external device, such as a
power failure or a hardware malfunction. The TRAP interrupt has the highest priority and cannot be
disabled.
2. RST 7.5: The RST 7.5 interrupt is a maskable interrupt that is generated by a software instruction. It has the
second highest priority.
3. RST 6.5: The RST 6.5 interrupt is a maskable interrupt that is generated by a software instruction. It has the
third highest priority.
4. RST 5.5: The RST 5.5 interrupt is a maskable interrupt that is generated by a software instruction. It has the
fourth highest priority.
5. INTR: The INTR interrupt is a maskable interrupt that is generated by an external device, such as a
keyboard or a mouse. It has the lowest priority and can be disabled.

When microprocessor receives any interrupt signal from peripheral(s) which are requesting its services, it stops its
current execution and program control is transferred to a sub-routine by generating CALL signal and after executing
sub-routine by generating RET signal again program control is transferred to main program from where it had
stopped. When microprocessor receives interrupt signals, it sends an acknowledgement (INTA) to the peripheral
which is requesting for its service.

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THE CLASSIFICATIONS OF MICROPROCESSOR 8085 INTERRUPTS

In the 8085 microprocessor, interrupts can be classified based on various criteria such as their nature, priority, and
source. Here are the classifications of interrupts in the 8085 microprocessor:
Based on Nature:
1. Maskable Interrupts:
o Interrupts that can be enabled or disabled by the programmer.
o The response to these interrupts can be controlled based on the priority of the interrupt sources.
o Examples include RST 7.5, RST 6.5, RST 5.5, RST 4.5, and TRAP.
2. Non-Maskable Interrupt (NMI):
o An interrupt that cannot be disabled by the programmer.
o It has the highest priority and is used for critical tasks.
o In the 8085 microprocessor, the TRAP interrupt is a non-maskable interrupt.
Based on Priority:
1. Priority Interrupts:
o Interrupts that are assigned different priorities.
o The microprocessor services the interrupt with the highest priority first.
o Helps in managing critical tasks effectively.
Based on Source:
1. Hardware Interrupts:
o Interrupts generated by external hardware devices connected to the microprocessor.
o Examples include interrupt requests from input/output devices.
2. Software Interrupts:
o Interrupts initiated by specific instructions in the program.
o The 8085 microprocessor uses software interrupts through the RST (Restart) instructions.
Based on Specific Functionality:
1. RST Interrupts:
o Special restart interrupts (RST 7.5, RST 6.5, RST 5.5, RST 4.5) that provide fixed vector addresses
to jump to specific memory locations.
o Used for handling specific tasks or subroutines.
2. TRAP Interrupt:
o A specific interrupt that is non-maskable and has the highest priority in the 8085 microprocessor.
o Used for critical tasks that require immediate attention.
Based on Usage:
1. External Interrupts:
o Interrupts generated externally by peripheral devices.
o Handled by the microprocessor to respond to events from external sources.
2. Internal Interrupts:
o Interrupts generated internally within the microprocessor.
o Used for specific operations or exceptional conditions within the processor.
Understanding the classifications of interrupts in the 8085 microprocessor helps programmers and system designers
effectively manage interrupt handling, prioritize tasks, and ensure the smooth operation of the system in response to
external events and internal conditions.

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The types of 8085 microprocessors and interrupt handling

In the 8085 microprocessors and interrupt handling, two common types of interrupts are vectored interrupts and non-
vectored interrupts. Here is an explanation of both types:
1) Vectored Interrupts:
 Definition: In a vectored interrupt system, when an interrupt request occurs, the interrupting device directly
sends a vector address to the processor.
 Vector Address: The vector address points to the memory location where the interrupt service routine (ISR)
for that specific interrupt is located.
 Handling Process:
o The processor uses the vector address to locate the starting address of the ISR in the interrupt vector
table.
o The processor then branches to the ISR to handle the interrupt.
 Advantages:
o Efficiency: Faster response time as the processor directly jumps to the ISR without searching for the
service routine.
o Priority Handling: Allows for easy implementation of priority levels for different interrupts.
 Example: The Intel 8085 microprocessor uses vectored interrupts for interrupts like RST 7.5, RST 6.5, RST
5.5, RST 4.5, and TRAP.
2) Non-Vectored Interrupts:
 Definition: In a non-vectored interrupt system, when an interrupt request occurs, the processor starts
executing a fixed routine to identify and handle the interrupt source.
 No Specific Address: The processor does not receive a specific vector address for the interrupting device.
 Handling Process:
o The processor sequentially checks each interrupt source to identify the source of the interrupt.
o Once identified, the processor jumps to a fixed memory location where the ISR for that interrupt
source resides.
 Advantages:
o Simplicity: Easier to implement compared to vectored interrupts.
o Less Overhead: Requires less memory for the interrupt vector table.
 Example: The Intel 8085 microprocessor uses non-vectored interrupts for the TRAP interrupt.
Key Differences:
 Identification Process:
o Vectored: Directly identifies the ISR using a vector address.
o Non-Vectored: Sequentially identifies the interrupt source and then jumps to the corresponding
ISR.
 Response Time:
o Vectored: Faster response time due to direct addressing.
o Non-Vectored: Slightly slower response time as it involves an identification process.
 Implementation Complexity:
o Vectored: Requires interrupt vector table and handling logic.
o Non-Vectored: Simple to implement as it follows a fixed routine for all interrupts.
Understanding the differences between vectored and non-vectored interrupts helps in designing efficient interrupt
handling mechanisms based on the specific requirements of a microprocessor system.

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INTERRUPT HANDLING PROCESS/OPERATION:

1. Interrupt Request (IRQ):

o When an interrupting device requests the processor's attention, it sends an interrupt request signal to
the microprocessor.
2. Interrupt Acknowledge:
o The processor acknowledges the interrupt request and suspends the current instruction execution.
3. Interrupt Vector Addressing:
o The interrupt vector address is used to locate the address of the interrupt service routine
corresponding to the specific interrupt source.
4. Save Current State:
o The processor saves the current program counter and status of the interrupted program before
transferring control to the ISR.
5. Execute Interrupt Service Routine:
o The ISR is executed to handle the specific interrupt request and perform the necessary operations.
6. Return from Interrupt:
o After completing the ISR, the processor restores the saved state, including the program counter, and
resumes the main program execution.
Interrupts play a crucial role in managing real-time events, prioritizing tasks, and handling external devices
efficiently in microprocessor-based systems like the 8085. By using interrupts, the processor can respond promptly
to critical events without relying solely on the sequential execution of instructions.

Terminologies
1) Interrupt Service Routine (ISR)
A small program or a routine that when executed, services the corresponding interrupting source is called an
ISR.
2) TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts. By default, it is enabled until it
gets acknowledged. In case of failure, it executes as ISR and sends the data to backup memory. This interrupt
transfers the control to the location 0024H.
3) RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts. When this interrupt is
executed, the processor saves the content of the PC register into the stack and branches to 003CH address.
4) RST 6.5
It is a maskable interrupt, having the third highest priority among all interrupts. When this interrupt is executed,
the processor saves the content of the PC register into the stack and branches to 0034H address.
5) RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor saves the content of the PC register into
the stack and branches to 002CH address.
6) INTR
It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by resetting the
microprocessor.
When INTR signal goes high, the following events can occur −
 The microprocessor checks the status of INTR signal during the execution of each instruction.
 When the INTR signal is high, then the microprocessor completes its current instruction and sends active
low interrupt acknowledge signal.

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 When instructions are received, then the microprocessor saves the address of the next instruction on stack
and executes the received instruction.

There are five interrupt signals in the 8085 microprocessor:

1. TRAP: The TRAP interrupt is a non-maskable interrupt that is generated by an external device, such as a
power failure or a hardware malfunction. The TRAP interrupt has the highest priority and cannot be
disabled.
2. RST 7.5: The RST 7.5 interrupt is a maskable interrupt that is generated by a software instruction. It has the
second highest priority.
3. RST 6.5: The RST 6.5 interrupt is a maskable interrupt that is generated by a software instruction. It has the
third highest priority.
4. RST 5.5: The RST 5.5 interrupt is a maskable interrupt that is generated by a software instruction. It has the
fourth highest priority.
5. INTR: The INTR interrupt is a maskable interrupt that is generated by an external device, such as a
keyboard or a mouse. It has the lowest priority and can be disabled.

When microprocessor receives any interrupt signal from peripheral(s) which are requesting its services, it stops its
current execution and program control is transferred to a sub-routine by generating CALL signal and after executing
sub-routine by generating RET signal again program control is transferred to main program from where it had
stopped. When microprocessor receives interrupt signals, it sends an acknowledgement (INTA) to the peripheral
which is requesting for its service.

Description of various Interrupts

1. Hardware and Software Interrupts – When microprocessors receive interrupt signals through pins
(hardware) of microprocessor, they are known as Hardware Interrupts. There are 5 Hardware Interrupts in
8085 microprocessor. They are – INTR, RST 7.5, RST 6.5, RST 5.5, TRAP Software Interrupts are those
which are inserted in between the program which means these are mnemonics of microprocessor. There are
8 software interrupts in 8085 microprocessor. They are – RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6,
RST 7.
2. Vectored and Non-Vectored Interrupts – Vectored Interrupts are those which have fixed vector address
(starting address of sub-routine) and after executing these, program control is transferred to that address.
Vector Addresses are calculated by the formula 8 * TYPE

INTERRUPT VECTOR ADDRESS

TRAP (RST 4.5) 24 H
RST 5.5 2C H
RST 6.5 34 H
RST 7.5 3C H

1. For Software interrupts vector addresses are given by:

INTERRUPT VECTOR ADDRESS
RST 0 00 H
RST 1 08 H
RST 2 10 H
RST 3 18 H
RST 4 20 H

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RST 5 28 H
RST 6 30 H
RST 7 38 H

1. Non-Vectored Interrupts are those in which vector address is not predefined. The interrupting device gives
the address of sub-routine for these interrupts. INTR is the only non-vectored interrupt in 8085
microprocessor.
2. Maskable and Non-Maskable Interrupts – Maskable Interrupts are those which can be disabled or
ignored by the microprocessor. These interrupts are either edge-triggered or level-triggered, so they can be
disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts in 8085 microprocessor. Non-Maskable
Interrupts are those which cannot be disabled or ignored by microprocessor. TRAP is a non-maskable
interrupt. It consists of both level as well as edge triggering and is used in critical power failure conditions.

Priority of Interrupts – When microprocessor receives multiple interrupt requests simultaneously, it will execute
the interrupt service request (ISR) according to the priority of the interrupts.

Instruction for Interrupts –

1. Enable Interrupt (EI) – The interrupt enable flip-flop is set and all interrupts are enabled following the
execution of next instruction followed by EI. No flags are affected. After a system reset, the interrupt enable
flip-flop is reset, thus disabling the interrupts. This instruction is necessary to enable the interrupts again
(except TRAP).

2. Disable Interrupt (DI) – This instruction is used to reset the value of enable flip-flop hence disabling all the
interrupts. No flags are affected by this instruction.

3. Set Interrupt Mask (SIM) – It is used to implement the hardware interrupts (RST 7.5, RST 6.5, RST 5.5)
by setting various bits to form masks or generate output data via the Serial Output Data (SOD) line. First the

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required value is loaded in accumulator then SIM will take the bit pattern from it.

4. Read Interrupt Mask (RIM) – This instruction is used to read the status of the hardware interrupts (RST
7.5, RST 6.5, RST 5.5) by loading into the A register a byte which defines the condition of the mask bits for
the interrupts. It also reads the condition of SID (Serial Input Data) bit on the microprocessor.

Uses of Interrupts in 8085 microprocessor:

1) Interrupts in the 8085 microprocessor are used for various purposes, including:
2) Real-time processing: Interrupts allow the microprocessor to respond quickly to external events in real-time,
such as user input or hardware signals. This is particularly useful in applications such as control systems and
data acquisition systems where time-critical operations are required.

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3) Multi-tasking: Interrupts enable the microprocessor to perform multiple tasks simultaneously by temporarily
suspending the current task and executing the ISR for the interrupting event. This allows the microprocessor
to switch between different tasks and maximize the utilization of system resources.
4) Input/output operations: Interrupts can be used for handling input/output operations, such as data transfer
between the microprocessor and external devices. This allows the microprocessor to perform other tasks
while waiting for input/output operations to complete.
5) Error handling: Interrupts can be used for error handling and exception handling, such as detecting and
recovering from hardware or software errors.
6) Power management: Interrupts can be used for power management, such as putting the microprocessor into
a low-power mode when it is not needed and waking it up when an interrupt occurs.

Issues of Interrupts in 8085 microprocessor:

There are several issues that need to be considered when using interrupts in the 8085 microprocessor:

1. Priority conflicts: The 8085 microprocessor supports multiple interrupt signals with different priorities. If
multiple interrupts occur simultaneously, it can lead to priority conflicts and result in incorrect operation or
system failure. Therefore, the priority levels of each interrupt signal need to be carefully designed and tested
to avoid conflicts.

2. Race conditions: Race conditions can occur when multiple processes try to access the same resources, such
as registers or memory locations, simultaneously. This can lead to incorrect results or system failure.
Therefore, interrupt handlers need to be carefully designed to avoid race conditions, such as by disabling
interrupts during critical operations.

3. Interrupt latency: Interrupt latency is the time delay between when an interrupt occurs and when the
corresponding ISR starts executing. Interrupt latency can affect the system’s responsiveness and real-time
performance. Therefore, interrupt handlers need to be designed to minimize interrupt latency, such as by
using fast interrupt service routines and optimizing the interrupt handling process.

4. Interrupt nesting: Interrupt nesting occurs when an interrupt occurs while the microprocessor is executing
an ISR for another interrupt. Interrupt nesting can lead to complex interrupt handling and priority conflicts.
Therefore, interrupt handlers need to be carefully designed to avoid interrupt nesting, such as by disabling
lower-priority interrupts during critical operations.

5. Interrupt overhead: Interrupt overhead is the additional processing time and resources required to handle
interrupts. Interrupt overhead can affect the system’s performance and efficiency, especially if the system
experiences a high volume of interrupts. Therefore, interrupt handlers need to be designed to minimize
interrupt overhead, such as by optimizing the interrupt handling process and reducing unnecessary
operations.

Methods of Handling Microprocessor Interrupts

In the Intel 8085 microprocessor, various mechanisms are used to handle interrupts efficiently. Let's discuss the
following mechanisms in detail:

1. Software Polling:

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 Definition: Software polling refers to the technique where the microprocessor continuously checks the status
of an interrupt source through software instructions.
 Process: The processor uses looping constructs to check the status of the interrupt source at regular
intervals.
 Efficiency: Software polling can be resource-intensive as it requires constant monitoring by the processor.
 Suitability: Suitable for low-priority or less time-sensitive interrupt sources where immediate response is
not critical.

2. Hardware Polling:
 Definition: Hardware polling involves the use of external hardware components to detect and
handle interrupts.
 Process: External hardware circuits monitor the status of interrupt sources and inform the processor when an
interrupt occurs.
 Efficiency: Hardware polling reduces the burden on the processor by offloading interrupt detection to
dedicated hardware.
 Response Time: Offers faster response times compared to software polling due to dedicated hardware
monitoring.

3. Hardware Identification - Vectored Interrupt:

 Vectored Interrupts: In the vectored interrupt mechanism, the interrupting device provides a specific
vector address to the processor during the interrupt acknowledge cycle.
 Identification: Each interrupt source is associated with a unique vector address that points to the memory
location of its Interrupt Service Routine (ISR).
 Efficiency: Vectored interrupts streamline the interrupt handling process by directly identifying the ISR
without the need for additional lookup.
 Priority Handling: Enables efficient handling of multiple interrupt sources with varying priorities.

4. Comparison:
 Software vs. Hardware Polling:
o Software Polling:
 Relies on software instructions for interrupt detection.
 Processor-intensive and may lead to delays in response.
o Hardware Polling:
 Uses dedicated hardware for interrupt detection.
 Offers faster response times and reduces processor overhead.

 Hardware Polling vs. Vectored Interrupt:

o Hardware Polling:
 Relies on external hardware components for interrupt detection.
 Efficient but may require additional hardware circuits.
o Vectored Interrupt:
 Uses vector addresses to directly identify the ISR.
 Simplifies interrupt handling and improves response time.

By understanding and effectively utilizing these interrupt mechanisms, programmers and system designers can
optimize interrupt handling in the Intel 8085 microprocessor, ensuring efficient response to external events while
maintaining system performance and reliability.
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Definition of interrupt:
Interrupt is a mechanism by which an I/O or an instruction can suspend the normal execution of processor and get
itself serviced. Generally, a particular task is assigned to that interrupt signal. In the microprocessor-based system
the interrupts are used for data transfer between the peripheral devices and the microprocessor. In simple words,
Interrupt may be said as
 The process starts from the I/O device
 The process is asynchronous.
 An interrupt is considered to be an emergency signal that may be serviced.
 The Microprocessor may respond to it as soon as possible.

Interrupt in the 8085 micro-processor:

When microprocessor receives any interrupt signal from peripheral(s) which are requesting its services, it stops its
current execution and program control is transferred to a sub-routine by generating CALL signal and after executing
sub-routine by generating RET signal again program control is transferred to main program from where it had
stopped.
When microprocessor receives interrupt signals, it sends an acknowledgement (INTA) to the peripheral which is
requesting for its service.

Changes when micro-processor is interrupted:

When the Microprocessor receives an interrupt signal, it suspends the currently executing program and jumps to an
Interrupt Service Routine (ISR) to respond to the incoming interrupt. Each interrupt will most probably have its own
ISR.

What is interrupt service routine (ISR):

A small program or a routine that when executed services the corresponding interrupting source is called as an ISR.
Each interrupt will most probably have its own ISR.

Familiarization of interrupts in 8085:

Process of interrupts:
When the interrupt signal arrives:
 The processor will break its routine
 Go to a different routine (interrupt service routine)
 Complete the interrupt service routine (ISR)
 Go back to the “regular” routine in order to execute an interrupt routine, the processor:
 Should be able to accept interrupts (interrupt enable)
 Save the last content of the program counter
 Know where to go in program memory to execute the ISR
 Tell the outside world that it is executing an interrupt
 Go back to the saved PC location when finished.
 Interrupts increase processor system efficiency by letting I/O device request CPU Time only when that
device needs immediate attention.
 An interrupt is a subroutine call initialized by external hardware.
 The request is asynchronous
 It may occur at any point in a program’s execution.

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Diagram:

Fig 1: interrupt in 8085

Classification of interrupts:

Hardware and software interrupts: –

 When microprocessors receive interrupt signals through pins (hardware) of microprocessor, they are known
as Hardware Interrupts.
 There are 5 Hardware Interrupts in 8085 microprocessor. They are — INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP
 Software Interrupts are those which are inserted in between the program which means these are mnemonics
of microprocessor. There are 8 software interrupts in 8085 microprocessor.
 They are–RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.

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FIG 2 : classification of interrupts

Interrupts can be classified into two types:
 Maskable Interrupts (Can be delayed or rejected)
 Non-Maskable Interrupts (Cannot be delayed or rejected)
Interrupts can also be classified into:
 Vectored (the address of the service routine is hard-wired)
 Non-vectored (the address of the service routine needs to be supplied externally by the device)

Maskable and non-maskable interrupts:

 Maskable Interrupts are those which can be disabled or ignored by the microprocessor.
 These interrupts are either edge-triggered or level-triggered, so they can be disabled. INTR, RST 7.5, RST
6.5, RST 5.5 are maskable interrupts in 8085 microprocessor.

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Fig 4 : representation of maskable and non-maskable interrupt

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Fig 5: maskable interrupts

Non-Maskable Interrupts are those which cannot be disabled or ignored by microprocessor. TRAP is a non-maskable
interrupt. It consists of both level as well as edge triggering and is used in critical power failure conditions.
 MP completes its current machine cycle.
 There are two ways of redirecting the execution to the ISR depending on whether the interrupt is vectored or
non-vectored.
Vectored and non-vectored interrupts:
Vectored Interrupts are those which have fixed vector address (starting address of sub-routine) and after executing
these, program control is transferred to that address.
Vector Addresses are calculated by the formula 8 * TYPE

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Fig 6: vectored interrupt

Non-Vectored Interrupts are those in which vector address is not predefined. The interrupting device gives the
address of sub-routine for these interrupts. INTR is the only non-vectored interrupt in 8085 microprocessor.

Response to interrupt:

8085 interrupt structure:

There are 5 interrupt inputs:
 TRAP (non-maskable)
 RST7.5
 RST6.5
 INTR
 RST 5.5

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Fig 7: interrupt structure of 8085

Response to interrupt:
 Responding to an interrupt may be immediate or delayed depending on whether the interrupt is maskable or non-
maskable and whether interrupts are being masked or not.
 MP completes its current machine cycle.
 There are two ways of redirecting the execution to the ISR depending on whether the interrupt is vectored or
non-vectored.
Process:
1) The processing of the current instruction is completed.
2) An interrupt machine cycle is executed during which the PC is saved and control is
3) transferred to an appropriate memory location.
4) The state of the MPU is saved.
5) If more than one I/O device is associated with the location transferred to, the highest priority device requesting
an interrupt is identified.
6) A subroutine is executed which services the interrupt I/O device.
7) The saved state of the microprocessor is restored.
8) Control is returned to the instruction that follows the interrupted instruction.

Instruction for interrupts –

Enable interrupt (EI):

The interrupt enable flip-flop is set and all interrupts are enabled following the execution of next instruction
followed by EI. No flags are affected. After a system reset, the interrupt enable flip-flop is reset, thus disabling the
interrupts. This instruction is necessary to enable the interrupts again (except TRAP).

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Disable interrupt (DI):

This instruction is used to reset the value of enable flip-flop hence disabling all the interrupts. No flags are affected
by this instruction

SIM instruction:
It is used to implement the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by setting various bits to form masks or
generate output data via the Serial Output Data (SOD) line. First the required value is loaded in accumulator then
SIM will take the bit pattern from it.

Fig 8: format of 8-bit data to be loaded in accumulator

 Bit 0 is the mask for RST 5.5, bit 1 is the mask for RST 6.5 and bit 2 is the mask for RST 7.5.
 If the mask bit is 0, the interrupt is available.
 If the mask bit is 1, the interrupt is masked.
 Bit 3 (Mask Set Enable — MSE) is an enable for setting the mask.
 If it is set to 0 the mask is ignored and the old settings remain.
 If it is set to 1, the new setting are applied.
 Bit 4 of the accumulator in the SIM instruction allows explicitly resetting the RST 7.5 memory even if the
microprocessor did not respond to it.
 Bit 5 is not used by the SIM instruction
 Bit 6 & Bit 7 is used for extra functionality such as serial data transmission.
 Example: Set the interrupt masks so that RST5.5 is enabled, RST6.5 is masked, and RST7.5 is enabled.
 First, determine the contents of the accumulator.

Example:
 Set the interrupt masks so that RST 5.5 is enabled, RST 6.5 is masked and RST 7.5 is enabled.
 First, determine the contents of the accumulator.
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 Enable 5.5 bit 0=0

 Disable 6.5 bit 1=1
 Enable 7.5 bit 2=0
 Allow setting the masks bit 3=1
 Don’t reset the flip-flop bit 4=0
 Bit 5 is not used bit 5=0
 Don’t use serial data bit 6=0
 Serial data is ignored bit 7=0
 EI; Enable interrupts including INTR
 MVI A, OA; Prepare the mask to enable RST 7.5 and 5.5, disable 6.5
 SIM; Apply the setting RST masks

Read interrupt mask (RIM):

This instruction is used to read the status of the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by loading into the
A register a byte which defines the condition of the mask bits for the interrupts. It also reads the condition of SID
(Serial Input Data) bit on the microprocessor showing the status of each interrupt pin and mask.

 Load the accumulator with an 8-bit pattern

Fig 9: pin configuration of interrupt

Bits 0–2 show the current setting of the mask for each of RST 7.5, RST 6.5 and RST 5.5. They return the contents of
the three mask flip flops.
 Bit 3 shows whether the maskable interrupt process is enabled or not.
 It can be used by a program to determine whether or not interrupts are enabled.
 Bits 4–6 show whether or not there are pending interrupts on RST 7.5, RST 6.5, and RST 5.5.
 Bit 7 is used for Serial Data Input.

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The RIM instruction reads the value of the SID pin on the microprocessor and returns it in this bit.
 Microprocessor can be interrupted again before the completion of the ISR.
 As soon as the 1st interrupt arrives, all maskable interrupts are disabled.
 They will only be enabled after the execution of the EI instruction.
If the EI instruction is placed early in the ISR, other interrupt may occur before the ISR is done.

WORKING PRINCIPLES OF INTERRUPTS -

There are 6 pins available in 8085 for interrupt:

1) TRAP
2) RST 7.5
3) RST6.5
4) RST5.5
5) INTR
6) INTA

Execution of interrupts:
When there is an interrupt requests to the Microprocessor then after accepting the interrupts Microprocessor send the
INTA (active low) signal to the peripheral. The vectored address of particular interrupt is stored in program counter.
The processor executes an interrupt service routine (ISR) addressed in program counter. There are two types of
interrupts used in 8085 Microprocessor:
1) Hardware Interrupts,
2) Software Interrupts

Hardware interrupt:
As I have already discussed that there are 6 interrupt pins in the microprocessor used as Hardware Interrupts given
below:
1) TRAP
2) RST7.5
3) RST6.5
4) RST5.5
5) INTR

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Software interrupts:
A software interrupts is a particular instructions that can be inserted into the desired location in the program. There
are eight Software interrupts in 8085 Microprocessor from RST 0 to RST 7.
RST0
RST1
RST2
RST3
RST4
RST5
RST6
RST7
They allow the microprocessor to transfer program control from the main program to the subroutine program. After
completing the subroutine program, the program control returns back to the main program.
We can calculate the vector address of these interrupts using the formula given below:
Vector Address = Interrupt Number × 8
For Example:
 RST2: vector address=2×8 = 16
 RST1: vector address=1×8 = 08
 RST3: vector address=3×8 = 24

Non-vectored interrupt:
1) The interrupt process should be enabled using the EI instruction.
2) The 8085 checks for an interrupt during the execution of every instruction.
3) If INTR is high, MP completes current instruction, disables the interrupt and sends INTA(Interrupt
acknowledge) signal to the device that interrupted .
4) INTA allows the I/O device to send a RST instruction through data bus.

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5) Upon receiving the INTA signal, MP saves the memory location of the next instruction on the stack and the
program is transferred to ‘call’ location (ISR Call) specified by the RST instruction.
6) Microprocessor Performs the ISR.
7) ISR must include the ‘EI’ instruction to enable the further interrupt within the program.
8) RET instruction at the end of the ISR allows the MP to retrieve the return address from the stack and the
program is transferred back to where the program was interrupted.
9) Although INTR is a maskable interrupt, it does NOT need SIM to get enabled.
Just instruction EI is enough.
The 8085 recognizes 8 RESTART instructions: RST0 — RST7.

VECTORED INTERRUPTS:

TRAP:
 It is non maskable edge and level triggered interrupt. TRAP has the highest priority and vectors interrupt.
 Edge and level triggered means that the TRAP must go high and remain high until it is acknowledged.
 In case of sudden power failure, it executes a ISR and send the data from main memory to backup memory.
 As we know that TRAP can’t be masked but it can be delayed using HOLD signal.
 This interrupt transfers the microprocessor’s control to location 0024H. Trap Interrupt can also be masked
by resetting the microprocessor. There is no other way to mask it.

TRIGGERING LEVELS:
 RST 7.5 is positive edge sensitive.
 When a positive edge appears on the RST7.5 line, a logic 1 is stored in the flip-flop as a “pending” interrupt.
 Since the value has been stored in the flip flop, the line does not have to be high when the microprocessor
checks for the interrupt to be recognized.
 The line must go to zero and back to one before a new interrupt is recognized.
 RST 6.5 and RST 5.5 are level sensitive.
 The interrupting signal must remain present until the microprocessor checks for interrupts.

 TRAP is the only non-maskable interrupt.

 It does not need to be enabled because it cannot be disabled.
 It has the highest priority amongst interrupts.
 It is edge and level sensitive.
 Must make a low-to-high transition and remain high to be acknowledged.
 After acknowledgement, it is NOT recognized again until it goes low, then high again and remains high.
 It is to avoid false triggering due to noise/logic glitches.
 TRAP is usually used for power failure and emergency shutoff.

When the 8085A is reset:

Its internal interrupt enable flip-flop is reset. This disables ALL the maskable interrupts. So, the MPU only responds
to TRAP. Vectored address for TRAP is 0024 H.

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Fig 12: priority of interrupt

RESTART AS SOFTWARE INTERRUPT:

Restart sequence:
 The restart sequence is made up of three machine cycles
 In the 1st machine cycle: The Microprocessor sends the INTA signal.
 While INTA is active the microprocessor reads the data lines expecting to receive, from the interrupting
device, the opcode for the specific RST instruction.
 In the 2nd and 3rd machine cycles: the 16-bit address of the next instruction is saved on the stack.
 Then the microprocessor jumps to the address associated with the specified RST instruction.
 There are 8 different RST instructions.
 Each RST instruction tells the processor to go to a specific memory address (call location — fixed).

Reading the RST 5 instruction:

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The above example is for generating RST 5:

RST 5’s op code is EF =11101111

Hardware generation of RST opcode:

 During the interrupt acknowledge machine cycle, (the 1st machine cycle of the RST operation):
 The Microprocessor activates the INTA signal.
 This signal will enable the Tri-state buffers, which will place the value EFH on the data bus.
 Therefore, it is sending the Microprocessor the RST 5 instruction.
 The RST 5 instruction is exactly equivalent to CALL 0028H

SOME IMPORTANT INTERRUPTS-

INTR interrupt:
 The microprocessor checks the INTR line one clock cycle before the last T-state of each instruction.
 The INTR line must be deactivated before the EI is executed. Otherwise, the microprocessor will be
interrupted again.
 Once the microprocessor starts to respond to an INTR interrupt, INTA becomes active (=0). Therefore,
INTR should be turned off as soon as the INTA signal is received. response to the acknowledge signal,
external logic places an instruction OPCODE on the data bus. In the case of multi byte instruction,
additional interrupt acknowledge machine cycles are generated by the 8085 to transfer the additional bytes
into the Microprocessor.
 On receiving the instruction, the 8085 save the address of next instruction on stack and execute received
instruction.
 The Programmable Interrupt Controller (PIC) functions as an overall manager in an Interrupt-Driven system
environment. It accepts requests from the peripheral equipment, determines which of the in-coming requests
is of the highest priority.
 The 8259A is a device specifically designed for use in real time, interrupt driven microcomputer systems.

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 It manages eight levels or requests and has built in features for expandability to other 8259A’s (up to 64
levels). It is programmed by the system’s software as an I/O peripheral.
 Each peripheral device usually has a special program or ``routine’’ that is associated with its specific
functional or operational requirements; this is referred to as a ``service routine’’.
 The PIC, after issuing an Interrupt to the CPU, must somehow input information into the CPU that can
``point’’ the Program Counter to the service routine associated with the requesting device. This ``pointer’’ is
an address in a vectoring table and will often be referred to, in this document, as vectoring data.

 Since the 8085 has five interrupt lines, interrupts may occur during an ISR and remain pending.
 Using the RIM instruction, it is possible to read the status of the interrupt lines and find if there are any pending
interrupts.

Pending interrupts:
Since the 8085 has 5 interrupt lines, interrupts may occur during an ISR and remain pending. Using the rim
instruction, it is possible to read the status of the interrupt lines and find if there are any pending interrupts.

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Multiple interrupts:

 There are 8 different RST Instructions.

 How do MPU allow multiple devices to interrupt using the INTR line?
 The microprocessor can only respond to one signal on INTR at a time.
 Therefore, we must allow the signal from only one of the devices to reach the microprocessor.
 We must assign some priority to the different devices and allow their signals to reach the microprocessor
according to the priority.
 The solution is to use a circuit called the priority encoder as opcodes for the different RST instructions
follow a set pattern.
 When microprocessor receives multiple interrupt requests simultaneously, it will execute the interrupt
service request (ISR) according to the priority of the interrupts.

MULTIPLE INTERRUPTS
If more than one device is connected to the interrupt line, the processor needs to know to which device service
routine it should branch to. The identification of the device requesting service can be done in either hardware or
software, or a combination of both. The three main methods are:
1. Software Polling,
2. Hardware Polling, (Daisy Chain),
3. Hardware Identification (Vectored Interrupts).

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1. Software Polling.
In this method, all interrupts are serviced by branching to the same service program. This program then checks
with each device if it is the one generating the interrupt. The order of checking is determined by the priority that
has to be set. The device having the highest priority is checked first and then devices are checked in descending
order of priority. If the device is checked to be generating the interrupt, another service program is called which
works specifically for that particular device.
A software routine is used to identify the device requesting service. A simple polling technique is used, each
device is checked to see if it was the one needing service.

Having identified the device, the processor then branches to the appropriate interrupt-handling-routine address
for the given device. The order in which the devices appear in the polling sequence determines their priority.
The structure will look something like this-
if (device[0].flag)
device[0].service();
else if (device[1].flag)
device[1].service();
.
.
.
else
//raise error

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Summary of Software Polled I/O

Polling is the most common and simplest method of I/O control. It requires no special hardware and all I/O
transfers are controlled by the CPU programme. Polling is a synchronous mechanism, by which devices are
serviced in sequential order.
The polling technique, however, has limitations.
1) it is wasteful of the processors time, as it needlessly checks the status of all devices all the time,
2) it is inherently slow, as it checks the status of all I/O devices before it comes back to check any given
once again,
3) when fast devices are connected to a system, polling may simply not be fast enough to satisfy the
minimum service requirements,
4) priority of the device is determined by the order in the polling loop, but it is possible to change it via
software.

2. Hardware Polling (Daisy Chain)

The daisy-chaining method involves connecting all the devices that can request an interrupt in a serial manner.
This configuration is governed by the priority of the devices. The device with the highest priority is placed first
followed by the second highest priority device and so on. The given figure depicts this arrangement.

Working/Operation:
There is an interrupt request line which is common to all the devices and goes into the CPU.
 When no interrupts are pending, the line is in HIGH state. But if any of the devices raises an interrupt, it
places the interrupt request line in the LOW state.
 The CPU acknowledges this interrupt request from the line and then enables the interrupt acknowledge line
in response to the request.
 This signal is received at the PI (Priority in) input of device 1.
 If the device has not requested the interrupt, it passes this signal to the next device through its PO (priority
out) output. (PI = 1 & PO = 1)
 However, if the device had requested the interrupt, (PI =1 & PO = 0)
 The device consumes the acknowledge signal and block its further use by placing 0 at its PO
(priority out) output.
 The device then proceeds to place its interrupt vector address (VAD) into the data bus of CPU.

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 The device puts its interrupt request signal in HIGH state to indicate its interrupt has been taken care
of.
 If a device gets 0 at its PI input, it generates 0 at the PO output to tell other devices that acknowledge signal
has been blocked. (PI = 0 & PO = 0)
Hence, the device having PI = 1 and PO = 0 is the highest priority device that is requesting an interrupt.
Therefore, by daisy chain arrangement we have ensured that the highest priority interrupt gets serviced first and
have established a hierarchy. The farther a device is from the first device, the lower its priority.

3. Hardware Identification (Vectored Interrupts)

This is the fastest system. The onus is placed on the requesting device to request the interrupt, and identify itself.
The identity could be a branching address for the desired interrupt-handling routine.
If the device just supplies an identification number, this can be used in conjunction with a lookup table to
determine the address of the required service routine. Response time is best when the device requesting service
also supplies a branching address.

Priority interrupts:
Advantages:
1. Priority interrupts allow for the efficient handling of high-priority tasks that require immediate attention.
This is especially important in real-time systems where certain tasks must be completed within strict time

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constraints.

2. They are more efficient than software polling as the processor does not waste time constantly checking for
events that have not occurred.
3. Priority interrupts are also more deterministic, as the response time to an event can be accurately predicted
based on its priority level.

Disadvantages:
1. One potential disadvantage of priority interrupts is the possibility of lower priority tasks being starved of
resources if high-priority tasks are continuously interrupting the processor.
2. If not implemented properly, priority interrupts can lead to priority inversion, where a low-priority task
holds a resource required by a higher-priority task, causing a delay in the high-priority task’s execution.

Software polling:
Advantages:
1. Software polling is relatively simple to implement and does not require specialized hardware.
2. It can be used to detect events that occur at irregular intervals, as the processor can check for events
whenever it is not performing other tasks.

Disadvantages:
1. Software polling is less efficient than priority interrupts as the processor must constantly check for events
even if none have occurred.
2. In real-time systems, software polling may not be suitable as it is difficult to guarantee the response time to
an event, especially if the processor is busy with other tasks.

Daisy chaining:
Advantages:
1. Daisy chaining allows multiple devices to share a single interrupt line, reducing the number of interrupt lines
required.
2. It is relatively simple to implement and does not require specialized hardware.

Disadvantages:
1. Daisy chaining can result in increased response time as each device must wait for the previous device to
complete its interrupt handling before it can start its own.
2. It can also be difficult to implement and troubleshoot, especially if there are multiple devices on the same
interrupt line.

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