EXP.
NO : 1A DATE: 13/01/2025
REALIZATION OF COMBINATIONAL LOGIC CIRCUITS-I
AIM:
To write a Verilog code to implement the Half Adder, Half Subtractor, Full Adder,
and Full Subtractor using data flow modeling and verify the result in MODELSIM Software.
ALGORITHM:
1. Start the program.
2. Declare the module with input and output ports.
3. Use the Boolean expressions with continuous assign statements, design the Half
Adder, Half Subtractor, Full Adder, and Full Subtractor using data flow modeling.
4. End the module.
5. Compile and Simulate the design in MODELSIM Software and Verify
the functionality of the design.
PROGRAM:
i)HALF ADDER
module halfadder(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule
ii)HALF SUBTRACTOR
module halfsubtractor(a,b,diff,brw);
input a,b;
output diff, brw;
assign diff=a^b;
assign brw=(~a)&(b);
endmodule
iii)FULL ADDER
module fulladder(a,b,cin,sum,carry);
input a,b,cin;
output sum,carry;
assign sum=a^b^cin;
assign carry=(a&b)|(b&cin)|(cin&a);
endmodule
iv)FULL SUBTRACTOR
module fullsubtractor(a,b,bin,diff,bout);
input a,b,bin;
output diff,bout;
assign diff=a^b^bin;
assign bout=((~a)&b)|((~a)|b)&bin);
endmodule
SIMULATION OUTPUT:
i)HALF ADDER
ii)HALF SUBTRACTOR
iii)FULL ADDER
iv)FULL SUBTRACTOR
Prelab(10)
Demo (20)
Record(10)
Viva(10)
Total(50)
RESULT:
Thus, the VERILOG code for Half Adder, Half Subtractor, Full Adder, and Full
Subtractor were implemented in dataflow modeling and the functionality of the design was
verified in the MODELSIM software.
EXP. NO: 1B
DATE :18/01/2025
AIM:
To write a Verilog code to implement the Half Adder,Half Subtractor,Full
Adder,and Full Subtractor in behavioral modeling using if-else statements and case
statements and verify the result in MODELSIM software.
ALGORITHM:
1. Start the program.
2. Declare the module with input and output ports.
3. Using if-else statements and case statements design half adder, half
Subtractor, full adder, and full Subtractor in behavioral modeling.
4. End the module.
5. Compile and simulate the design in MODELSIM software and verify the
functionality of the design.
PROGRAM:
i)HALF ADDER USING IF-ELSE STATEMENT
module ha_ifelse(a,b,sum,carry);
input a,b;
output reg sum,carry;
always@(a or b)
begin
if(a==0 && b==0)
begin
sum=0;
carry=0;
end
else if(a==0 && b==1)
begin
sum=1;
carry=0;
end
else if(a==1 && b==0)
begin
sum=1;
carry=0;
end
else if(a==1 && b==1)
begin
sum=0;
carry=1;
end
end
endmodule.
ii)HALF SUBTRACTOR USING IF-ELSE STATEMENT
module hs_ifelse(a,b,diff,borr);
input a,b;
output reg diff,borr;
always@(a or b)
begin
if(a==0 && b==0)
begin
diff=0;
borr=0;
end
else if(a==0 && b==1)
begin
diff=1;
borr=1;
end
else if(a==1 && b==0)
begin
diff=1;
borr=0;
end
else if(a==1 && b==1)
begin
diff=0;
borr=0;
end
end
endmodule
iii)FULL ADDER USING IF-ELSE STATEMENT
module fa_ifelse(a,b,cin,sum,carry);
input a,b,cin;
output reg sum,carry;
always@(a or b or cin)
begin
if(a==0 && b==0 && cin==0)
begin
sum=0;
carry=0;
end
else if(a==0 && b==0 && cin==1)
begin
sum=1;
carry=0;
end
else if(a==0 && b==1 && cin==0)
begin
sum=1;
carry=0;
end
else if(a==0 && b==1 && cin==1)
begin
sum=0;
carry=1;
end
else if(a==1 && b==0 && cin==0)
begin
sum=1;
carry=0;
end
else if(a==1 && b==0 && cin==1)
begin
sum=0;
carry=1;
end
else if(a==1 && b==1 && cin==0)
begin
sum=0;
carry=1;
end
else if(a==1 && b==1 && cin==1)
begin
sum=1;
carry=1;
end
end
endmodule
iv)FULL SUBTRACTOR USING IF-ELSE STATEMENT
module fs_ifelse(a,b,bin,diff,bout);
input a,b,bin;
output reg diff,bout;
always@(a or b or bin)
begin
if(a==0 && b==0 && bin==0)
begin
diff=0;
bout=0;
end
else if(a==0 && b==0 && bin==1)
begin
diff=1;
bout=1;
end
else if(a==0 && b==1 && bin==0)
begin
diff=1;
bout=1;
end
else if(a==0 && b==1 && bin==1)
begin
diff=0;
bout=1;
end
else if(a==1 && b==0 && bin==0)
begin
diff=1;
bout=0;
end
else if(a==1 && b==0 && bin==1)
begin
diff=0;
bout=0;
end
else if(a==1 && b==1 && bin==0)
begin
diff=0;
bout=0;
end
else if(a==1 && b==1 && bin==1)
begin
diff=1;
bout=1;
end
end
endmodule
v)HALF ADDER USING CASE STATEMENT
module ha_case(a,sum,carry);
input [1:0]a;
output reg sum,carry;
always@(a)
begin
case(a)
2'b00:begin sum=0;carry=0;end
2'b01:begin sum=1;carry=0;end
2'b10:begin sum=1;carry=0;end
2'b11:begin sum=0;carry=1;end
endcase
end
endmodule
vi)HALF SUBTRACTOR USING CASE STATEMENT
module hs_case(a,diff,bout);
input [1:0]a;
output reg diff,bout;
always@(a)
begin
case(a)
2’b00:begin diff=0;bout=0;end
2’b01:begin diff=1;bout=1;end
2’b10:begin diff=1;bout=0;end
2’b11:begin diff=0;bout=0;end
endcase
end
endmodule
vii)FULL ADDER USING CASE STATEMENT
module fa_case(a,b,cin,sum,cout);
input a,b;
input cin;
output reg sum,cout;
always@(a or b or cin)
begin
case({a,b,cin})
3’b000:begin sum=0;cout=0;end
3’b001:begin sum=1;cout=0;end
3’b010:begin sum=1;cout=0;end
3’b011:begin sum=0;cout=1;end
3’b100:begin sum=1;cout=0;end
3’b101:begin sum=0;cout=1;end
3’b110:begin sum=0;cout=1;end
3’b111:begin sum=1;cout=1;end
endcase
end
endmodule
viii)FULL SUBTRACTOR USING CASE STATEMENT
module fs_case(a,b,bin,diff,bout);
input a,b;
input bin;
output reg diff,bout;
always@(a or b or bin)
begin
case({a,b,bin})
3’b000:begin diff=0;bout=0;end
3’b001:begin diff=1;bout=1;end
3’b010:begin diff=1;bout=1;end
3’b011:begin diff=0;bout=1;end
3’b100:begin diff=1;bout=0;end
3’b101:begin diff=0;bout=0;end
3’b110:begin diff=0;bout=0;end
3’b111:begin diff=1;bout=1;end
endcase
end
endmodule
SIMULATION OUTPUT:
i)HALF ADDER USING IF-ELSE STATEMENT
ii)HALF SUBTRACTOR USING IF-ELSE STATEMENT
iii)FULL ADDER USING IF-ELSE STATEMENT
iv)FULL SUBTRACTOR USING IF-ELSE STATEMENT
v)HALF ADDER USING CASE STATEMENT
vi)HALF SUBTRACTOR USING CASE STATEMENT
vii)FULL ADDER USING CASE STATEMENT
viii)FULL SUBTRACTOR USING CASE STATEMENT
Prelab(10)
Demo (20)
Record(10)
Viva(10)
Total(50)
RESULT:
Thus, the Half Adder, Half Subtractor, Full Adder,and Full Subtractor were
implemented using the behavioural modeling with if-else statement and case statement and
the functionality of the design was verified using MODELSIM software
