Six Switch Cascaded H bridge Five Level

Inverter For Single Phase Applications

Project Report
Submitted in partial fulfillment of the requirements

for the award of the B.Tech. degree in Electrical & Electronics Engineering

by

Krishnakanth C (TCR21EE080)

Krishnapriya NG(TCR21EE082)

Nandini Saj P(TCR21EE097)

Udit Mahesh (TCR21EE127)

Sherin VI (PKD21EE047)

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

GOVERNMENT ENGINEERING COLLEGE, THRISSUR

KERALA

December 2022
 DEPARTMENT OF ELECTRICAL
AND ELECTRONICS ENGINEERING

GOVERNMENT ENGINEERING COLLEGE

THRISSUR - 680009

Certificate

This is to certify that the report titled ”Six-Switch Cascaded

H-Bridge Five-Level Inverter For Single Phase Applications ” is a

bonafied record of the project report presented by Krishnakanth C

(TCR21EE080), Krishnapriya NG(TCR21EE082),Nandini Saj

P(TCR21EE097),Udit Mahesh (TCR21EE127),Sherin VI

(PKD21EE047). under our supervision toward the partial

fulfillment of the requirements for the award of B.Tech. in

Electrical & Electronics Engineering of A.P.J. Abdul Kalam

Technological University.

Dr.Jaison Mathew PROF.Lalgy Gopi

Associate Professor Assistant Professor
Dept. of Electrical and Electronics Dept. of Electrical and Electronics
Engineering . Engineering.
Government Engineering College Government Engineering College
Thrissur Thrissur
PROF. Nevin Jacob K
Assistant Professor
Dept. of Electrical and Electronics
Engg.
Government Engineering College
Thrissur

ii
 Declaration

We hereby declare that the project report Six-Switch Cascaded H

bridge Five level inverter For Single Phase Applications, submitted

for partial fulfillment of the requirements for the award of degree

of Bachelor of Technology of the APJ AbdulKalam Technological

university, Kerala is a bonafide work done by us under supervision

of Prof .Nevin Jacob K This submission represents our ideas in our

own words and where ideas or words of others have been included, we

have adequately and accurately cited referenced the original sources.

We also declare that I have adhered to ethics of academic honesty and

integrity and have not misrepresented or fabricated any data or idea or

fact or source in my submission. We understand that any violation of

the above will be a cause for disciplinary action by the institute and/or

the University and can also evoke panel action from the sources which

have thus not been properly cited or from whom proper permission

has not been obtained. This report has not been previously formed

the basis for the award of any degree, diploma or similar title of any

Other university.
 Acknowledgement

It gives us great pleasure to present our project report on ”Six-Switch

Cascaded H Bridge Five level Inverter For Single Phase Applications”.

No work, however big or small, has ever been done without the

contribution of others. So these words of acknowledgement,come

as a small gesture of gratitude towards all those people, without

whom the successful completion of this report would not have been

possible. We are extremely grateful to Dr.Meenakshy K , Principal,

Government Engineering College Thrissur and Dr. Manju B, Head

of department, Electrical Engineering, for providing all the required

resources for the successful completion of my project phase 1.We would

like to express our gratitude towards project coordinators Dr.Jaison

Mathews ,Prof.Lalgy Gopi Department of Electrical and Electronics

Engineering and our guide Prof .Nevin Jacob K who gave us their

valuable suggestions, reviews, motivation and direction. Last but not

the least we would like to thank all our friends, who supported us with

their valuable criticism, advice and support.

 Abstract

The need for effective inverter systems has increased due to the

growing integration of renewable energy sources, especially in solar

applications. Key performance parameters such output power quality,

power loss, implementation complexity, and cost are examined in this

study as it examines a modified version of a cascaded multilevel H-

bridge inverter. The best five-level inverter arrangement was found by

weighing trade-offs between various performance parameters. After

a thorough analysis of several cutting-edge PWM approaches, the

inverter uses a level-shifted in-phase disposition PWM scheme to

reduce harmonic distortion. For improved harmonic suppression, an

LC filter was added, which significantly improved the output waveform

quality. After MATLAB/ Simulink simulations were used to validate

the system, Proteus ISIS was used to implement it on hardware.

An ATmega microprocessor and a specially designed, inexpensive

MOSFET driver were used to

Contents

List of Figures viii

List of Tables viii

1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Outline of the Report . . . . . . . . . . . . . . . . . . . . 3

2 Literature Survey 4
2.1 1. ”A novel high energetic efficiency multilevel topology
with reduced impact on supply network ”by Y. Ounejjar
and K. Al-Haddad . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 2. ”Design and Hardware Implementation Considera-
tions of Modified Multilevel Cascaded H-Bridge Inverter
for Photovoltaic System” by S. Shuvo, E. Hossain, T.
Islam, A. Akib, S. Padmanaban, and M. Z. R. Khan . . 5

3 Methodology 6
3.1 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Pulse Width Modulation (PWM): . . . . . . . . . . . . . . 6
3.3 Matlab / Simulink Simulation . . . . . . . . . . . . . . . . 7
3.4 Microcontroller Implementation . . . . . . . . . . . . . . . 7
3.5 Comparison and evolution . . . . . . . . . . . . . . . . . . 8

vi
4 Circuit Diagram 9
4.1 Circuit Working . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Simulation 13
5.1 Simulation Diagram . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . 14

6 Hardware 17
6.1 Components and Specifications . . . . . . . . . . . . . . . 17
6.1.1 MOSFET (IRFP250 . . . . . . . . . . . . . . . . . . 17
6.1.2 Optocouplers(TLP250) . . . . . . . . . . . . . . . . 18
6.1.3 Microcontroller(ATmega2560) . . . . . . . . . . . . 19
6.1.4 Isolated DC-DC Converter . . . . . . . . . . . . . . 21
6.1.5 Resistors . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.6 Capacitors . . . . . . . . . . . . . . . . . . . . . . . 22

7 Conclusion 23
7.1 Future scope . . . . . . . . . . . . . . . . . . . . . . . . . . 24

vii
List of Figures

4.1 Circuit daigram at various switching . . . . . . . . . . . . 10

5.1 Block diagram for six switch cascaded H bridge five level
inverter with RL load . . . . . . . . . . . . . . . . . . . . . 13
5.2 RL load Io . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 RL load Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4 RL load THD . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1 Algorithm to operate ATmega2560 to generate PWM

signalsto drive the proposed inverter. Timer counter
registers ICR1 and ICR3 areused for defining PWM
frequency for timer 1 and timer 3. For defining pulse
width, OCR1A and OCR1B PWM pulse width registers
are used for . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

viii
Chapter 1

Introduction

1.1 Background

An advanced kind of multilevel inverter, a 6-switch 5-level Cascaded

H-Bridge (CHB) inverter is essential for converting direct current
(DC) into alternating current (AC) while also greatly enhancing output
waveform quality and lowering harmonic distortion. Applications for
this technology have grown in prominence, including motor drives,
power quality improvement, and renewable energy systems.
The notion of multilevel inverters, which use multiple voltage levels
to produce a more sinusoidal output waveform than conventional two-
level inverters, is the basis of this type of inverter. By doing this,
they contribute to lowering the output’s total harmonic distortion
(THD), which enhances power conversion efficiency and linked loads’
performance.
For a CHB to function, the cascaded H-bridge architecture is
essential.

1
1.2 Motivation

Motivation for a Six-Switch Cascaded H-Bridge Five-Level Inverter

1. Improved Power Quality: Generates a low-THD, near-sinusoidal
AC output.
2. Higher Efficiency: Lower switching losses with maintained
waveform quality.
3. Smaller Filters: Reduced need for large filters, ideal for compact
applications.
4. Scalable Design: Easily expandable for increased voltage or
better quality.
5. Lower Component Stress: Distributes voltage stress, enhancing
reliability.
6. Cost-Effective: Balances high performance with reduced compo-
nent costs.
7. Renewable Suitability: Optimized for efficient DC-to-AC
conversion in single-phase renewable systems.

1.3 Objectives

Aim To design and build a five-level, six-switch cascaded H-bridge

inverter for single-phase applications while minimising component
usage, maximising efficiency, and lowering total harmonic distortion
(THD).
Objectives
1. To create a five-level, six-switch cascaded H-bridge inverter with
the fewest possible parts.
2. To eliminate switching losses and circuit complexity as much as
possible in the design.

2
 3. To generate a lower THD AC output in contrast to conventional
lower-level inverters.
Effective and dependable power conversion systems are now re-
quired due to the growing demand for electric vehicles, renewable
energy systems, and other uses.
By lowering total harmonic distortion (THD), enhancing output
waveform quality, and permitting operation at greater voltage levels
with less stress on components, multi-level inverters (MLIs) meet this
need.
Nevertheless, there are still issues with current topologies, including
complicated control schemes, a higher component count, and the
requirement to balance capacitor voltages in specific setups.
Consequently, a topology that increases efficiency, lowers THD, and
uses the fewest components possible must be implemented.

1.4 Outline of the Report

The organization of this report is as follows.

As already seen, Chapter 1, presents background of the work on Six
switch five level CHB inverter.
Chapter 2, portrays the literature survey .
In Chapter 3, presents the definition of the problem and solution
methodology .
In Chapter 4, Explain circuit diagram and Circuit working.
In Chapter 5, shows Simulation result.
Chapter 6 shows hardware implementation strategies and chapter
?? brings out the final conclusion and future scope of our project.

3
Chapter 2

Literature Survey

2.1 1. ”A novel high energetic efficiency mul-

tilevel topology with reduced impact on

supply network ”by Y. Ounejjar and K. Al-

Haddad

This paper presents a novel multilevel inverter topology designed to

improve energy efficiency and reduce stress on the supply network. The
study introduces a six-switch, five-level cascaded H-bridge multilevel
inverter (MLI) and evaluates its performance in terms of energy
savings, harmonic reduction, and component optimization. The
authors focus on minimizing total harmonic distortion (THD) while
achieving a high-quality AC output. This work contributes to
developing more sustainable inverter designs that address the growing
demand for efficient, reliable power conversion in renewable energy
and other applications.

4
2.2 2. ”Design and Hardware Implementation

Considerations of Modified Multilevel Cas-

caded H-Bridge Inverter for Photovoltaic

System” by S. Shuvo, E. Hossain, T. Islam,

A. Akib, S. Padmanaban, and M. Z. R.

Khan

This paper focuses on the design and practical implementation of a

modified multilevel cascaded H-bridge inverter (CHB MLI) specifically
tailored for solar photovoltaic (PV) applications. The authors analyze
the use of a six-switch, five-level inverter configuration, comparing it
with more complex, higher-level inverter topologies. Their findings
highlight how this configuration balances efficiency, component count,
and cost-effectiveness, making it suitable for renewable energy setups.
The study also addresses challenges in achieving stable voltage levels,
reducing harmonic distortion, and managing control complexity, which
are crucial for real-world applications in PV systems. This work
emphasizes the practical feasibility and reliability of six-switch MLIs
in meeting PV system requirements

5
Chapter 3

Methodology

3.1 Topology

The design begins by selecting a five-level inverter topology with a

reduced switch count. The modified topology uses only six switches,
strategically placed to produce five distinct voltage levels at the
output. This approach reduces both the hardware complexity and the
associated costs while maintaining the quality of the output waveform.
Each switch is connected in an H-Bridge configuration, enabling the
inverter to generate different voltage levels by controlling the switching
states.

3.2 Pulse Width Modulation (PWM):

Pulse Width Modulation (PWM) is essential in refining the inverter’s

output. The methodology employs Level-Shifted PWM (LS-PWM),
which is designed to control each H-Bridge cell independently, enabling
multiple voltage levels to be synthesized.
LS-PWM involves using several carrier signals, each shifted in
phase, to control the switching points of each level. By adjusting the

6
width of the pulses, PWM can create a waveform that closely follows
a sinusoidal shape.
This approach reduces harmonic content, as PWM allows for precise
control over each level’s duration. LS-PWM ensures a balance between
the quality of the output waveform and the efficiency of the inverter.

3.3 Matlab / Simulink Simulation

Before constructing a physical prototype, the inverter is simulated

in MATLAB/Simulink. This simulation models each component and
switching angle to predict the output waveform’s behavior. By
analyzing the output in Simulink, researchers can examine THD levels,
switching losses, and waveform quality for each switching strategy.
In this study, each switching method is tested in the simulation
environment to determine which yields the most desirable performance
metrics.
The output waveform is analyzed for THD, frequency stability, and
voltage levels. Simulink’s ability to model the real-time behavior of
each component helps identify any issues in the design before physical
implementation.

3.4 Microcontroller Implementation

For the actual hardware prototype, an ATmega2560 microcontroller

is used to generate PWM signals and control the inverter’s switches.
The microcontroller’s programming defines the switching sequence and
timing for each H-Bridge cell based on the selected switching strategy.
This approach allows real-time control over each level’s voltage
output and switching state.The modified inverter’s performance is

7
evaluated against conventional multilevel inverters. Key metrics for
comparison include THD, efficiency, switching losses, and component
usage.

3.5 Comparison and evolution

The Six Switch cascaded H bridge five level inverter inverter’s

performance is evaluated against conventional multilevel inverters.
Key metrics for comparison include THD, efficiency, switching losses,
and component usage.
THD Comparison: The modified 5-level inverter is shown to achieve
lower THD than traditional inverters, with a stepped waveform that
closely approximates a sinusoidal shape.
Efficiency Assessment: Due to the reduced number of switches
and optimized switching strategy, the modified inverter demonstrates
higher efficiency and lower power losses.
Cost Analysis: The reduction in switch count and associated
components leads to lower manufacturing costs, making this design
a more cost-effective solution without sacrificing output quality.

8
Chapter 4

Circuit Diagram

9
4.1 Circuit Working

Figure 4.1: Circuit daigram at various switching

10
 H-Bridge Configuration: The core of the circuit is the H-bridge,
formed by four switches (S11, S12, S21, and S22). These switches are
typically transistors that can be turned on and off to control the flow
of current. Voltage Sources: Two voltage sources (V1 and V2) are
connected to the H-bridge. In this case, they seem to be DC voltage
sources. Controlling RL Load
Positive Voltage: To apply a positive voltage to the RL load, we
turn on S11 and S22 while keeping S12 and S21 off. This connects V1
to the top of RL and V2 to the bottom of RL, resulting in a positive
voltage across RL. Negative Voltage: To apply a negative voltage to the
RL load, we turn on S12 and S21 while keeping S11 and S22 off. This
connects V1 to the bottom of RL and V2 to the top of RL, resulting
in a negative voltage across RL. Zero Voltage: To apply zero voltage
to the RL load, we can either turn off all the switches or turn on both
S11 and S12 (while keeping S21 and S22 off ) or turn on both S21 and
S22 (while keeping S11 and S12 off ). This effectively disconnects the
load from the voltage sources.
+V: S11 and S22 are on, applying a positive voltage to RL. -V: S12
and S21 are on, applying a negative voltage to RL. +2V: Possibly a
higher voltage configuration by adjusting V1 and V2. -2V: Possibly a
lower voltage configuration by adjusting V1 and V2. Applications
H-bridge circuits like this are widely used in:
Motor Control: Varying the voltage applied to a motor allows
for controlling its speed and direction. Power Switching: Switching
high-power loads on and off efficiently. Audio Amplifiers: Generating
audio signals by varying the voltage applied to a speaker. Important
Considerations
Switch Ratings: The switches (transistors) in the H-bridge must be
rated for the voltage and current levels of the load. Heat Dissipation:

11
Switching high currents can generate heat, so proper heat dissipation
is crucial. Inductive Loads: If the load is inductive (like a motor),
precautions must be taken to handle the voltage spikes that can occur
when the current through an inductor is suddenly interrupted.

12
Chapter 5

Simulation

5.1 Simulation Diagram

Figure 5.1: Block diagram for six switch cascaded H bridge five level inverter
with RL load

13
5.2 Simulation Results

Figure 5.2: RL load Io

14
Figure 5.3: RL load Vo

15
Figure 5.4: RL load THD

16
Chapter 6

Hardware

6.1 Components and Specifications

6.1.1 MOSFET (IRFP250

The IRFP250 is a high-power N-channel MOSFET with: Drain-

Source Voltage (Vdss): 200V Continuous Drain Current (Id): 30A
Rds(on): 0.085 ohms Gate Charge (Qg): 160nC IRFP250s require an
appropriate gate driver circuit, especially at high frequencies. Use
isolated gate drivers to handle each H-bridge cell independently. The
driver should be able to provide the required gate charge within a
short time for faster switching.A very low cost MOSFETdriver is
introduced in this section compared to the pre vious mechanisms used
in this paper. It is achieved bydesigning an isolated MOSFET driver
by modifying theexisting non-isolated integrated circuit (IC), which

17
reducesthe cost of driving the MOSFETs by a considerable mar gin.
Non-isolated half bridge driver IR-2111 is used forthis MOSFET driver.
IR2111 is a half-bridge driver. It can The output of the proposed 5-
level multilevel CHB inverterwith 4 kHz PWM switching frequency,
implemented in hardware.

6.1.2 Optocouplers(TLP250)

Optocouplers are chosen to build the driving mechanism.6 TLP250

are required OK1 ,OK2 ,OK3,Ok4,Ok5,Ok6 are the designated octa-
couplers .The TLP250 is an optocoupler with an integrated gate driver
capable of directly driving MOSFETs and IGBTs.It can output up to
1.5A of peak current, which is generally sufficient for switching power
MOSFETs like the IRFP250.Each TLP250 will require a 15V supply
on the output side, isolated for each H-bridge cell. For a 6-switch CHB
inverter, you’ll need six isolated 15V supplies.Ensure each isolated
supply can handle the required current for both the TLP250 and the
MOSFET’s gate charging needs. Typically, a 0.5W or 1W isolated
DC-DC converter per TLP250 should suffice.The TLP250 can handle
switching frequencies up to about 20 kHz reliably, making it suitable

18
for many medium-speed applications. Specifications: Isolation Voltage:
2500 Vrms Output Peak Current: ±1.5A Supply Voltage (Vcc): 10-
35V Propagation Delay Time: 0.5 µs Switching Frequency: Up to 25
kHz Input Forward Current (If ): 10-20 mA Output Voltage Drop:
Vcc - 2.0V (typical at 0.1A) Operating Temperature Range: -20°C to
+85°C Package: 8-pin DIP or SMD

6.1.3 Microcontroller(ATmega2560)

19
 An ATmega2560 is used in this stage, which has four 16-bittimers
– thus meeting the design requirements.ATmega2560 has four timers
available, with three PWMchannels at each timer. Timer 1 and timer
3 are used in this hardware setup for PWM generation, using two
of eachof these timers’ available PWM channels. To operate the
microcontroller, certain registers need to be configured as instructed
by the datasheet . For the desired operation,timer counter registers
ICR1 and ICR3 are used for definingPWM frequency for timer 1 and
timer3. For defining pulse width, OCR1A and OCR1B registers are
used for the two channels of timer 1, while configuring OCR3A and
OCR3B registers served the purpose for the two channels of timer
3. Specifications: Microcontroller: 8-bit AVR RISC-based Operating
Voltage: 4.5 - 5.5V Flash Memory: 256 KB (of which 8 KB used by
bootloader) SRAM: 8 KB EEPROM: 4 KB Clock Speed: Up to 16
MHz Digital I/O Pins: 86 PWM Channels: 12 Analog Input Pins:
16 (10-bit ADC) Timers: Six (Two 8-bit and Four 16-bit) UART: 4
I2C (TWI): 1 SPI: 1 Operating Temperature Range: -40°C to +85°C
Package: 100-pin TQFP

20
Figure 6.1: Algorithm to operate ATmega2560 to generate PWM signalsto drive
the proposed inverter. Timer counter registers ICR1 and ICR3 areused for
defining PWM frequency for timer 1 and timer 3. For defining pulse width,
OCR1A and OCR1B PWM pulse width registers are used for

6.1.4 Isolated DC-DC Converter

Isolated DC-DC converters are critical for providing the isolated gate
drive power needed for each switch.These isolated DC-DC converters
power up totem-pole drive optocouplers, which receive signals from
the microcontroller, and this mecha nism drives the MOSFETs to
produce the multilevel out put.For a 6-switch CHB inverter, it requires
six isolated power supplies, one for each gate drive circuit DC1

21
,DC2,DC3,DC4 ,DC5,DC6 .

6.1.5 Resistors

For a 6-switch, 5-level CHB inverter, 10k ohm, 0.25W six resistors are
ideal as pull-down resistors on each MOSFET gate, ensuring stable off-
state operation. Make sure to place them close to each gate to prevent
noise interference. For other purposes, such as current limiting in
optocouplers or gate resistors, the value might need adjustment based
on specific circuit requirements.

6.1.6 Capacitors

In a 6-switch, 5-level CHB inverter,Two 1000 µF capacitors are useful

as DC link capacitors, ripple filters, and decoupling capacitors for gate
driver power supplies. Properly rated and positioned, these capacitors
contribute to stable and efEficient inverter operation.

22
Chapter 7

Conclusion

This study has introduced a single-phase modified 5-level symmetric

cascaded H-bridge (CHB) inverter with a streamlined design of only
6 switches. By reducing the number of switches, this inverter
design achieves a lower cost, simpler configuration, reduced space
requirements, and minimized switching losses, all of which contribute
to greater efficiency. The CHB architecture was selected over other
topologies due to its distinctive benefits, such as achieving the optimum
level count and switching frequency for effective power conversion.
While a 7-level CHB with a switching frequency of 6 kHz initially
showed the best unfiltered performance, an LC filter significantly
improved output quality . Additionally, advanced pulse-width mod-
ulation (PWM) techniques were explored, with the level-shifted in-
phase disposition PWM technique proving to be the most effective in
reducing THD. Although a higher switching frequency of over 7 kHz
was used, which increased switching losses, the substantial reduction
in THD improved the inverter’s overall performance, allowing the
increased losses to be considered negligible. After validating the
design through simulations in MATLAB/Simulink, the system was
tested and implemented in hardware using MOSFETs and an ATmega

23
microcontroller. Minor deviations in hardware output compared to
simulations were attributed to measurement using transformers. This
inverter design offers an efficient and feasible solution for power
conversion with potential applications in various fields.

7.1 Future scope

Future work can explore the application of this modified CHB inverter
in real-world standalone and grid-connected photovoltaic (PV) sys-
tems, which could benefit from the inverter’s reduced complexity and
efficient power conversion. Further research could involve optimizing
the inverter for compatibility with other renewable energy sources,
making it adaptable for hybrid systems. Additionally, improvements
in the control algorithms, especially in real-time feedback and adaptive
PWM techniques, could be investigated to enhance the inverter’s
response to variable load conditions and maximize its efficiency in dy-
namic environments. Thermal management and durability under high-
power operation could also be areas for enhancement, alongside the
exploration of more advanced semiconductor materials for MOSFETs
that offer lower conduction losses and higher switching capabilities. By
extending this work, the CHB inverter could contribute significantly
to the development of renewable energy systems and efficient power
management in modern electrical grids.

24
Bibliography

1. H. R. Muhammad, Power Electronics-Circuits, Devices, and

Applications. Upper Saddle River, NJ, USA: Prentice-Hall, 2004.
2. E. Villanueva, P. Correa, J. Rodrı́guez, and M. Pacas, “Control of
a single-phase cascaded H-bridge multilevel inverter for grid-connected
photovoltaic systems,” IEEE Trans. Power Electron., vol. 56, no. 11,
pp. 4399–4406, Nov. 2009.
3.E. E. Espinosa et al., “A new modulation method for a 13-level
asymmetric inverter toward minimum THD,” IEEE Trans. Ind. Appl.,
vol. 50, no. 3, pp. 1924–1933, May/Jun. 2014.
4.K. Yang, X. Lan, Q. Zhang, and X. Tang, “Unified Selective
Harmonic Elimination for Cascaded H-bridge Asymmetric Multilevel
Inverter,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 6, no. 4,
pp. 2138–2146, Dec. 2018.

25