Introduction to ASIC

• ASIC is an acronym for Application Specific Integrated

Circuit.
• As the name indicates, ASIC is a non-standard integrated
circuit that is designed for a specific use or application.
• ASICs are designed from scratch for a specific application,
ensuring optimized performance and functionality.
• They are more power-efficient and faster than general-
purpose ICs because they are customized for a single task.
Types of ASIC
Full-Custom ASICs
• A Full custom ASIC is one which includes some (possibly
all) logic cells that are customized and all mask layers that
are customized.
• Full-custom ICs are the most expensive to manufacture and
to design.
• A microprocessor is an example of a full-custom IC. Other
examples: memory, analog/digital communications
• The disadvantages of full-custom design include increased
design, time, complexity, design expense, and highest risk.
Semi-Custom ASIC
• ASICs , for which all of the logic cells are predesigned and
some (possibly all) of the mask layers are customized are
called semi-custom ASICs.
• Using the predesigned cells from a cell library makes the
design , much easier.
• There are two types of semicustom ASICs
(i) Standard-cell–based ASICs
(ii) Gate-array–based ASICs.
 Standard Cell Based ASIC
• A cell-based ASIC (cell-based
IC) uses predesigned logic cells
(AND gates, OR gates,
multiplexers, and flip-flops, for
example) known as standard
cells.
• All mask layers are customized.
• The ASIC designer defines only
the placement of the standard
cells and the interconnect in a
CBIC.
• However, the standard cells can
be placed anywhere on the
silicon; this means that all the
mask layers of a CBIC are
customized and are unique to a
particular customer.
 Gate-Array ASIC
• In a gate array (sometimes abbreviated GA) or gate-array based ASIC the
transistors are predefined on the silicon wafer.
• The predefined pattern of transistors on a gate array is the base array , and
the smallest element that is replicated to make the base array is the base
cell.
• The logic cells in a gate-array library are often called macros .
• A Gate Array ASIC is a partially prefabricated IC with a grid of
unconnected transistors or gates (AND, OR, NAND, NOR, etc.) on the
silicon wafer. Customization happens during the final manufacturing steps
by connecting these gates as per the design.
• Types:
o Channeled: encoder, decoder, other combinational circuits or low
complex circuits
o Channel-less: IoT devices, automative control systems, signal processing,
smart phones
 Programmable Logic Devices
• Programmable logic devices ( PLDs ) are standard ICs that are
available in standard configurations.
• However, PLDs may be configured or programmed to create a
part customized to a specific application, and so they also belong
to the family of ASICs.
• The simplest type of programmable IC is a read-only memory
(ROM).
• An electrically programmable ROM, or EPROM, uses
programmable MOS transistors whose characteristics are altered
by applying a high voltage.
Programmable Logic Device
Field-Programmable Gate Arrays (FPGAs)

• There is very little difference between an FPGA and a PLD. An

FPGA is usually just larger and more complex than a PLD.
• There is a method for programming the basic logic cells and the
interconnect.
• The core is a regular array of programmable basic logic cells
that can implement combinational as well as sequential logic
(flip-flops).
• Programmable I/O cells surround the core.
• The architecture consists of configurable logic blocks,
configurable I/O blocks, and programmable interconnect. Also,
there will be clock circuitry for driving the clock signals to each
logic block, and additional logic resources such as ALUs,
memory, and decoders may be available
FPGA Architecture
 Design Entry
ASIC Flow

Logic synthesis

System
Partitioning

Floor Planning Post layout

simulation

Placement

Routing Circuit
Extraction
 Introduction to SoC
• A System-on-Chip (SoC) is an integrated circuit (IC) that
consolidates all the essential components of a complete electronic
system onto a single chip.
• These components typically include a processor, memory,
input/output interfaces, and other functional modules required for
a specific application.
• Key Features:
o Compact Design
o Application-Specific
o Power efficiency
• Applications:
o Consumer electronics
o IoT Devices
o Automative
o Health care
o Industrial automation
Functional Verification
• The functional verification step verifies the functionality of
the design or the behavior of the system.
• It ensures that the design of a digital circuit (such as an
ASIC or SoC) functions correctly according to the
specified requirements before it is fabricated.
• Purpose of functional verification

1. Bug detection
2. Validation against Specifications
Steps in verification
1. Understanding Specifications
2. Developing Verification Plan
3. Creating a Testbench
4. Applying Test Stimuli
5. Checking Results
6. Debugging
7. Coverage Analysis
 RTL-Gate level Synthesis
• RTL (Register Transfer Level) to Gate-Level Synthesis is a crucial
step in the VLSI design flow. It involves transforming a high-level,
technology-independent description of a digital circuit (RTL) into a low-
level, technology-dependent netlist of logic gates that can be
implemented on a physical chip.
• Register Transfer Level (RTL) is a hardware description that represents
a digital circuit using constructs such as registers, combinational logic,
and clock cycles.
• RTL is written in hardware description languages (HDLs) like Verilog or
VHDL.
• A gate-level netlist is a detailed, technology-specific description of the
circuit, represented as a network of logic gates (e.g., AND, OR, NOT) and
flip-flops connected by wires.
• It is mapped to the standard cells of the target technology library provided
by the foundry.
Synthesis Optimization Techniques in VLSI
Synthesis optimization is a crucial step in the VLSI design process that
aims to improve the performance, area, and power of a digital circuit during
RTL to gate-level synthesis. Advanced tools and strategies are used to meet
design constraints while maintaining functional correctness.
1. Timing Optimization
Ensures that the design meets its clock frequency requirements by reducing
critical path delays.
•Strategies:
• Logic Restructuring: Reorganize logic to reduce delay along critical
paths.
• Path Balancing: Adjust timing of logic levels to equalize delays.
• Gate Sizing: Replace slower gates with faster (larger) gates to reduce
delay.
• Buffer Insertion: Add buffers to long paths to minimize signal delay.
• Pipelining: Split long combinational paths by inserting registers.
2. Area Optimization
Minimizes the silicon area required for the design, reducing costs and improving
yield.
•Strategies:
• Resource Sharing: Use the same hardware resources (e.g., adders or
multipliers) for multiple operations when possible.
• Gate Pruning: Remove unused or redundant logic.
• Logic Collapsing: Simplify combinational logic expressions to reduce
gate count.
3. Power Optimization
Reduces both dynamic and static power consumption to meet low-power design
goals.
•Strategies:
• Clock Gating: Disable the clock signal for idle parts of the circuit.
• Operand Isolation: Prevent unnecessary switching by isolating logic
when inputs are unchanged.
• Power-Aware Mapping: Choose gates with lower switching power
during synthesis.
4. Logic Optimization
Improves the design’s combinational logic by simplifying Boolean expressions
and removing redundancies.
•Strategies:
• Boolean Simplification: Use Karnaugh maps or heuristic algorithms to
simplify expressions.
• Redundancy Elimination: Detect and remove logic that doesn’t affect
the output.

5. Technology Mapping
Maps the high-level design to specific gates available in the target technology
library.
•Strategies:
• Library Selection: Choose the most appropriate standard cells for
power, area, and timing trade-offs.
• Cell Binding: Map high-level RTL operators (e.g., adders,
multiplexers) to optimized cell implementations
Pre-Layout Timing Verification
Pre-layout timing verification is a critical step in the VLSI
design process that ensures the design meets its timing
constraints before the physical layout (placement and routing) is
complete. At this stage, the design is represented as a gate-level
netlist, and interconnect delays are estimated
Purpose of Pre-Layout Timing Verification
1.Timing Closure:
1. Ensure the design meets setup, hold, and clock constraints.
2.Design Validation:
1. Verify that logic paths are correctly optimized and that
critical paths meet the required timing specifications.
3.Preparation for Physical Design:
1. Detect and address timing issues early to reduce iterations
during layout.
 Static-Timing Analysis
• It is a method of validating the timing performance of a
design by checking all possible paths from timing violations
under worst case conditions.
• It considers worst logical delay through each logic element
but not the logical operation of the circuit.
• It does not check the functionality of the circuit.
• Purpose:
Timing verification: Ensure the design meets setup and
hold timing requirements.
Identifying Critical Paths: Locate the slowest paths in the
design to optimize performance.
 Setup and Hold Time
Setup time is the minimum amount of time that the data input (D) must be
stable before the active edge (e.g., rising or falling edge) of the clock signal
for the data to be reliably latched into a flip-flop.
Why it matters: If the data input changes too close to the clock edge, the
flip-flop may enter a metastable state, potentially causing errors in the circuit.

Hold time is the minimum amount of time that the data input (D) must remain
stable after the active clock edge to ensure the data is properly latched.
Why it matters:
If the input data changes immediately after the clock edge, the flip-flop might
fail to capture the correct data.
 Clock Skew and Jitter
Clock skew (sometimes called timing skew) is a phenomenon in
synchronous digital circuit systems in which the same sourced
clock signal arrives at different components at different times.
Cause : Wires, Buffers etc
Types: Positive and Negative Skew

Clock Jitter: Sometimes some external sources like noise,

voltage variations may cause to disrupt the natural periodicity or
frequency of the clock. This deviation from the natural location
of the clock is termed to be clock jitter.
Timing Constraints in STA
Setup (Max) Constraints and Hold (min) constraints
Example
Question
Question
Calculate the minimum time period and maximum clock frequency at which
the circuit can operate.

Tclk>25 ns
F=1/Tclk
 Question

NOR delay: 2 ns
Inverter delay: 1 ns
Mux delay: 1.5 ns
Calculate critical path
delay?
Floor Planning
• To find approximate locations of a set of modules that need
to be placed on a layout surface

• Available region typically considered rectangular

• Modules are also rectangular in shape, but there may be

exceptions (for example L-shaped Module)

• The input to the Floor-planning phase is a set of blocks, the

area of each block, possible shapes of each block and the
number of terminals for each block and the netlist.
Factors for Floor Planning
Shape of the blocks: In order to simplify the problem, the blocks are assumed to be
rectangular. More recently, other shapes such as L-shapes have been considered,
however dealing with such shapes is computationally intensive.

Routing considerations: In chip planning, it is required that routing is considered as

an integral part of the problem. The blocks are placed in a manner such that there is
sufficient routing area between the blocks, so that routing algorithms can complete the
task of routing of nets between the blocks.

Packaging considerations: All of these blocks generate heat when the circuit is
operational. The heat dissipated should be uniform over the entire surface of the group
of blocks placed by the placement algorithms.

Pre-placed blocks: In some cases, the locations of some of the blocks may be fixed, or
a region may be specified for their placement. For example, in high performance chips,
the clock buffer may have to be located in the center of the chip.
 Placement
• In VLSI design, placement is a critical step in the physical design flow, which
comes after logic synthesis and before routing. Placement involves determining the
exact locations of standard cells (like logic gates, flip-flops, etc.) on the chip while
optimizing various factors such as area, power, timing, and routability.

• It is the process of arranging a set of modules on the layout surface.

– Each module has fixed shape and fixed terminal locations.

Objectives:

Minimize Wirelength: The overall wirelength affects both the signal delay and power
consumption. Good placement aims to reduce the interconnect lengths.
Timing Optimization: Critical paths, which affect the chip’s clock speed, should be
minimized by placing related cells closer together.
Power Distribution: Placement must ensure that power is distributed evenly, avoiding
hotspots.
Routability: Ensuring that the design has enough space for the routing of interconnects
without congestion.
 Floor plan vs Placement
Floorplanning: Some of the blocks may be flexible, and the exact location of the pins
are not yet fixed
Placement: All blocks have well-defined geometrical shapes, with defined pin
locations and separate space for routing
 Routing
Making physical connections between signal pins using metal layers is called routing.
•Nets must be routed within the routing regions.
•Nets must not be short-circuited.

Global Routing:
It divides the entire design into regions and generates a tentative route for each net. Each
net is assigned to a set of routing region.
It identifies the available tracks and assign layers to nets
It does not specify the actual layout of wires and it is not sensitive to DRV (design rule
violations).

Detailed routing:
The main goal of detailed routing is to complete all the required interconnects without
leaving shorts or spacing violations (DRC violations). Here, the actual layout of wire is
specified
It completes the connections by adding vias
It is routed in two phases:
First make all connections without worrying the DRC
Verify DRC and incrementally fix them till DRC count is zero.
CMOS Process Flow
Layout Design and design rules
• Layout design in VLSI (Very Large Scale Integration) refers to the
physical design phase in chip development, where the circuit design is
translated into a geometric representation. This step determines the
physical placement of transistors, interconnections, and other components
on the silicon wafer.

• The design rules are usually described in two ways:

(i) Micron rules, in which the layout constraints such as minimum feature
sizes and minimum allowable feature separations are stated in terms of
absolute dimensions in micrometers

(ii) Lambda rules, which specify the layout constraints in terms of a single
parameter (λ) and thus allow linear, proportional scaling of all geometrical
constraints.
Example layout
CMOS Layout
Stick Diagram
Stick Diagrams Rules
Example: Stick Diagram