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Common Source Amplifier Design Assignment

The document outlines an assignment for an Analog Electronics course at IIT Hyderabad, due on February 5, 2025. It includes instructions for designing a common source amplifier with specific performance criteria, such as a minimum small signal gain of 25 and various bandwidth calculations. Additionally, it requires the application of load capacitance and the comparison of designs with and without source degeneration resistance.

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Ameen Aazam
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26 views1 page

Common Source Amplifier Design Assignment

The document outlines an assignment for an Analog Electronics course at IIT Hyderabad, due on February 5, 2025. It includes instructions for designing a common source amplifier with specific performance criteria, such as a minimum small signal gain of 25 and various bandwidth calculations. Additionally, it requires the application of load capacitance and the comparison of designs with and without source degeneration resistance.

Uploaded by

Ameen Aazam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Electrical Engineering

Indian Institute of Technology Hyd January 29, 2025


Analog Elex
Deadline: 05 Feb 2025, 11:59 PM Assignment # 2 Maximum Marks: TBD
Instructions:
1. Rule of thumb = Fix Vdsat (for all nmos and pmos - mini. voltage required for saturation) = 150mV - 200mV.
2. βn = 300µA/V2 , βn = 75µA/V2 .
3. VDD = 3.3V, Tech Node = 180 nm
4. For all design consider the DC bias current = 100 µA
5. You can opt different values, mentioned in pt 1 and 4, if needed for your design with a propoer reasoning.
6. Use LT spice for simulations.
————————————————————————————————————————————————–

1. (a). Design (architecture and W/L ratio) a common source amplifier for a minimum small signal incremental gain
of 25. Design the circuit foe a maximize input and output swing for a given DC bais current of 100uA. Design
the circuit with proper biasing circuit.
(b). Plot the frequency response of the amplifier and find its 3dB frequency (or BW) and Unity Gain Bandwidth
(UGB).
(c). Apply a load capacitance of 1pF at the output and find its 3dB frequency (or BW) and Unity Gain Bandwidth
(UGB).
(d). Repeat part (a-c) for a CS amplifier with a source degenerative resistance of 5 kohm.
(e). Apply a source follower stage to the amplifier designed in both cases (with and without source degeneration
resistance) and drive the same load of 1 pF capacitance at the output of the second stage.
(f). Design a source follower amplifier for a gain of approximately 1 with proper biasing circuit to dirve an output
capacitance of 1pF. Find its 3dB frequency (or BW) and Unity Gain Bandwidth (UGB).
(g). Compare the 3dB BW of all designs with and without output load capacitance and comment that which design
gives best Gain×Bangwidth(3dB) product.

Student’s roll number: Ended here

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