PHYSICAL VLSI DESIGN L T P C
EC22504
(Common to EC and EE) 3 0 0 3
COURSE OBJECTIVES:
● To understand the fabrication processes of MOS circuits, design rules for layouts and the
limitations in scaling.
● To learn about realization of MOS circuits for various combinational logic blocks and
analyze the performance trade-offs with respect to the area, power and delay.
● To study the various arithmetic building blocks and their timing constraints.
● To learn about the various synchronous and asynchronous sequential designs and analyze
the timing constraints.
● To learn about the various architectural choices available for FPGA.
UNIT I MOS TRANSISTOR PRINCIPLE 9
NMOS, PMOS -Enhancement and depletion MOSFET; MOS transistor-Ideal I-V characteristics;
Fabrication Process - MOSFET, CMOS- n-well, p-well, Twin tub, SOI; Scaling principles and
fundamental limits; CMOS inverter characteristics; Stick diagram; Layout diagrams; Design rules;
Layer Representation.
UNIT II COMBINATIONAL LOGIC CIRCUITS 9
Static CMOS Design: Examples of Combinational Logic Design; Complementary CMOS concept
and properties; Ratioed Logic -DCVSL logic gate; Pass Transistor Logic - Concept,
Complementary PTL and Differential PTL; CMOS transmission gate; Elmore’s constant; Dynamic
CMOS design: Dynamic Logic - Basic Principles; Issues in Dynamic Design; Cascading Dynamic
Gates.
UNIT III SEQUENTIAL LOGIC CIRCUITS 9
Timing Metrics for Sequential Circuits; Static Latches and Registers; Bi-stability Principle;
Multiplexer Based Latches; Master-Slave based Edge Triggered Register; Non-ideal clock signals;
Dynamic Latches and Registers; Transmission-Gate Edge-triggered Registers; C2MOS Register;
Dual-Edge Registers; Timing issues; Pipelines; Clock Strategies; Synchronous and Asynchronous
design. Introduction to Memory.
UNIT IV DESIGNING ARITHMETIC BUILDING BLOCKS 9
Data path circuits: Architectures for Ripple Carry Adders; Carry Look Ahead Adders; Carry Select
Adder; Carry Bypass Adder; High speed adders - Brunt Kung adder, Kogge Stone; Multipliers -
Wallace Tree multiplier, Booth Multiplier; Barrel shifters; Speed and Area Trade-off for all above
Arithmetic Building Blocks.
UNIT V IMPLEMENTATION STRATEGIES 9
Full custom and Semi-custom design; Standard cell design and cell libraries; FPGA building block
architecture - FPGA interconnect routing procedures; Design for Testability: Ad Hoc Testing, Scan
Design, BIST. Low power design principles.
TOTAL: 45 PERIODS
TEXT BOOKS:
1. Jan M.Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated Circuits: A
Design Perspective”, Third Edition, Prentice Hall of India, 2008.
2. M.J. Smith, “Application Specific Integrated Circuits”, Addisson Wesley, 1997.
REFERENCES:
1. N.Weste, K.Eshraghian, “Principles of CMOS VLSI Design”, Second Edition, Addision
Wesley 1993.
2. R.Jacob Baker, Harry W.LI., David E.Boyee, “CMOS Circuit Design, Layout and
Simulation”, Prentice Hall of India 2005.
3. 3. A.Pucknell, Kamran Eshraghian, “BASIC VLSI Design”, Third Edition, Prentice Hall of
India, 2007.
COURSE OUTCOMES: RBT
Upon successful completion of the course, students should be able to: Level
Represent the CMOS logic circuit design using Stick Diagrams and Layout
CO1 3
Diagrams.
CO2 Realize the MOS circuits for various combinational logic blocks. 4
CO3 Choose a suitable MOS logic style for designing Sequential logic blocks. 4
CO4 Select suitable MOS logic style for designing arithmetic logic blocks. 4
CO5 Choose a suitable FPGA implementation strategy. 3
Bloom’s Taxonomy (RBT) Level: Remember-1; Understand-2; Apply-3; Analyze-4; Evaluate-5;
Create-6
COURSE ARTICULATION MATRIX
*COs POs PSOs
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1. 3 3 - 2 3 - - - - - - 2 3 3
2. 3 2 1 3 3 - 2 - - - - 2 3 3
3. 3 2 1 3 3 - 2 - - - - 2 3 3
4. 3 2 1 3 3 - - - - - - 2 3 3
5. 3 2 - 2 3 - - - - - - 2 3 1
* 1 – Weak, 2 – Moderate, 3 - Strong
L T P C
EC22505 TRANSMISSION LINES AND RF SYSTEMS
3 0 0 3
COURSE OBJECTIVES:
• To inculcate the various types of transmission lines.
• To give thorough understanding about high frequency line, power and impedance
measurements.
• To impart technical knowledge in impedance matching using smith chart.
• To introduce waveguides and high frequency parameters for circuit representation of RF
network.
• To deal with the issues in the design of RF amplifiers and filters.
UNIT I TRANSMISSION LINE THEORY 9
Symmetrical networks- Characteristic impedance and Propagation constant, General theory of
Transmission lines-Types, General solution, The infinite line, Wavelength, Velocity of propagation,
Waveform distortion, the distortion-less line, Line not terminated in Z0, Reflection coefficient,
Reflection factor, Reflection Loss, Input and transfer impedance, Open and short circuited lines.
UNIT II HIGH FREQUENCY TRANSMISSION LINES 9
Transmission line equations at radio frequencies, Line constants of Zero dissipation, Voltage and
current on the dissipation less line, Standing Waves, Standing Wave Ratio, Input impedance of the
dissipation-less line - Open and short-circuited lines, Power and Impedance measurement
UNIT III IMPEDANCE MATCHING IN HIGH FREQUENCY LINES 9
Impedance matching: λ/8, λ/2 lines, Quarter wave transformer- Impedance matching by stubs -
Single stub and double stub matching - Smith chart-Solutions of problems using Smith chart -Single
stub matching using Smith chart.
UNIT IV TWO PORT NETWORK THEORY AND WAVEGUIDES 9
High Frequency parameters, Formulation of S parameters, Properties of S parameters, Reciprocal
and lossless Network, Transmission matrix, Waveguides- Rectangular and Circular, TE and TM
modes in rectangular waveguides. Introduction to resonators.
UNIT V RF AMPLIFIERS AND FILTERS 9
RF amplifiers- design of amplifiers, Filter fundamentals, Design of filters of Constant K - Low Pass,
High Pass, Band Pass, Band Elimination, m- derived sections - low pass, high pass.
TOTAL: 45 PERIODS
TEXT BOOKS:
1. John D.Ryder, “Networks, Lines and Fields”, Prentice Hall of India, 2nd Edition, 2006.
2. Reinhold Ludwig and Gene Bogdanov, “RF Circuit Design: Theory and Applications”,
Pearson Education Inc., 2011.
3. Samuel Y Liao, “Microwave Devices and Circuits” Prentice Hall of India 2012.
REFERENCES:
1. Umesh Sinha, "Transmission Lines and Networks: Networks, Filters and Transmission lines"
Satya Prakashan, Publication, 2010.
2. E.C.Jordan and K.G. Balmain, ―Electromagnetic Waves and Radiating System, Prentice
Hall of India, 2006.
COURSE OUTCOMES: RBT
Upon successful completion of the course, students should be able to: Level
Explain line theory and classify transmission lines. Assess distortion less
CO1 2
transmissions on lines.
CO2 Express transmission lines at high frequency and assess the performance. 2
Assess performance of lines implementing impedance matching techniques using
CO3 3
Smith chart.
CO4 Explain the high frequency parameters and waveguides. 2
CO5 Analyze amplifiers at RF amplifier and design filters. 3
Bloom’s Taxonomy (RBT) Level: Remember-1; Understand-2; Apply-3; Analyze-4; Evaluate-5;
Create-6
COURSE ARTICULATION MATRIX
*COs POs PSOs
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1. 1 1 2 - - 3 1 1 - 2 - 1 2 -
2. 1 1 2 - - 3 1 1 - 2 - 1 2 -
3. 1 1 2 - - 3 1 1 - 2 - 1 2 -
4. 1 1 2 - - 3 1 1 - 2 - 1 2 -
5. 1 1 2 - - 3 1 1 - 2 - 1 2 -
* 1 – Weak, 2 – Moderate, 3 - Strong
L T P C
EC22511 COMMUNICATION SYSTEMS LABORATORY
0 0 3 1.5
COURSE OBJECTIVES:
• To visualize the effects of sampling, multiplexing and digital pulse modulation techniques.
• To implement AM & FM modulation and demodulation.
• To implement FSK, PSK and M-ary schemes.
• To implement Equalization algorithms and Error control coding schemes.
• To simulate communication link and CDMA link
LIST OF EXPERIMENTS
1. Signal Sampling and reconstruction
2. Time Division Multiplexing
3. AM Modulator and Demodulator
4. FM Modulator and Demodulator
5. Pulse Code Modulation and Demodulation
6. Delta Modulation and Demodulation
7. Observation (simulation) of signal constellations of BPSK, QPSK
8. Line coding schemes
9. ASK, FSK, PSK, DPSK, BPSK, QPSK and M-ary schemes (Simulation)
10. Error control coding schemes - Linear Block Codes (Simulation)
11. Communication link simulation
12. CDMA- DSSS and FHSS (simulation)
Note: Observed outputs of experiments and Simulated outputs must be plotted and attached to the
records written by the students.
TOTAL: 45 PERIODS
LIST OF EQUIPMENTS FOR A BATCH OF 30 STUDENTS:
Description of Items Quantity
Kits for Signal Sampling, TDM, AM, FM, PCM, DM and Line Coding Schemes 2 Nos. each
MATLAB / SCILAB or equivalent software package for simulation experiments 10 Licenses
CRO’s 10 Nos
PCs 10 No
Signal Generator /Function Generators (2 MHz) 10 Nos
Components and Accessories: Transistor-BC 107, XR 2206, Resistors, Capacitors, -
diodes,Bread Boards,wires,IC 565
TEXT BOOKS:
1. Simon Haykin, “Communication Systems”, 4th edition, Wiley Publications, 2013.
2. Amitabha Bhattacharya, “Digital Communication”, TMH, Ninth Reprint 2017.
COURSE OUTCOMES: RBT
Upon successful completion of the course, students should be able to: Level
Construct and validate the results of AM, FM modulator and Demodulator, Time
CO1 Division Multiplexing (TDM), Signal Sampling and Reconstruction, Pulse Code 3
Modulation (PCM), Delta Modulation and Demodulation
CO2 Construct and observe the results of Base Band Signaling techniques 3
Simulation and forecasting of Signal Constellations, Digital Modulation Schemes in
CO3 4
MATLAB
Simulate and verify the results of error detection and correction coding techniques
CO4 4
in MATLAB.
Simulate and validate the results of AM Communication link(system) using
CO5 4
MATLAB.
Bloom’s Taxonomy (RBT) Level: Remember-1; Understand-2; Apply-3; Analyze-4; Evaluate-5;
Create-6
COURSE ARTICULATION MATRIX
*COs POs PSOs
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1. 3 3 3 3 2 - - - - - - 3 3 3
2. 3 3 3 3 2 - - - - - - 3 3 3
3. 3 3 3 3 2 - - - - - - 3 3 3
4. 3 3 3 3 - - - - - - - 3 3 3
5. 3 3 3 3 - - - - - - - 3 3 3
* 1 – Weak, 2 – Moderate, 3 - Strong
L T P C
EC22512 COMMUNICATION NETWORKS LABORATORY
0 0 3 1.5
COURSE OBJECTIVES:
• To understand the working of various network protocols through implementation.
• To have hands-on experience in configuring and simulating computer networks using network
simulation tools.
• To examine the functionality of networking devices like hub, switch, router, repeater, etc.
through practical implementation.
• To implement and analyze various network topologies through practical setup.
• To understand routing algorithms through practical implementation.
LIST OF EXPERIMENTS
1. Implementation of Ethernet/Fast Ethernet and TCP protocol
2. Implementation of Stop and Wait, Goback-N and Selective Repeat Protocol
3. Simulation of a Client-Server Model including the configuration of Telnet
4. Simulation of Echo/Ping/Talk commands
5. Implementation of CSMA / CA protocol and compare with CSMA/CD protocols.
6. Implementing Standard Network Topologies: Star, Bus and Ring using LAN Trainer Kit
7. Implementation of Distance Vector and Link State Routing algorithm
8. Implementation of Encryption and Decryption Using LAN Trainer Kit
9. Configuration of VLAN
10. Simulation of HTTP and DNS Server
11.Configuration of Wireless LAN
12. Configuration of Address Resolution protocol
13. Simulation of DHCP protocol
TOTAL: 45 PERIODS
LIST OF EQUIPMENTS FOR A BATCH OF 30 STUDENTS:
Description of Items Quantity
Desktop Computers-8GB RAM/512GB HDD, Processor i3/i5 30
Cisco Packet Tracer Software 30
N-Sim 15
LAN Trainer Kit 3
TEXT BOOKS:
1. William Stallings, Cryptography and Network Security, Seventh Edition, Pearson Education,
2017.
2. Behrouz A. Forouzan, “Cryptography and Network Security”, 2nd edition Tata McGraw Hill,
2010.
COURSE OUTCOMES: RBT
Upon successful completion of the course, students should be able to: Level
Design & simulate computer networks using network simulation tools and analyze
CO1 6
performance.
CO2 Examine functionality of networking devices through practical setup. 4
CO3 Design and implement different network topologies. 6
CO4 Implement and analyze various network protocols. 4
Obtain the comprehensive hands-on experience in configuring, managing and
CO5 4
troubleshooting computer networks.
Bloom’s Taxonomy (RBT) Level: Remember-1; Understand-2; Apply-3; Analyze-4; Evaluate-5;
Create-6
COURSE ARTICULATION MATRIX
POs PSOs
COs
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1. 3 3 3 2 3 1 - - - 3 1 1 3 2
2. 3 2 2 3 3 2 - - - 2 - 1 2 1
3. 3 3 3 2 3 1 - - - 3 1 1 3 2
4. 3 2 2 3 3 1 - - - 2 - 1 2 1
5. 3 3 2 3 3 2 - - - 2 - 1 2 1
* 1 – Weak, 2 – Moderate, 3 - Strong
L T P C
EC22513 VLSI DESIGN LABORATORY
0 0 3 1.5
COURSE OBJECTIVES:
● To learn Hardware Descriptive Language
● To learn the fundamental principles of VLSI circuit design in digital and analog domain.
● To familiarize fusing of logical modules on FPGAs
● To provide hands on design experience with professional design (EDA) platforms
● To provide an idea of making an effective report based on experiments.
LIST OF EXPERIMENTS
1. HDL based design and simulation of Combinational circuits
(a) 4-bit Ripple Carry Adder
(b) Carry Look ahead adder
(c) Multiplexer and Demultiplexer
(d) Decoder and Priority Encoder
(e) Code Converters
2. HDL based design and simulation of Sequential circuits
(a) Shift register (SISO, SIPO, PIPO)
(b) Synchronous and asynchronous Counter design
(c) Mealy and Moore model
3. HDL based design, simulation and synthesis of Multiplier and ALU - Perform Synthesis, Place &
Route, post Place & Route simulation and static timing analysis. Identification of critical path
4. Simulation of Static and Dynamic logic using EDA tool.
5. Design and schematic simulation of a simple analog circuit and analyze the same
6. Layout generation, parasitic extraction and post-simulation of Inverter & Universal Gates
7. Analyze the Area, Power and Delay for sequential circuits using the EDA tool.
TOTAL: 45 PERIODS
LIST OF EQUIPMENTS FOR A BATCH OF 30 STUDENTS:
Description of Items Quantity
1. Xilinx software, Xilinx or Altera FPGA 15 Nos.
2. Cadence/Tanner or equivalent software package 15 Licenses
3. PCs 15 Nos.
TEXT BOOKS:
1. R. Jacob Baker, “CMOS: Circuit Design, Layout, and Simulation”, IEEE Press, Wiley, 2010
2. Sung-Mo Kang & Yusuf Leblebici, CMOS Digital Integrated Circuits - Analysis & Design,
MGH, Second Ed., 1999.
3. Kang, Leblibici, CMOS Digital Integrated Circuits, 3rd Ed., Tata Mc-Graw Hill, 2001.
4. Jan M. Rabaey, Digital Integrated Circuits, 2nd Ed., Pearson Education, 2002.
5. Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, Pearson Education,
2nd Edition, 2010.
COURSE OUTCOMES: RBT
Upon successful completion of the course, students should be able to: Level
CO1 Prepare HDL code for basic as well as advanced digital integrated circuits. 3
CO2 Use and import the logic modules into FPGA Boards. 4
CO3 Design, Synthesize, Place and Route the digital ICs. 4
CO4 Design, Simulate and Extract the layouts of IC Blocks using EDA tools. 4
CO5 Compute Area, Delay and Power report of digital circuits using EDA tools. 4
Bloom’s Taxonomy (RBT) Level: Remember-1; Understand-2; Apply-3; Analyze-4; Evaluate-5;
Create-6
COURSE ARTICULATION MATRIX
*CO POs PSOs
s 1 2 3 4 5 6 7 8 9 10 11 12 13 14
1. 3 3 - - - - - - - - - - - 1
2. 2 2 2 - - - - - - - - 2 - -
3. 2 3 3 - - - - - - - - - - 2
4. 1 2 - - - - - - - - - - - -
5. 2 2 1 - - - - - - - - - - -
* 1 – Weak, 2 – Moderate, 3 - Strong
