Omni ision

Advanced Information
® Preliminary Datasheet

OV7720/OV7221 CMOS VGA (640x480) CAMERACHIPTM Sensor

with OmniPixel2TM Technology

General Description Applications

The OV7720 (color) and OV7211 (black and white) • Cellular and picture phones
CAMERACHIP™ image sensors are low voltage CMOS • Toys
image sensors that provide the full functionality of a • PC Multimedia
single-chip VGA camera and image processor in a small • Digital still cameras
footprint package. The OV7720/OV7221 provides
full-frame, sub-sampled or windowed 8-bit/10-bit images Key Specifications
in a wide range of formats, controlled through the Serial
Camera Control Bus (SCCB) interface. Array Size 640 x 480
This device has an image array capable of operating at up Digital Core 1.8VDC + 10%
to 60 frames per second (fps) in VGA with complete user Power Supply Analog 3.0V to 3.3V
control over image quality, formatting and output data I/Oa 1.7V to 3.3V
transfer. All required image processing functions, Power Active
120 mW typical
including exposure control, gamma, white balance, color (60 fps VGA, YUV)
Requirements
saturation, hue control and more, are also programmable Standby < 20 µA
through the SCCB interface. In addition, OmniVision Temperature Range -20°C to +70°C
sensors use proprietary sensor technology to improve • YUV/YCbCr [Link]
image quality by reducing or eliminating common • RGB565/555/444
Output Format (8-bit)
lighting/electrical sources of image contamination, such • GRB [Link]
as fixed pattern noise, smearing, blooming, etc., to • Raw RGB Data
produce a clean, fully stable color image. Lens Size 1/4"
Lens Chief Ray Angle TBD
Note: The OV7720/OV7221-CSP2 uses Max Image Transfer Rate 60 fps for VGA
Pb a lead-free package. Sensitivity
S/N Ratio
TBD
TBD
Dynamic Range TBD
Features Scan Mode Progressive
Electronic Exposure Up to 510:1 (for selected fps)
• High sensitivity for low-light operation
• Standard SCCB interface Pixel Size 6.0 µm x 6.0 µm
• Output support for Raw RGB, RGB (GRB [Link], Dark Current TBD
RGB565/555/444) and YCbCr ([Link]) formats Well Capacity TBD
• Supports image sizes: VGA, QVGA, and any size Fixed Pattern Noise < 0.03% of VPEAK-TO-PEAK
scaling down from CIF to 40x30 Image Area 3984 µm x 2952 µm
• VarioPixel® method for sub-sampling Package Dimensions 5345 µm x 5265 µm
• Automatic image control functions including: a. I/O power should be 2.45V or higher when using the internal
Automatic Exposure Control (AEC), Automatic Gain regulator for Core (1.8V); otherwise, it is necessary to provide
Control (AGC), Automatic White Balance (AWB), an external 1.8V for the Core power supply
Automatic Band Filter (ABF), and Automatic Figure 1 OV7720/OV7221-CSP2 Pinout (Top View)
Black-Level Calibration (ABLC)
• Image quality controls including color saturation,
hue, gamma, sharpness (edge enhancement), and
A1 A2 A3 A4 A5 A6
anti-blooming ADVDD RSTB VREFH FSIN SCL D0
• ISP includes noise reduction and defect correction
B1 B2 B3 B4 B5 B6
• Lens shading correction
ADGND VREFN AVDD AGND SDA HREF
• Saturation level auto adjust (UV adjust)
C1 C6
• Edge enhancement level auto adjust
• De-noise level auto adjust PWDN
OV7720 / OV7221 VSYNC

• Frame synchronization capability D1 D6

D5 D4

Ordering Information E1 E2 E3 E4 E5 E6
D7 D1 DVDD PCLK DOVDD D6
Product Package F1 F2 F3 F4 F5 F6

OV07720-VL1A (Color, lead-free) 28-pin CSP2 D9 D3 XCLK DOGND D2 D8

OV07221-VL1A (B&W, lead-free) 28-pin CSP2 7720CSP_DS_001

© 2006 OmniVision Technologies, Inc. VarioPixel, OmniVision, and the OmniVision logo are registered trademarks of OmniVision Technologies, Inc.
Version 1.1, September 1, 2006 OmniPixel2 and CameraChip are trademarks of OmniVision Technologies, Inc.
These specifications are subject to change without notice.
OV7720/OV7221-CSP2 CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision

Functional Description
Figure 2 shows the functional block diagram of the OV7720/OV7221 image sensor. The OV7720/OV7221 includes:
• Image Sensor Array (total array of 656 x 488 pixels, with active pixels 640 x 480 in YUV mode)
• Analog Signal Processor
• A/D Converters
• Test Pattern Generator
• Digital Signal Processor (DSP)
• Image Scaler
• Timing Generator
• Digital Video Port
• SCCB Interface

Figure 2 Functional Block Diagram

column G
sense amp buffer buffer

analog R
A/D
row select

processing
image
array B image video
DSP* scaler FIFO port D[9:0]

exposure/ test pattern

gain detect generator

registers

video timing exposure/gain SCCB

clock generator control interface
XCLK

FSIN

HREF

PCLK

VSYNC

RSTB

PWDN

SCL

SDA

note 1 DSP* (lens shading correction, de-noise, white/black pixel correction, auto white balance, etc.) 7720CSP_DS_002

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Omni ision Functional Description

Image Sensor Array In general, the combination of the A/D Range Multiplier
and A/D Range Control sets the A/D range and maximum
The OV7720/OV7221 sensor has an image array of value to allow the user to adjust the final image brightness
656 x 488 pixels for a total of 320,128 pixels, of which as a function of the individual application.
640 x 480 pixels are active (307,200 pixels). Figure 3
shows a cross-section of the image sensor array.

Figure 3 Image Sensor Array

Test Pattern Generator

The Test Pattern Generator features the following:

glass
• 8-bar color bar pattern
• Shift "1" in output pin

microlens microlens microlens

Digital Signal Processor (DSP)

This block controls the interpolation from Raw data to

green red RGB and some image quality control.
blue
• Edge enhancement (a two-dimensional high pass
filter)
7720CSP_DS_003
• Color space converter (can change Raw data to RGB
or YUV/YCbCr)
Timing Generator • RGB matrix to eliminate color cross talk
• Hue and saturation control
In general, the timing generator controls the following
• Programmable gamma control
functions:
• Transfer 10-bit data to 8-bit
• Array control and frame generation
• Internal timing signal generation and distribution
• Frame rate timing
Image Scaler
• Automatic Exposure Control (AEC)
• External timing outputs (VSYNC, HREF/HSYNC, and This block controls all output and data formatting required
PCLK) prior to sending the image out. This block scales
YUV/RGB output from VGA to CIF and almost any size
under CIF.
Analog Signal Processor

This block performs all analog image functions including: Digital Video Port
• Automatic Gain Control (AGC)
• Automatic White Balance (AWB) Register bits COM2[1:0] increase IOL/IOH drive current
and can be adjusted as a function of the customer’s
loading.
A/D Converters

After the Analog Processing block, the bayer pattern Raw SCCB Interface
signal is fed to a 10-bit analog-to-digital (A/D) converter
shared by G and BR channels. This A/D converter The Serial Camera Control Bus (SCCB) interface controls
operates at speeds up to 12 MHz and is fully synchronous the CAMERACHIP sensor operation. Refer to OmniVision
to the pixel rate (actual conversion rate is related to the Technologies Serial Camera Control Bus (SCCB)
frame rate). Specification for detailed usage of the serial control port.

In addition to the A/D conversion, this block also has the

following functions:
• Digital Black-Level Calibration (BLC)
• Optional U/V channel delay
• Additional A/D range controls

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Pin Description

Table 1 Pin Description

Pin Number Name Pin Type Function/Description

A1 ADVDD Power ADC power supply

A2 RSTB Input System reset input, active low

A3 VREFH Reference Reference voltage - connect to ground using a 0.1 µF capacitor

A4 FSIN Input Frame synchronize input

A5 SCL Input SCCB serial interface clock input

A6 D0a Output Data output bit[0]

B1 ADGND Power ADC ground

B2 VREFN Reference Reference voltage - connect to ground using a 0.1 µF capacitor

B3 AVDD Power Analog power supply

B4 AGND Power Analog ground

B5 SDA I/O SCCB serial interface data I/O

B6 HREF Output HREF output

Power Down Mode Selection

C1 PWDN Input (0)b 0: Normal mode
1: Power down mode

C6 VSYNC Output Vertical sync output

D1 D5 Output Data output bit[5]

D6 D4 Output Data output bit[4]

E1 D7 Output Data output bit[7]

E2 D1 Output Data output bit[1]

E3 DVDD Power Power supply (+1.8 VDC) for digital logic core

E4 PCLK Output Pixel clock output

E5 DOVDD Power Digital power supply for I/O (1.7V ~ 3.3V)

E6 D6 Output Data output bit[6]

F1 D9c Output Data output bit[9]

F2 D3 Output Data output bit[3]

F3 XCLK Input System clock input

F4 DOGND Power Digital ground

F5 D2 Output Data output bit[2]

F6 D8 Output Data output bit[8]

a. D[9:0] for 10-bit Raw RGB data (D[9] MSB, D[0] LSB)
b. Input (0) represents an internal pull-down resistor.
c. D[9:2] for 8-bit YUV or RGB565/RGB555 (D[9] MSB, D[2] LSB)

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Omni ision Electrical Characteristics

Electrical Characteristics
Table 2 Operating Conditions

Parameter Min Max

Operating temperature -20°C +70°C

Storage temperaturea -40°C +125°C

a. Exceeding the stresses listed may permanently damage the device. This is a stress rating only and functional operation
of the sensor at these and any other condition above those indicated in this specification is not implied. Exposure to
absolute maximum rating conditions for any extended period may affect reliability.

Table 3 Absolute Maximum Ratings

Ambient Storage Temperature -40ºC to +95ºC

VDD-A 4.5 V

Supply Voltages (with respect to Ground) VDD-C 3V

VDD-IO 4.5 V

All Input/Output Voltages (with respect to Ground) -0.3V to VDD-IO+0.5V

Lead-free Temperature, Surface-mount process 245ºC

NOTE: Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may
result in permanent device damage.

Table 4 DC Characteristics (-20°C < TA < 70°C)

Symbol Parameter Condition Min Typ Max Unit

VDD-A DC supply voltage – Analog – 3.0 3.3 3.6 V

VDD-C DC supply voltage – Digital Core – 1.62 1.8 1.98 V

VDD-IO DC supply voltage – I/O power – 2.5 – 3.3 V

IDDA Active (Operating) current See Note a 10 + 8b mA

IDDS-SCCB Standby current 1 mA

See Note c
IDDS-PWDN Standby current 10 20 µA

VIH Input voltage HIGH CMOS 0.7 x VDD-IO V

VIL Input voltage LOW 0.3 x VDD-IO V

VOH Output voltage HIGH CMOS 0.9 x VDD-IO V

VOL Output voltage LOW 0.1 x VDD-IO V

IOH Output current HIGH See Note d 8 mA

IOL Output current LOW 15 mA

IL Input/Output leakage GND to VDD-IO ±1 µA

a. VDD-A = 3.3V, VDD-C = 1.8V, VDD-IO = 3.3V

IDDA = ∑{IDD-IO+ IDD-C + IDD-A}, fCLK = 24MHz at 30 fps YUV output, no I/O loading
b. IDD-C = 10mA, IDD-A = 8mA, without loading
c. VDD-A = 3.3V, VDD-C = 1.8V, VDD-IO = 3.3V
IDDS-SCCB refers to a SCCB-initiated Standby, while IDDS-PWDN refers to a PWDN pin-initiated Standby
d. Standard Output Loading = 25pF, 1.2KΩ

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OV7720/OV7221-CSP2 CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision

Table 5 Functional and AC Characteristics (-20°C < TA < 70°C)

Symbol Parameter Min Typ Max Unit
Functional Characteristics
A/D Differential non-linearity + 1/2 LSB
A/D Integral non-linearity +1 LSB
AGC Range 30 dB
Red/Blue adjustment range 12 dB
Inputs (PWDN, CLK, RESET#)

fCLK Input clock frequency 10 24 48 MHz

tCLK Input clock period 21 42 100 ns

tCLK:DC Clock duty cycle 45 50 55 %

tS:RESET Setting time after software/hardware reset 1 ms

tS:REG Settling time for register change (10 frames required) 300 ms
SCCB Timing (see Figure 4)

fSCL Clock frequency 400 KHz

tLOW Clock low period 1.3 μs

tHIGH Clock high period 600 ns

tAA SCL low to data out valid 100 900 ns

tBUF Bus free time before new START 1.3 μs

tHD:STA START condition hold time 600 ns

tSU:STA START condition setup time 600 ns

tHD:DAT Data in hold time 0 μs

tSU:DAT Data in setup time 100 ns

tSU:STO STOP condition setup time 600 ns

tR, tF SCCB rise/fall times 300 ns

tDH Data out hold time 50 ns

Outputs (VSYNC, HREF, PCLK, and D[9:0] (see Figure 5, Figure 6, Figure 7, and Figure 8)

tPDV PCLK[↓] to data out valid 5 ns

tSU D[9:0] setup time 15 ns

tHD D[9:0] hold time 8 ns

tPHH PCLK[↓] to HREF[↑] 0 5 ns

tPHL PCLK[↓] to HREF[↓] 0 5 ns

• VDD: VDD-C = 1.8V, VDD-A = 3.3V, VDD-IO = 3.3V

• Rise/Fall Times: I/O: 5ns, Maximum
AC SCCB: 300ns, Maximum
Conditions: • Input Capacitance: 10pf
• Output Loading: 25pF, 1.2KΩ to 3.3V
• fCLK: 24MHz

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Omni ision Timing Specifications

Timing Specifications

Figure 4 SCCB Timing Diagram

tF tHIGH tR

SCL

tLOW tSU:STO
tHD:STA tSU:DAT

SDA (IN) tSU:STA

tAA tHD:DAT tBUF

SDA (OUT)

tDH 7720CSP_DS_004

Figure 5 Horizontal Timing

tPCLK

PCLK

tPHL tPHL

HREF (row data)

tSU
tPDV

D[9:0] last byte zero first byte last byte

tHD
7720CSP_DS_005

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OV7720/OV7221-CSP2 CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision

Figure 6 VGA Frame Timing

510 x tLINE

480 x tLINE
VSYNC
4 x tLINE 18 tLINE tLINE = 784 tP 8 tLINE

144 tP

HREF
640 tP
64 tP 37 tP 13 tP

HSYNC

D[9:0] invalid data invalid data

row 0 row 1 row 2 row 479

P0 - P639
note 1 for raw data, tP = tPCLK
note 2 for YUV/RGB, tP = 2 x tPCLK 7720CSP_DS_006

Figure 7 QVGA Frame Timing

278 x tLINE

1240 x tLINE
VSYNC
4 x tLINE 22 tLINE tLINE = 576 tP 12 tLINE

256 tP

HREF
320 tP
64 tP 149 tP 43 tP

HSYNC

D[9:0] invalid data invalid data

row 0 row 1 row 2 row 239

P0 - P319
note 1 for raw data, tP = tPCLK
note 2 for YUV/RGB, tP = 2 x tPCLK 7720CSP_DS_007

Figure 8 CIF Frame Timing

VGA HREF
(see figure 6,
VGA frame timing)

CIF HREF
(3 from 5)

VSYNC

7720CSP_DS_008

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Omni ision Timing Specifications

Figure 9 RGB 565 Output Timing Diagram

tPCLK

PCLK

tPHL tPHL

HREF (row data)

tPDV tSU

D[9:2] last byte zero first byte last byte

tHD

first byte second byte

D[9] R4 D[9] G2

D[8] . D[8] .

D[7] . D[7] G0

D[6] . D[6] B4

D[5] R0 D[5] .

D[4] G5 D[4] .

D[3] . D[3] .

D[2] G3 D[2] B0
7720CSP_DS_009

Figure 10 RGB 555 Output Timing Diagram

tPCLK

PCLK

tPHL tPHL

HREF (row data)

tPDV tSU

D[9:2] last byte zero first byte last byte

tHD

first byte second byte

D[9] X D[9] G2

D[8] R4 D[8] .

D[7] . D[7] G0

D[6] . D[6] B4

D[5] . D[5] .

D[4] R0 D[4] .

D[3] G4 D[3] .

D[2] G3 D[2] B0
7720CSP_DS_010

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OV7720/OV7221-CSP2 CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision

Figure 11 RGB 444 Output Timing Diagram

tPCLK

PCLK

tPHL tPHL

HREF (row data)

tPDV tSU

D[9:2] last byte zero first byte last byte

tHD

first byte second byte

D[9] X D[9] G3

D[8] . D[8] .

D[7] . D[7] .

D[6] X D[6] G0

D[5] R3 D[5] B3

D[4] . D[4] .

D[3] . D[3] .

D[2] R0 D[2] B0
7720CSP_DS_011

10 Proprietary to OmniVision Technologies, Inc. Version 1.1, September 1, 2006

Omni ision Register Set

Register Set
Table 6 provides a list and description of the Device Control registers contained in the OV7720/OV7221. For all register
Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 42 for write and 43 for read.

Table 6 Device Control Register List (Sheet 1 of 11)

Address Register Default

(Hex) Name (Hex) R/W Description
AGC – Gain control gain setting
00 GAIN 00 RW Bit[7:0]: AGC[7:0] (see GREEN[7:6] (0x03) for AGC[9:8])
• Range: [00] to [FF]
AWB – Blue channel gain setting
01 BLUE 80 RW
• Range: [00] to [FF]
AWB – Red channel gain setting
02 RED 80 RW
• Range: [00] to [FF]
AWB – Green channel gain setting
03 GREEN 00 RW
• Range: [00] to [FF]
Common Control 1
04 COM1 00 RW Bit[7:2]: Reserved
Bit[1:0]: AGC 2 MSBs, AGC[9:8]
U/B Average Level
05 BAVG 00 RW
Automatically updated based on chip output format
Y/Gb Average Level
06 GAVG 00 RW
Automatically updated based on chip output format
V/R Average Level
07 RAVG 00 RW
Automatically updated based on chip output format
Exposure Value – AEC MSBs
08 AECH 00 RW Bit[7:5]: AEC[15:8] (see register AEC for AEC[7:0]}
Automatically updated based on chip output format
Common Control 2
Bit[7:5]: Reserved
Bit[4]: Soft sleep mode
Bit[3:2]: Pixel clock output delay control
• Range: [00] to [11]
09 COM2 01 RW
Bit[1:0]: Output drive capability
00: 1x
01: 2x
10: 3x
11: 4x
0A PID 77 R Product ID Number MSB (Read only)
0B VER 20 R Product ID Number LSB (Read only)

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Table 6 Device Control Register List (Sheet 2 of 11)

Address Register Default

(Hex) Name (Hex) R/W Description
Common Control 3
Bit[7]: Vertical flip image ON/OFF selection
Bit[6]: Horizontal mirror image ON/OFF selection
Bit[5]: Swap B/R output sequence in RGB output mode
Bit[4]: Swap Y/UV output sequence in YUV output mode
Bit[3]: Swap output MSB/LSB
0C COM3 00 RW Bit[2]: Tri-state option for output clock at power-down period
0: Tri-state at this period
1: No tri-state at this period
Bit[1]: Tri-state option for output data at power-down period
0: Tri-state at this period
1: No tri-state at this period
Bit[0]: Sensor color bar test pattern output enable
Common Control 4
Bit[7:6]: PLL frequency control
00: Bypass PLL
01: PLL 4x
10: PLL 6x
11: PLL 8x
0D COM4 00 RW
Bit[5:4]: AEC evaluate window
00: Full window
01: 1/2 window
10: 1/4 window
11: Low 2/3 window
Bit[3:0]: Reserved
Common Control 5
Bit[7]: Auto frame rate control ON/OFF selection
Bit[6]: Auto frame rate control speed selection
Bit[5:4]: Auto frame rate max rate control
00: No reduction of frame rate
01: Max reduction to 1/2 frame rate
10: Max reduction to 1/4 frame rate
11: Max reduction to 1/8 frame rate
0E COM5 01 RW Bit[3:2]: Auto frame rate active point control
00: Add frame when AGC reaches 2x gain
01: Add frame when AGC reaches 4x gain
10: Add frame when AGC reaches 8x gain
11: Add frame when AGC reaches 16x gain
Bit[1]: Reserved
Bit[0]: AEC max step control
0: AEC increase step has limit
1: No limit to AEC increase step
Common Control 6
Bit[7:1]: Reserved
0F COM6 43 RW
Bit[0]: Auto window setting ON/OFF selection when format
changes

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Omni ision Register Set

Table 6 Device Control Register List (Sheet 3 of 11)

Address Register Default

(Hex) Name (Hex) R/W Description
Exposure Value
10 AEC 40 RW
Bit[7:0]: AEC[7:0] (see register AECH for AEC[15:8])
Internal Clock
Bit[7]: Reserved
Bit[6]: Use external clock directly (no clock pre-scale
11 CLKRC 80 RW available)
Bit[5:0]: Internal clock pre-scalar
F(internal clock) = F(input clock)/(Bit[5:0]+1)
• Range: [0 0000] to [1 1111]
Common Control 7
Bit[7]: SCCB Register Reset
0: No change
1: Resets all registers to default values
Bit[6]: Resolution selection
0: VGA
1: QVGA
Bit[5]: ITU656 protocol ON/OFF selection
Bit[4]: Reserved
12 COM7 00 RW Bit[3:2]: RGB output format control
00: GBR[Link]
01: RGB565
10: RGB555
11: RGB444
Bit[1:0]: Output format control
00: YUV
01: Processed Bayer RAW
10: RGB
11: Bayer RAW
Common Control 8
Bit[7]: Enable fast AGC/AEC algorithm
Bit[6]: AEC - Step size limit
0: Step size is limited to vertical blank
1: Unlimited step size
13 COM8 8F RW Bit[5]: Banding filter ON/OFF
Bit[4]: Enable AEC below banding value
Bit[3]: Fine AEC ON/OFF control
Bit[2]: AGC Enable
Bit[1]: AWB Enable
Bit[0]: AEC Enable

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OV7720/OV7221-CSP2 CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision

Table 6 Device Control Register List (Sheet 4 of 11)

Address Register Default

(Hex) Name (Hex) R/W Description
Common Control 9
Bit[7]: Histogram or average based AEC/AGC selection
Bit[6:4]: Automatic Gain Ceiling - maximum AGC value
000: 2x
001: 4x
010: 8x
011: 16x
14 COM9 4A RW 100: 32x
101 64x
110: 128x
111: Not allowed
Bit[3]: Reserved
Bit[2]: Drop VSYNC output of corrupt frame
Bit[1]: Drop HREF output of corrupt frame
Bit[0]: Reserved
Common Control 10
Bit[7]: Output negative data
Bit[6]: HREF changes to HSYNC
Bit[5]: PCLK output option
0: Free running PCLK
1: PCLK does not toggle during horizontal blank
Bit[4]: PCLK reverse
15 COM10 00 RW Bit[3]: HREF reverse
Bit[2]: VSYNC option
0: VSYNC changes on falling edge of PCLK
1: VSYNC changes on rising edge of PCLK
Bit[1]: VSYNC negative
Bit[0]: Output data range selection
0: Full range
1: Data from [10] to [F0] (8 MSBs)
16 RSVD XX – Reserved
23 (VGA)
17 HSTART RW Horizontal Sensor Size
3F (QVGA)
A0 (VGA) Horizontal Frame (HREF column) end high 8-bit (low 2 bits are at
18 HSIZE RW
50 (QVGA) HREF[1:0])
07 (VGA)
19 VSTRT RW Vertical Frame (row) start high 8-bit (low 1 bit is at HREF[6])
03 (QVGA)
F0 (VGA)
1A VSIZE RW Vertical Sensor Size
78 (QVGA)
Data Format - Pixel Delay Select (delays timing of the D[9:0] data
relative to HREF in pixel units)
1B PSHFT 40 RW
• Range: [00] (no delay) to [FF] (256 pixel delay which accounts for
whole array)
1C MIDH 7F R Manufacturer ID Byte – High (Read only = 0x7F)
1D MIDL A2 R Manufacturer ID Byte – Low (Read only = 0xA2)
1E RSVD XX – Reserved

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Omni ision Register Set

Table 6 Device Control Register List (Sheet 5 of 11)

Address Register Default

(Hex) Name (Hex) R/W Description
1F LAEC 00 RW Fine AEC Value - defines exposure value less than one line period
Common Control 11
Bit[7:2]: Reserved
20 COM11 04 RW
Bit[1]: Single frame ON/OFF selection
Bit[0]: Single frame transfer trigger
21 RSVD XX – Reserved
22 BDBase FF RW Banding Filter Minimum AEC Value
23 DBStep 01 RW Banding Filter Maximum Step
24 AEW 75 RW AGC/AEC - Stable Operating Region (Upper Limit)
25 AEB 63 RW AGC/AEC - Stable Operating Region (Lower Limit)
AGC/AEC Fast Mode Operating Region
26 VPT D4 RW Bit[7:4]: High nibble of upper limit of fast mode control zone
Bit[3:0]: High nibble of lower limit of fast mode control zone
27-28 RSVD XX – Reserved

29 HOutSize A0 (VGA) RW Horizontal Data Output Size MSBs (2 LSBs at register EXHCH[1:0])
50 (QVGA)
Dummy Pixel Insert MSB
Bit[7:4]: 4 MSB for dummy pixel insert in horizontal direction
2A EXHCH 00 RW Bit[3]: Reserved
Bit[2]: Vertical data output size LSB
Bit[1:0]: Horizontal data output size 2 LSBs
Dummy Pixel Insert LSB
2B EXHCL 00 RW
8 LSB for dummy pixel insert in horizontal direction

2C VOutSize F0 (VGA) RW Vertical Data Output Size MSBs (LSB at register EXHCH[2])
78 (QVGA)
2D ADVFL 00 RW LSB of Insert Dummy Lines in Vertical Direction (1 bit equals 1 line)
2E ADVFH 00 RW MSB of Insert Dummy Lines in Vertical Direction
2F YAVE 00 RW Y/G Channel Average Value
30 LumHTh 80 RW Histogram AEC/AGC Luminance High Level Threshold
31 LumLTh 60 RW Histogram AEC/AGC Luminance Low Level Threshold
Image Start and Size Control
Bit[7]: Mirror image edge alignment
Bit[6]: Vertical HREF window start control LSB
32 HREF 80 RW Bit[5:4]: Horizontal HREF window start control LSBs
Bit[3]: Data output bit shift test pattern ON/OFF control
Bit[2]: Vertical sensor size LSB
Bit[1:0]: Horizontal sensor size 2 LSBs
33 DM_LNL 00 RW Dummy Line Low 8 Bits
34 DM_LNH 00 RW Dummy Line High 8 Bits
35 ADoff_B 80 RW AD Offset Compensation Value for B Channel
36 ADoff_R 80 RW AD Offset Compensation Value for R Channel

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Table 6 Device Control Register List (Sheet 6 of 11)

Address Register Default

(Hex) Name (Hex) R/W Description
37 ADoff_Gb 80 RW AD Offset Compensation Value for Gb Channel
38 ADoff_Gr 80 RW AD Offset Compensation Value for Gr Channel
39 Off_B 80 RW Analog Process B Channel Offset Compensation Value
3A Off_R 80 RW Analog Process R Channel Offset Compensation Value
3B Off_Gb 80 RW Analog Process Gb Channel Offset Compensation Value
3C Off_Gr 80 RW Analog Process Gr Channel Offset Compensation Value
Common Control 12
3D COM12 80 RW Bit[7:6]: Reserved
Bit[5:0]: DC offset compensation for analog process
Common Control 13
Bit[7]: Analog processing channel BLC ON/OFF control
3E COM13 F3 RW
Bit[6]: ADC channel BLC ON/OFF control
Bit[5:0]: Reserved
Edge Enhancement Adjustment
Bit[7:4]: Reserved
Bit[3:2]: AD offset compensation option
x0: Use R/Gr channel value for B/Gb
01: Use B/Gb channel value for R/Gr
3F COM14 1F RW
11: Use B/Gb/R/Gr channel value independently
Bit[1:0]: Analog processing offset compensation option
x0: Use R/Gr channel value for B/Gb
01: Use B/Gb channel value for R/Gr
11: Use B/Gb/R/Gr channel value independently
Common Control 15
Bit[7:4]: Reserved
40 COM15 C0 RW
Bit[3]: AD add 128 bit offset
Bit[2:0]: Reserved
Common Control 16
41 COM16 08 RW Bit[7:2]: Reserved
Bit[1:0]: BLC target 2 LSBs
42 TGT_B 80 RW BLC Blue Channel Target Value
43 TGT_R 80 RW BLC Red Channel Target Value
44 TGT_Gb 80 RW BLC Gb Channel Target Value
45 TGT_Gr 80 RW BLC Gr Channel Target Value

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Table 6 Device Control Register List (Sheet 7 of 11)

Address Register Default

(Hex) Name (Hex) R/W Description
Lens Correction Control 0
Bit[7:3]: Reserved
Bit[2]: Lens correction control select
0: R, G, and B channel compensation coefficient is
set by registers LCC3 (0x49)
46 LCC0 00 RW 1: R, G, and B channel compensation coefficient is
set by registers LCC5 (0x4B), LCC3 (0x49), and
LCC6 (0x4C), respectively
Bit[1]: Reserved
Bit[0]: Lens correction enable
0: Disable
1: Enable
Lens Correction Option 1 – X Coordinate of Lens Correction Center
47 LCC1 00 RW
Relative to Array Center
Lens Correction Option 2 – Y Coordinate of Lens Correction Center
48 LCC2 00 RW
Relative to Array Center
Lens Correction Option 3
49 LCC3 50 – G channel compensation coefficient when LCC0[2] (0x46) is 1
R, G, and B channel compensation coefficient when LCC0[2] is 0
Lens Correction Option 4 – radius of the circular section where no
4A LCC4 30 –
compensation applies
4B LCC5 50 RW Lens Correction Option 5 (effective only when LCC0[2] is high)
4C LCC6 50 RW Lens Correction Option 6 (effective only when LCC0[2] is high)
Analog Fix Gain Amplifier
Bit[7:6]: Gb channel fixed gain
4D FixGain 00 RW Bit[5:4]: Gr channel fixed gain
Bit[3:2]: B channel fixed gain
Bit[1:0]: R channel fixed gain
Sensor Reference Control
4E AREF0 F0 RW
• Range: [00] to [FF]
Sensor Reference Current Control
Bit[7:4]: Sensor reference current control
4F AREF1 10 RW Bit[3]: Internal regulator ON/OFF selection
Bit[2]: Reserved
Bit[1:0]: Analog reference control
Analog Reference Control
50 AREF2 30 RW
• Range: [00] to [FF]
ADC Reference Control
51 AREF3 00 RW
• Range: [00] to [FF]
ADC Reference Control
52 AREF4 00 RW
• Range: [00] to [FF]
ADC Reference Control
53 AREF5 24 RW
• Range: [00] to [FF]

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Table 6 Device Control Register List (Sheet 8 of 11)

Address Register Default

(Hex) Name (Hex) R/W Description
Analog Reference Control
54 AREF6 3A RW
• Range: [00] to [FF]
Analog Reference Control
55 AREF7 FC RW
• Range: [00] to [FF]
56-5F RSVD XX – Reserved
60 UFix 80 RW U Channel Fixed Value Output
61 VFix 80 RW V Channel Fixed Value Output
62 AWBb_blk FF RW AWB Option for Advanced AWB
AWB Control Byte 0
Bit[7]: AWB gain enable
63 AWB_Ctrl0 F0 RW Bit[6]: AWB calculate enable
Bit[5]: Reserved
Bit[4:0]: WBC threshold 2
DSP Control Byte 1
Bit[7]: FIFO enable/disable selection
Bit[6]: UV adjust function ON/OFF selection
Bit[5]: YUV444 to 422 UV channel option selection
64 DSP_Ctrl1 1F RW Bit[4]: Color matrix ON/OFF selection
Bit[3]: Interpolation ON/OFF selection
Bit[2]: Gamma function ON/OFF selection
Bit[1]: Black defect auto correction ON/OFF
Bit[0]: White defect auto correction ON/OFF
DSP Control Byte 2
65 DSP_Ctrl2 00 RW Bit[7:4]: Reserved
Bit[3:0]: Scaling control
DSP Control Byte 3
Bit[7]: UV output sequence option
Bit[6]: Reserved
Bit[5]: DSP color bar ON/OFF selection
66 DSP_Ctrl3 10 RW Bit[4]: Reserved
Bit[3]: FIFO power down ON/OFF selection
Bit[2]: Scaling module power down control 1
Bit[1]: Scaling module power down control 2
Bit[0]: Interpolation module power down control
67 DSP_Ctrl4 00 RW DSP Control Byte 4
68 AWB_bias 00 RW AWB BLC Level Clip
69 AWBCtrl1 5C RW AWB Control 1
6A AWBCtrl2 11 RW AWB Control 2
6B AWBCtrl3 A2 RW AWB Control 3
6C AWBCtrl4 01 RW AWB Control 4
6D AWBCtrl5 50 RW AWB Control 5

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Table 6 Device Control Register List (Sheet 9 of 11)

Address Register Default

(Hex) Name (Hex) R/W Description
6E AWBCtrl6 80 RW AWB Control 6
6F AWBCtrl7 80 RW AWB Control 7
70 AWBCtrl8 0F RW AWB Control 8
71 AWBCtrl9 00 RW AWB Control 9
72 AWBCtrl10 00 RW AWB Control 10
73 AWBCtrl11 0F RW AWB Control 11
74 AWBCtrl12 0F RW AWB Control 12
75 AWBCtrl13 FF RW AWB Control 13
76 AWBCtrl14 FF RW AWB Control 14
77 AWBCtrl15 FF RW AWB Control 15
78 AWBCtrl16 10 RW AWB Control 16
79 AWBCtrl17 70 RW AWB Control 17
7A AWBCtrl18 70 RW AWB Control 18
7B AWBCtrl19 F0 RW AWB Control 19
7C AWBCtrl20 F0 RW AWB Control 20
7D AWBCtrl21 F0 RW AWB Control 21
7E GAM1 0E RW Gamma Curve 1st Segment Input End Point 0x04 Output Value
7F GAM2 1A RW Gamma Curve 2nd Segment Input End Point 0x08 Output Value
80 GAM3 31 RW Gamma Curve 3rd Segment Input End Point 0x10 Output Value
81 GAM4 5A RW Gamma Curve 4th Segment Input End Point 0x20 Output Value
82 GAM5 69 RW Gamma Curve 5th Segment Input End Point 0x28 Output Value
83 GAM6 75 RW Gamma Curve 6th Segment Input End Point 0x30 Output Value
84 GAM7 7E RW Gamma Curve 7th Segment Input End Point 0x38 Output Value
85 GAM8 88 RW Gamma Curve 8th Segment Input End Point 0x40 Output Value
86 GAM9 8F RW Gamma Curve 9th Segment Input End Point 0x48 Output Value
87 GAM10 96 RW Gamma Curve 10th Segment Input End Point 0x50 Output Value
88 GAM11 A3 RW Gamma Curve 11th Segment Input End Point 0x60 Output Value
89 GAM12 AF RW Gamma Curve 12th Segment Input End Point 0x70 Output Value
8A GAM13 C4 RW Gamma Curve 13th Segment Input End Point 0x90 Output Value
8B GAM14 D7 RW Gamma Curve 14th Segment Input End Point 0xB0 Output Value
8C GAM15 E8 RW Gamma Curve 15th Segment Input End Point 0xD0 Output Value
Gamma Curve Highest Segment Slope - calculated as follows:
8D SLOP 20 RW
SLOP[7:0] = (0x100 - GAM15[7:0]) x 4/3
8E DNSTh 00 RW De-noise Threshold
Edge Enhancement Control 0
8F EDGE0 00 RW Bit[7:5]: Reserved
Bit[4:0]: Edge enhancement strength control

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Table 6 Device Control Register List (Sheet 10 of 11)

Address Register Default

(Hex) Name (Hex) R/W Description
Edge Enhancement Control 1
90 EDGE1 08 RW Bit[7:4]: Reserved
Bit[3:0]: Edge enhancement threshold control
91 DNSOff 10 RW Auto De-noise Threshold Control
92 EDGE2 1F RW Edge Enhancement Strength Low Point Control
93 EDGE3 01 RW Edge Enhancement Strength High Point Control
94 MTX1 2C RW Matrix Coefficient 1
95 MTX2 24 RW Matrix Coefficient 2
96 MTX3 08 RW Matrix Coefficient 3
97 MTX4 14 RW Matrix Coefficient 4
98 MTX5 24 RW Matrix Coefficient 5
99 MTX6 38 RW Matrix Coefficient 6
Matrix Control
Bit[7]: Matrix double ON/OFF selection
Bit[6]: Reserved
Bit[5]: Sign bit for MTX6
9A MTX_Ctrl 9E RW Bit[4]: Sign bit for MTX5
Bit[3]: Sign bit for MTX4
Bit[2]: Sign bit for MTX3
Bit[1]: Sign bit for MTX2
Bit[0]: Sign bit for MTX1
9B BRIGHT 00 RW Brightness Control
9C CNST 40 RW Contrast Control
9D CNST_ctr 00 RW Contrast Control Center
Auto UV Adjust Control 0
9E UVADJ0 11 RW Bit[7:4]: Auto UV adjust offset control 4 LSBs
Bit[3:0]: Auto UV adjust threshold control
Auto UV Adjust Control 1
Bit[7:3]: Auto UV adjust value
9F UVADJ1 02 RW Bit[2]: Reserved
Bit[1]: Auto UV adjust stop control
Bit[0]: Auto UV adjust offset control MSB
A0 SCAL0 00 RW Scaling Control 0
A1 SCAL1 40 RW Scaling Control 1 – for horizontal scaling control
A2 SCAL2 40 RW Scaling Control 2 – for vertical scaling control
A3 FIFOdlyM 06 RW FIFO Manual Mode Delay Control
A4 FIFOdlyA 00 RW FIFO Auto Mode Delay Control
A5 RSVD XX – Reserved
A6 SDE 00 RW Special Digital Effect Control
A7 USAT 40 RW U Component Saturation Control

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Table 6 Device Control Register List (Sheet 11 of 11)

Address Register Default

(Hex) Name (Hex) R/W Description
A8 VSAT 40 RW V Component Saturation Control
A9 HUE0 80 RW Hue Control 0
AA HUE1 80 RW Hue Control 1
Sign Bit for Hue and Contrast
Bit[7:4]: Reserved
AB SIGN 06 RW
Bit[3:2]: Contrast sign bit
Bit[1:0]: Hue sign bit
DSP Auto Function ON/OFF Control
Bit[7]: AWB auto threshold control
Bit[6]: De-noise auto threshold control
Bit[5]: Edge enhancement auto strength control
AC DSPAuto FF RW Bit[4]: UV adjust auto slope control
Bit[3]: Auto scaling factor control (register SCAL0 (0xA0))
Bit[2]: Auto scaling factor control (registers SCAL1 (0xA1 and
SCAL2 (0xA2))
Bit[1:0]: Reserved
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.

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Package Specifications
The OV7720/OV7221 uses a 28-ball Chip Scale Package 2 (CSP2). Refer to Figure 12 for package information, Table 7 for
package dimensions and Figure 13 for the array center on the chip.

Note: For OVT devices that are lead-free, all part marking letters are
lower case. Underlining the last digit of the lot number indicates
CSP2 is used.

Figure 12 OV7720/OV7221-CSP2 Package Specifications

1 2 3 4 5 6 6 5 4 3 2 1

A A center of BGA (die) =

B optical center B center of the package
C wxyz C
B J2 abcd
D D
E E
F chip center F

S2 J1 350
A
S1

top view bottom view

(bumps down) (bumps up)

note 1 part marking code:

C2 glass die C3 w - OVT product version
x - year part was assembled
y - month part was assembled
z - wafer number
abcd - last four digits of lot number
C1 C4 C
side view 7720CSP_DS_012

Table 7 OV7720/OV7221-CSP2 Package Dimensions

Parameter Symbol Minimum Nominal Maximum Unit

Package Body Dimension X A 5320 5345 5370 µm
Package Body Dimension Y B 5240 5265 5290 µm
Package Height C 845 905 965 µm
Ball Height C1 150 180 210 µm
Package Body Thickness C2 680 725 770 µm
Cover Glass Thickness C3 375 400 425 µm
Airgap Between Cover Glass and Sensor C4 30 45 60 µm
Ball Diameter D 320 350 380 µm
Total Pin Count N 28
Pin Count X-axis N1 6
Pin Count Y-axis N2 6
Pins Pitch X-axis J1 800 µm
Pins Pitch Y-axis J2 750 µm
Edge-to-Pin Center Distance Analog X S1 643 673 703 µm
Edge-to-Pin Center Distance Analog Y S2 728 758 788 µm

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Omni ision Package Specifications

Sensor Array Center

Figure 13 OV7720/OV7221 Sensor Array Center

3984 μm

A1 A2 A3 A4 A5 A6

array center (88.5 μm, 333.6 μm)

2952 μm

package center (0 μm, 0 μm)

sensor
array

OV7720 / OV7221

top view
note1 this drawing is not to scale and is for reference only.
note2 as most optical assemblies invert and mirror the image, the chip is
typically mounted with pins A1 to A6 oriented down on the PCB. 7720CSP_DS_013

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IR Reflow Ramp Rate Requirements

OV7720/OV7221 Lead-Free Packaged Devices

Note: For OVT devices that are lead-free, all part marking letters are
lower case

Figure 14 IR Reflow Ramp Rate Requirements

300.0
Z1 Z2 Z3 Z4 Z5 Z6 Z7 end
280.0
260.0
240.0
220.0
200.0
temperature (C)

180.0
160.0
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0 0.0 0.6 1.1 1.6 2.2 2.8 3.3 3.9
-22 -2 18 38 58 78 98 118 138 158 178 198 218 238 258 278 298 318 338 358 369
time (seconds)

-0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
time (minutes) 7720CSP_DS_013

Table 8 Reflow Conditions

Condition Exposure

Average ramp-up rate (30°C to 217°C) Less than 3°C per second

> 100°C Between 330 - 600 seconds

> 150°C At least 210 seconds

> 217°C At least 30 seconds (30 ~ 120 seconds)

Peak temperature 245°C

Cool-down Rate (peak to 50°C) Less than 6°C per second

Time from 30°C to 245°C No greater than 390 seconds

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Note:

• All information shown herein is current as of the revision and publication date. Please refer
to the OmniVision web site ([Link] to obtain the current versions of all
documentation.

• OmniVision Technologies, Inc. reserves the right to make changes to their products or to
discontinue any product or service without further notice (It is advisable to obtain current product
documentation prior to placing orders).

• Reproduction of information in OmniVision product documentation and specifications is

permissible only if reproduction is without alteration and is accompanied by all associated
warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible
or liable for any information reproduced.

• This document is provided with no warranties whatsoever, including any warranty of

merchantability, non-infringement, fitness for any particular purpose, or any warranty
otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision
Technologies, Inc. disclaims all liability, including liability for infringement of any proprietary
rights, relating to use of information in this document. No license, expressed or implied, by
estoppels or otherwise, to any intellectual property rights is granted herein.

• ‘OmniVision’, ’VarioPixel’ and the OmniVision logo are registered trademarks of OmniVision
Technologies, Inc. ’OmniPixel2’ and ’CameraChip’ are trademarks of OmniVision Technologies,
Inc. All other trade, product or service names referenced in this release may be trademarks or
registered trademarks of their respective holders. Third-party brands, names, and trademarks are
the property of their respective owners.

For further information, please feel free to contact OmniVision at info@[Link].

OmniVision Technologies, Inc.

1341 Orleans Drive
Sunnyvale, CA USA
(408) 542-3000

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Omni ision TM

REVISION CHANGE LIST

Document Title: OV7720 Datasheet Version: 1.0

DESCRIPTION OF CHANGES
• Initial Release
Omni ision TM

REVISION CHANGE LIST

Document Title: OV7720 Datasheet Version: 1.01

DESCRIPTION OF CHANGES
The following changes were made to version 1.0:
• Under Key Specifications on page 1, changed Temperature Range from “TBD” to
“-20°C to +70°C”
• In page 5, added Table 2, Operating Conditions
• In Table 4 on page 5, changed table title from “DC Characteristics (-30°C to 70°C)”
to “DC Characteristics (-20°C to 70°C)”
• In Table 5 on page 6, changed table title from
“Functional and AC Characteristics (-30°C < TA < 70°C) to
“Functional and AC Characteristics (-20°C < TA < 70°C)”
Omni ision TM

REVISION CHANGE LIST

Document Title: OV7720 (CSP2) Datasheet Version: 1.1

DESCRIPTION OF CHANGES
The following changes were made to version 1.01:
• On page 1, changed datasheet title from “OV7720 Color CMOS VGA (640x480)
CAMERACHIP™ Sensor with OmniPixel2 Technology” to “OV7720/OV7221 CMOS
VGA (640x480) CAMERACHIP™ Sensor with OmniPixel2 Technology”
• Under Ordering Information on page 1, changed part number from “OV07720-VL2A” to
“OV07720-VL1A”
• Under Ordering Information on page 1, added part number “OV07221-VL1A”
• Changed “OV7720” to “OV7720/OV7221-CSP2” in the header of every even numbered
page.
• Changed “OV7720” to “OV7720/OV7221” in multiple places throughout the datasheet