Program Interrupt |Interupt Cycle

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 Program Interrupt

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• In basic case(Programmed Control Transfer), The computer keeps

checking the flag bits(FGI,FGO), and when it finds it set, it initiates an
information transfer (this is sometimes called Polling)

• This type of transfer is in-efficient due to the difference of information

flow rate between the computer and the I/O device

• The computer is wasting time while checking the flag instead of doing
some other useful processing task

• An alternative to the programmed controlled procedure is to let the

external device inform the computer when it is ready for the transfer

• This type of transfer uses the interrupt facility

 Program Interrupt

• While the computer is running a program, it does not check

the flags
• Instead:
• When a flag is set, the computer is immediately
interrupted from proceeding with the current program
• The computer stops what it is doing to take care of the
input or output transfer
• Then, it returns to the current program to continue what it
was doing before the interrupt

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 Program Interrupt
• The interrupt facility can be enabled or disabled via a flip-flop
called IEN

• The interrupt enable flip-flop IEN can be set and cleared with two
instructions (IOF, ION):
• IOF: IEN  0 (the computer cannot be interrupted)
• ION: IEN  1 (the computer can be interrupted)

• Another flip-flop (called the interrupt flip-flop R) is used in the

computer’s interrupt facility to decide when to go through the
interrupt cycle
• So, the computer is either in an Instruction Cycle or in an
Interrupt Cycle
• The interrupt cycle is a hardware implementation of a branch and
save return address operation (BSA
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 Interrupt Cycle
R = Interrupt flip-flop
• When interrupt flipflop R=0 computer
Instruction cycle =0 =1
R
Interrupt cycle undergoes instruction cycle
Fetch and decode Store return address • At execution phase IEN is checked if it is 0
instructions in location 0
M[0]  PC continues with next instruction cycle
Execute IEN =0 • If it is 1 flag bits are checked.If both are 0
instructions Branch to location 1
=1
=1
FGI
PC  1 continues with next instruction cycle
=1
=0
IEN  0 • If either flag is set 1 when IEN=1 then R is
FGO
=0
R 0
set to 1 and control goes to an interrupt
R1
cycle

Flowchart for interrupt cycle

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 Interrupt Cycle
• Interrupt cycle is a hardware
R = Interrupt flip-flop implementation of a branch and save
Instruction cycle =0
R
=1
Interrupt cycle return address operation
Fetch and decode Store return address
• Return address in PC is stored in specific
instructions in location 0
M[0]  PC
location (address 0)
Execute
instructions
IEN =0 • Control inserts address 1 to PC and clears
=1
=1 Branch to location 1
PC  1 IEN and R so that no more interruptions
FGI
=0
can occur until interrupt request serviced
=1
FGO
IEN  0
R 0
and flag is set
=0
R1 • Microoperations
• RT0:AR← 0,TR ←PC
• RT1:M[AR] ←TR,PC← 0
Flowchart for interrupt cycle • RT2:PC← PC+1,IEN← 0,R← 0,SC ←0
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