User Interface

allegro Allegro
Allegro PCB Layout

A.

Allegro

? Padstack Designer
Padstack Designer Pad
? DB doctor
DB doctor
1. Data-base
2. Data-base
3. DRC
.brd .mcm .mdd .psm .dra .pad and . sav databases.

B. Cadence SPB Tools

PCB Designer V16.5 2 Tool
option (Onlyfor Allegro)
Allegro PCB Designer HDI Options
OrCAD PCB Designer
Allegro
 License
Option
PCB High-Speed option
Miniaturization option HDI
File Change Edit

C. Allegro
Allegro
Extension File Type
.brd Board/Substrate file that represents the drawing database
.dra Drawing file. You must create one of these before you create a
symbol file. Later,
this file is compiled into a binary symbol file.
.pad Padstack file

.osm Library file that stores format symbols

 .psm Library file that stores package/part symbols

.bsm Library file that stores drawing or board/substrate symbols

.fsm Library file that stores flash symbols
.ssm Library file that stores shape symbols
.mdd Library file that stores module definitions
.drl Output text files that contain NC drill data
.txt Text file, such as that used for parameters
.scr Script and macro files
.log Log file that contains data on processes
.art Artwork files
.dat Data files
.jrl A journal file which contains a record of events -- menu picks,
keyboard activity, and
so on -- which are recorded for each session in Allegro/APD. You
can share this
data with Cadence Usability staff to help us learn how you use the
product, which
will assist us in our efforts to improve the user interface.

D. Allegro
Allegro
C:\Cadence\SPB_16.6

C:\SPB_DATA
D:\WORK

* Win XP \Documents and Settings

E.
Allegro
Change
Directory
F.
Allegro

G. Allegro
 Allegro Allegro

Allegro
Allegro

# View > Customazation > Toolbar

 File File

File

Commands Buttons

H.
? Options Folder Tab
command
? Find Folder Tab (Find Filter)

? Visibility Folder Tab

? World View Window

#World View Window

? Move Display

? Resize Display
? Find Next
? Find Previous
XY
Snap to current grid
Relative (from last pick):
A
R

CMD :
1.
2.
3. Stop Esc

:
View > Windows Control Panel

I. Options Window
Options window
Options
 J.
Find
Find Allegro Find Find
Filter Element
Element
Element
 Design Object Find Filter

All On All Off Name

K. Visibility

Views

1. Last View Show

2. Film ... Show Artwork
3. File Show color
 View > Color View Save

Save view
Complete save
*.color
Views route route

L.

LMB LMB
RMB RMB Pop-Up
Menu stork
Shift Shift+RMB CMB
( middle mouse
wheel)
#

M.
# View>Zoom

Zoom In

Zoom Out

Zoom by Points
Zoom Fit board outline
Zoom World Drawing Extents size
Zoom Center x,y

Zoom Previous

Refresh
 Setup > User Preferences Categories
Input no_dynamic_zoom OK
Zoom In Zoom Out Zoom In Zoom Out
N.

Key Command Key Command

F1 Help
F2 Zoom Fit SF2 Property Edit
(available)
F3 Add Connect SF3 Slide
F4 Show Element SF4 Show Measure
(available)
F5 Redisplay SF5 Copy
F6 Done SF6 Move
F7 Next SF7 Dehilight All
F8 Oop SF8 Hilight Pick
F9 Cancel SF9 Edit Vertex
F10 Grid SF10 Save_as temp
(available)
 F11 Zoom In SF11 Zoom Previous
(available)
F12 Zoom Out SF12 Zoom World
(available)
SF2 Shift F2

alias

F2 Add connect

a b c
a. alias
b.
c.

F2 F12 Insert Home Page Up Delete End Page

Down

Ctrl Alt Shift Ctrl Alt Ctrl Shift Shift Alt Ctrl Alt Shift
Ctrl

F1 Help

O. Strokes
Strokes
Layout

Ctrl

Ctrl User Preferences

Setup > User Preferences Categories Input

no_dragpopup OK

P. Application Mode
 Setup/Application Mode, General,Placement,Etch,Flow Planning,Siginal
Interity,None

# General Edit Mode

# Etch Edit Mode

 # Placement Edit Mode

(2) Graphical User Interface

Placement Edit Options
Place By refdes: U* R*
(3) Context-Sensitive Editing
Placement Edit MODE

Q. Color
Color Layers Nets Layer Net

1. Layer class subclass folder

 Color Stipple patterns

2. Net
NET pins, vias, clines, shapes, and ratsnests
bus, diff pair, Xnet and net objects
Display/Color/Vibilitily
(1) net color Addr_bus Rats ,
Clk_Out
, A1~A7 Rats , :
(2) Clk_Out highlight Dehighlight :

(3) Type Filter net net color

All: net net color

Net: net net color
Bus: Bus net color
Xnet: Xnet net color
Diffpair: Diffpair net color
(4) Show only nets with color override color net
net :
- color net net color
- net color net color
(5) sort net net color list :

Ascending:
Descending:
Overrides on top: color net
Overrides on bottom: color net
(6) Disable custom colors net color color
:
net color net color .
color
layer
net color net color

(7) clear all nets net color

3. color palette
color palette
(1) Color Dialog box hide palette color palette
(2) color palette show palette

4. Color Dialog stipple pattern color

(1) color Dialog layer stack-up top stipple pattern
(2) allegro Etch top stipple pattern

R. 3-D Viewer
3-D Viewer allegro board file 3-D 3-D Viewer PCB
Editor Products
OpenGL APD/SiP
1. 3-D viewer menu View 3D view Icon

2. 3-D viewer 3-D environment

3. pre-selection 3-D HDI via

isolated sections 3D
4. 3D 3D

S. Flip Design
Flip design Y PCB
1. Flip design OpenGL Viewer
2. Flip Design menu View Flip Design Icon

T. Script
Script
 :
1. File Script
2. File Name
3. Record
4.
5. Stop
*.scr, command Replay :Replay [Link]

U. Embedded Net name

Cline, Pins, Shapes
Open GL Setup Design Parameters Display
form.

shape Cline net name

 pad net name

V. Env
ENV Allegro Allegro Env Set
Command User
Preference
allegro env file
1. <home>:\pcbenv\env file
2. Cadence\spb_16.6\share\pcb\text\env file (env_local.txt)
# Home

W. Skill File
# Skill File
Skill file Cadence Cadence Skill files
[Link] maintenance Cadence
Skill .il ([Link])
Skill file <home-dir>\pcbenv\ [Link] skill file
skill file ;
setSkillPath(buildString(append1(getSkillPath() "D:/skill")));
load("[Link]");
D:/skill : skill file D skill skill files

load : Allegro skill file .

# skill command :
skill file Allegro command . skill file
axlCMDRegister( XXX ) XXX Allegro command .

X. Getting Help
Allegro
# WinHelp F1 or
# [Link]
[Link]
# (CRC):0800-241-256
# Online service [Link]
[Link]

Padstacks
Allegro Padstack Designer Padstack Editor
Pad Pad

A. Anatomy of a Padstack

Pad Mask Layer, Signal Layer, Plane Layer

Mask Layer Soldermask( ) ,Pastemask ( ) Filmmask( ,
 ) Non-etch
Signal Layers ETCH
Plane Layers VCC Gnd Allegro
shape shape

Signal Layers Plane Layers Etch

Signal Layers padstack Regular pad Plane Layers Thermal Relief
pad flash symbol
Anti-pad

B. Pad
Pad
Regular pad

Thermal Relief pad plane

flash symbol Thermal Relief pad plane

plane

plane

Anti-pad plane
pad plane
pad
plane
Shape-pad

C. Pad
Pad Pad
Pad Pad shape symbol flash symbol

D. Shape Symbol
shape symbol
pad Pad( pad )
 shape symbol

shape symbol

a.
Setup>Drawing Size

PCB
mil mil
2

Move Origin X Y

shape symbol type shape

Size Other
Width Height
A B C D
A1 A2 A3 A4

OK
b. File>New
 Drawing Type Shape symbol
c. Drawing Name shape symbol
d. OK Shape symbol

e. , control panel Option ,

Shape Symbol

f. move Body Center, 0,0 .

g. File>save *.dra
h. File>Create symbol *.ssm PCB
Allegro
Setup/User Preference
Note: *.dra , *.ssm
Shape Symbol Pad
*.*SM Symbol dra

File/Create Symbol

E. Parameterized Rectangular shapes

shape shape shape corner

corner
1 shape

2 corner
Orthogonal 90
Chamfer 45
Round

3 shape Rectangular shape

F. Shape Expand/Contract
General Edit shape shape
Expand/Contract Option panel

G. Flash Symbol
Flash symbol
Flash Symbol

a. Setup>Drawing Size
b. File>New

c. Drawing Type Flash Symbol

d. Drawing Name shape symbol tr x x x

e. OK Shape symbol
f. control panel Option

g. Add>Flash Flash
h. ok Flash symbol

i. File>save *.dra
dra i Shape Symbol

j. File>Create symbol *.ssm PCB

TR60x44x10x45 Flash Symbol

Thermal = 60 mils
= 44 mils
= 10 mils
= 45 ?
a.
b. File>New
c. Drawing Type Flash Symbol
d. Drawing Name TR60x44x10x45
e. OK Shape symbol
f. control panel Option

g. Add>Flash Flash

h. ok flash
i. File>save *.dra
j. File>Create symbol *.fsm PCB

Flash Symbol Pad

H.
Symbol Pad

Allegro Pad Pad

 Pad
(1) Pad

Type pad
Etch layers
Mask layers
Single Mode
(2) Pad

Microvia :
Microvia, create via microvia; create via
Allow suppression of unconnected internal pads :
Artwork pad
Artwork Pad
Enable Antipads as Route Keepouts(ARK) :
, Mechanical Pin, antipads route keepout
, Mechanical Pin, antipads route keepout

(3)

mil 2 2

(4)
Enabled Pad drill 1
Rows Columns

Rows Columns drill 2 TOP View

Pad

Clearance Drill Drill

(5) Drill

#Hole type:
[Link] drill:
[Link] slot:
[Link] slot:
#Plating:
[Link]:Drill hole
[Link]-Plated:Drill hole
[Link]:Drill hole
Circle drill Oval slot Rectangle slot

(6) NC Drill

figure:
Character:
Width/Height:
Pad

(1) Single layer mode pad type

Single layer mode, pad SMD
Single layer mode, pad :via
(2) BEGIN LAYER 3
Regular, Thermal Relief, Anti Pad Regular Thermal Relief Anti
Pad

Geometry

Circle:
Square:
Oblong:
Rectangle:
Octagon:
Shape: Shape

(3) Width Height Pad

(4) Thermal Relief

Flash symbol
:TR_80_60 flash symbol fsm
(5) Pad Top

(6)

layer .

(7) top copy

2 - 16

(8) copy to all

Soldermask Top Soldermask

(9)

(10) File>save save as *.pad Pad

I. Padstack

(1) Design
Layout Tools/Padstacks/Modify Design Padstack
 Options Tab
Padstack Padstack Pad
Padstack
(2) Padstack
Allegro Padstack Editor Padstack

File/Open Padstack

Component Symbols
Allegro

A.

Package Symbol *.psm footprint

dip14 soic14 R0603 C0805
Mechanical Symbol *.bsm
outline
Format Symbol *.osm Logo assembly
Shape Symbol *.ssm pad
Flash Symbol *.fsm thermal relief
B. ( )
Package symbol

Example Dip16 Package Symbol Wizard

a. Pad
b. Allegro File>New

c. Drawing Type Package Symbol Wizard

d. Drawing Name Dip16 OK

Package Symbol Wizard

e. dip
smd soic
Dip Next
f. Cadence

Cadence

Load Template Next

g. Wizard
Datasheet mil 2 Package
symbol mil 2, Reference U* R* C*
U* Next

h. Pin
Number of pins Dip16 Pin 16
Lead pitch e
100mil
Terminal row spacing pin e1
Package width E
Package length D
Next

i. Pad

Default padstack to use for symbol pins padstack

Pad
Dip16 Pin Pad60cir36d
Padstack to use for pins 1 Pin1
Pin

pin Pin Dip16 Pad Pin1 padstack

pad Pad60sq36D Pin1 Pin

pin Pad Next

j. symbol origin *.psm

*.dra *.psm *.dra
1. Center of symbol origin origin
2. Pin 1of symbol pin origin
Create a compiled symbol *.dra *.psm
Do not create a compiled symbol *.dra *.psm
File>Create symbol
Next
k. (*.dra,*.psm) Finish
Dip16
Component outline Labels

l. File/Create Device Device

(Netin)

C.
Example soic14 package symbol

(1) (Padstack)
(2) Assembly outline Silkscreen outline
(3) Labels Device RefDes Value Tolerance Part Number
(4) Package Boundary Via keepout

(1) Padstack
a. Allegro File>New New Drawing

b. Drawing Type Package

Symbol
c. Drawing Name soic14
d. OK Package Symbol
e. Setup/Drawing Size

f. Layout>Pin Add Pin Pin

Control Panel Options

Connect pad
Mechanical Mechanical pad
soic14 Connect
Padstack Pad Pad
Pin1 Pin 2 Pin
 Pin1 Pin
Copy mode Padstack
Rectangular Polar

Rectangular soic14
Polar Pin
Pin Pin
Allegro Pin

#Qty: pin
#Spacing: pin
#Order:
Soic14 14 Pin X ______ Qty 7 Pin
Pin 100mil
Pin 7 Pin
Rotation 0

Pin
Pin Pin 1
Inc Pin 1

1 2

Pin number Pin

0 0 Pin

100 0 Pin 100mil

 soic14

Rectangular

pad 14 Pin

(2) Assembly outline Silkscreen outline

a. Add
Control Panel

Add Line Arc

Line
Arc w/Radius
3pt Arc
Circle
# Line Arc
(3) Package Boundary Via keepout
a. Package Boundary
Setup>Areas>Package Boundary
PACKAGE GEOMETRY
ASSEMBLY_TOP copy Package Boundary
shape

1. Setup>Areas>Package height , shape Options

Min height
Max height
Max height

2. Edit>property shape
 show shape

(4) Labels Device Refdes Value Tolerance Part

Number

a. Layout>Labels>RefDes RefDes REFDES

ASSEMBLY_TOP
U* R*
b. Layout>Labels>Device Device Device
ASSEMBLY_TOP
c. Layout>Labels>Value Value Value
ASSEMBLY_TOP
d. Layout>Labels>Tolerance Tolerance Tolerance
ASSEMBLY_TOP
e. Layout>Labels>Part Number Part Number Part
Number ASSEMBLY_TOP

Note:
RefDes

(5)
Note: save *.dra
[Link]
Create symbol *.psm ,
[Link]
no_symbol_onsave dra
psm
Setup/User Preference Drawing
Shape Symbol

(6) File/Create Device Device

D. Jumpers
allegro jumper
board file jumper
1. jumper

(1) allegro File New Drawing Type

Package symbol
jumper jumper

(2) Set up Design Parameters, Design

Jumper

(3) Add Connect 100 mils Jumper ,

0,0 100,0 via
(4) jumper Add 3pt Arc Package Geometry
Silkscreen_Top

(5) jumper place boundary shape Package Geometry

Place_Bound_Top place boundary
(5) jumper label Layout Labels RefDes RefDes

Silkscreen_Top label:jumper*

(7) File Save jumper

2. board file jumper

(1) board file drawing level JUMPER_LIST
jumper footprint
(2) jumper footprint
(3) Route-Connect, jumper

(4) Add jumper jumper jumper

jumper footprint
name jumper footprint name
(5) jumper pin jumper mirror
rotate jumper board file

(6)
E. Import/Export csv file
csv Pin

1. csv allegro File Import CSV Pin File

2. CSV pin file
CSVpin file
pin
3. csv pin file symbol editor File

Export CSV Pin File

F. Auto Re-pinning
pin

1. symbol editor Layout Renumber Pins

2. renumber pin
renumber
 Importing Logic
allegro Netlist Allegro
Capture Allegro Capture

A.
Netlist Allegro Layout
Netlist Capture
Netlist Allegro Layout
1. Orcad Capture
2. OrCAD Capture Netlist
3. Netlist Allegro PCB Designer layout
4. Allegro PCB layout
5. Allegro back annotate Logic layout
Logic OrCAD Capture
Netin
( ) Capture netlist PCB Editor Allegro
DesignEntryCIS(Capture)
( ) Capture netlist Other [Link]
Allegro Other ( 10.5
[Link]
[Link] )
Device File Device File
Device Pin

PACKAGE PSM PCB Footprint (

DIP14,SO8, C0402)
CLASS (for example, IC, discrete)
PINCOUNT Pin
PINORDER
PINUSE Pin (for example, INPUT,OUTPUT)
PINSWAP Swap Pin
FUNCTION Swap FUNCTION
POWER Pin
GROUND Pin
NC Pin
PACKAGEPROP TOL
PACKAGEPROP VALUE
END
 B. Capture
Capture layout

layout pin Functions swap

(1)
Netlist Symbol

Swap Pin
1.
2. Edit>Part
3. View>Package
4. Edit>Properties
 Swap Pin PinGroup swap Pin
PinGroup
Pin1 2 3 PinGroup 1 Pin4 5 6
PinGroup 2 Pin1 2 3 swap Pin4
5 6 swap

Swap Functions
Functions Gate

1. New>Library

2. Library Design>New Part

Edit Part Properties
Homogeneous Swap Function

3. Parts properties Functions

7400_0 Gate layout
Swap Functions
Device File
Netlist netlist
Device File
PACKAGE CLASS PINCOUNT END
DDR184
 PINSWAP FUNCTION Gate

Device File Function Gate D0~D7 Pin PinSwap

Function Gate Pin
Gate layout
Device File layout Swap

(2) PIN
Netlist Power pin
1.
2. Edit>Part
3. Pin
4. Edit>Properties

Type Power Allegro PCB Editor

netlist Pin Name netlist Type
Power Power Pin
 Add Property
(3) Capture Constraints
1.
2. Edit>Properties

Footprint
soic16 Allegro
Reference Value Property

C. Netlist
(1) Capture netlist PCB Editor
1. Netlist

2. Tool>Create Netlist Create Netlist ,

PCB
Editor
 Create PCB Editor Netlist Netlist , netlist

Create or Update PCB Editor Board netlist

netlist
Note
Allow etch removal during Eco netlist
ETCH
Place changed netlist
Always
If same symbol
Never netlist
Board Launching Option layout PCB
Design None netlist layout
Allegro

(2) Capture netlist Other

1. Tool>Create Netlist Create Netlist
2. Other
 other netlist
OrCAD 9.2 [Link]
netlist
OrCAD 9.2 [Link]
C:\Cadence\SPB_16.6\tools\capture\netforms
{Value} !{PCB Footprint} Netlist
Device Value
Reference netlist
PCB Footprint {

Allegro netlist :

PCB Footprint Device Value Tolerance Reference

Device Reference
Netlist Device
PCB Footprint Device Pcb footprint
Device PCB Footprint
, PCB Footprint
Device Value Reference,
D. Netlist Allegro
netlist
1. Allegro
2. Netlist File>Open
3. File>Import>Logic Netlist

4. Cadence netlist

5. Import directory netlist

6. Import Cadence Netlist

Note
# Import logic type Design Entry HDL Design Entry HDL
CIS(Capture) SCALD
netlist file
# Place changed component netlist

# Always :
# Never netlist
# If same symbol :

4 - 13
# HDL Constraint Manager Enabled How options
Constraint
Allegro Cadence HDL

# Import Changes Only constraints

constraints
# Overwrite current constraints constraints

constraints
# Allow etch removal during ECO: netlist
ETCH
# Ignore FIXED property : Fixed Property Pass
fixed
# Create user-defined properties : Netlist

# Create PCB XML from input data: XML

boardname_sch.xml.
Design Compare
# Design compare : Allegro Netlist XML
board
Netlist XML
netlist
Other Capture Other Netlist other

1. Allegro
2. Netlist File>Open
3. File>Import>Logic Netlist
4. Other netlist
Import netlist netlist

Import Other Netlist

Note
netlist Netlist netlist
netlist
Netlist
# Syntax check only : Netlist Netlist
# Supersede all logical data : Netlist
# Append device file log Device Log Log
# Allow etch removal during Eco netlist ETCH
# Ignore FIXED property : Fixed Property Pass Netin
,fixed

# Place changed component netlist

# Always :
# Never netlist
# If same symbol :

Creating Board
Allegro PCB Layout

Allegro

A. Board Wizard

1. File>New

2. Drawing Name :card

3. Drawing Type Board(Wizard)
4. OK Board(Wizard)
 Board Wizard
1. Next

-
-
-
-
-
2.
Yes Next

3. tech file Parameter

Next
4. board symbol
board symbol
Next

5.
 Units
Other

Specify The location of the origin for this drawing

- At the lower left corner of the drawing

- At the center of the drawing

Next
6.

Grid spacing

Setup>Grid
Etch layer count
Power Top, Bot, Gnd,
Pow 4
Do you want the default definitions of artwork films for these layers to be
generated?
Etch layer count
- Generate default artwork films

- Don t generate artwork films

Next
7.
Layer name
Top Bottom
Layer type
Routing layer
Powerplane Generate negative layers for Power planes
Power plane layer
,
Next
8.
Padstack

Minimum Line width

Minimum Line to Line spacing
Minimum Line to Pad spacing Padstack
Minimum Pad to Pad spacing Padstack Padstack

Default via padstack

Next
9.

Circular board
Rectangular board
Wizard
Mechanical Symbol
Mechanical Symbol
Next
10_1. Circular board

10_2 . Rectangular board

Width Height
Cut length

( Corner cutoff )
Route keepin distance

Package keepin distance

Note
Route keepin

Package keepin

Next
11. Board Wizard
 Finish

B.

1. File>New
2. Drawing Name test
3. Drawing Type Board
4. OK Board

Drawing Size

Setup> Cross-section

DRC
Total Thickness

Add Layer Above

Add Layer Below
Remove
Material

FR-4 Copper
Layer Type

Subclass Name

Negative Artwor k

Setup>Grid
Grid on

Non-Etch

Offset 0,0
All etch TOP
VCC GND BOTTOM

C. Outline

10000 12000
1. Add>Line
2. Control Panel Options Class Board Geometry
Sub-class Outline
3.
Command
X00 x 0 y 0
X 10000 0 x 10000 y 0
X 10000 12000 x 10000 y 12000
X 0 12000 x 0 y 12000
X00
10000 12000

Note
Manufacture > Dimension/Draft > Chamfer

Manufacture > Dimension/Draft> Fillet

Radius

4. Dxf shape
Shape/Compose Shape
D. Route keepin Package keepin
1 Setup>Areas> Route keeping Package keepin
2 Outline Route keepin Package keepin
outline

1 Edit>Z-copy
2 Control>Option
Options Form
Copy to Class/Subclass Package
Keepin>All Route keepin>All
Shape Options
- Copy Voids Netname shape Voids
Netname Etch shape
- Size Contract Expand shape
Offset 0
Route keepin Package keepin outline Contract
Offset
outline Route keepin Packagekeepin

Note
Z-Copy Outline shape
Control>Find Shape
Outline Line

Control>Find Line

E. Mechanical Symbol
Mechanical Symbol

1 File>New New Drawing

2 Drawing Name Test
3 Drawing Type Mechanical Symbol
4 OK Mechanical Symbol

Drawing Size
Outline

F. Associative Dimensioning
Allegro dimension dimension
dimension
dimension

1. :
Manufacturing - Dimension Environment
Dimension Edit command

2. 16.5 dimension

dimension
dimension
dimension
16.5 dimension
3. delete dimensions dimension
dimension
4. move text edit leader dimension
5. Y dimension Y
Lock dimensions

6. text

%v
%u MM In

7. change text
8. Z-move dimension

Board Geometry
Dimension
Assembly Notes
Any user defined subclass
Drawing Format
Any user defined subclass
Manufacturing
Any user defined subclass
9.
dimension
 dimension

Placement

Netlist File Allegro

A.

50mils
 Setup >Grids Placement
Non Etch Spacing 50

B. Placement

Place>manually

Placement List netlist PCB

PCB

Graphics Text
Note
List 4 4 Components by Refdes
netlist
database Mechanical symbol Format symbol Library

C. Placement
1. Place>Quickplace

PCB

Placement

Edge
Top Bottom

2. Place OK

netlist
outline
PCB
3. RefDes , Move Find
Find by Name RefDes

4.

Quickplace Overlap controls

quickplace

D. Align Components

Placement Application mode align components

1. application mode Placement Edit

2. Shift or Ctrl

3. SHIFT

Align component
Note:

1.
2.
DFA Constraint
E. Snap to Object

: pin mechanical

drawing Testpoint Figure

Snap

MOVE COPY

Snap pick to
 slide

move , pin mechanical drawing :

F. Placement Replication

placement Placement Replication

placement
Placement Replication Placement Edit Mode
:

1. Module Placement
 Place replicate create

2.

, Graser Module Definition File

(.mdd)

2.

Place replicate apply SAVE Graser

4.

G. Component Placement Applications

1. Placement Replication enhanced to support Interconnects

Placement replication etch Placement replication

(1) Allegro Placement Edit Mode

(2) Module Place

Replicate Create.
( Placement Mode )
(3) High light Module Etch ,
Done
(4) Module Module

(5) Module Module

(6) Place replicate apply
SAVE CHANNEL

(7)

(8)

Replicated Circuits
2. Moving Replicated Circuits as a Group
(1) Replicated Circuits group
(2) Replicated Circuits
Super Filter Module Replicated Circuits
Move
Move Find Filter group
Replicated Circuits
3. Locking the Circuits
(1) Circuits Circuits
Circuits
group
(2) group locked

4. Aligning Modules and Replicated Circuits

Modules Replicated Circuits

Modules Replicated Circuits

(1) Placement Edit Mode

(2) Modules
(Replicated Circuits)
(3) Modules Replicated Circuits Align
modules.

5. Update Replicated Circuits

(1) Replicated Circuits layout
Update Replicated Circuits
Replicated Circuits
(2) Update Replicated Circuits
- Fine filter Group
- Replicated Circuits Update Replicated
Circuits
- Done Replicated Circuits

- Replicated Circuits Module

6. ECO Changes to Circuits

logic Replicated Circuits
Place replicateapply placement
7. Disband Replicated Circuits
(1) Disband Group database group/module

(2) Replicated Circuits

- super Filter module replicated circuit

- Disband Group

8. Move Components one grid unit with Arrow Keys

(1) location
(2) location
- update env file env file
- Allegro Pre-selection None

(3) location
- allegro Pre-selection
- Shift Arrow keys
Arrow key grid
9. Change pick point during Move operation
(1) move pick point
(2) pick point

- User pick Rotation Point User pick

Change user pick move pick point

- Symbol Pin Options Rotation Point
Symbol Pin New
Enter New Value

10. Create/Disband Groups in Pre-Selection mode

(1) General Edit and Placement Edit group.
(2) General Edit and Placement Edit group.

- group Add to group.

- group graser OK

(3) General Edit and Placement Edit group

- disband group Disband group

11. Move command update

Move mirror ( ) mirror

 Constraints
Allegro Design Check Rule

Spacing Physical
Waive DRCs
Constraints Manager

, :
Setup > Constraint Manager
Setup > Constraint Manager > Physical
Setup > Constraint Manager > Spacing
Setup> Constraint Manager > Same Net Spacing

Constraint Manager Left Pane

Constraint Manager Work Area

A. Physical rules
Via :
1. Setting the Default Physical Rules Physical Constraint Set
Default Physical Line Width Neck width

2. Defining the Special Physical Rules

 Constraints Set Dsn Create Physical CSet

3. Assigning the Net Class

Referenced Physical CSet

B. Spacing rule set

:
1. Setting the Default Spacing Rules
Spacing Constraint Set Default

2. Defining the Special Spacing Rules

Default Create Spacing CSet

3. Assigning a Net Class

Referenced Physical CSet
4. Setting Class-Class Rules
Class-Class
Net Class-Class Create Net class-
Class

C. Same Net Spacing Rule Set

via
 :
1. Setting the Default Spacing Rules
Spacing Constraint Set Default

2. Defining the Special Spacing Rules

Default Create Spacing CSet .

3. Assigning a Net Class

Referenced Same Net CSet

D. HDI Constraint Driven Flow

1. Via List Viewer
(1) Access from Constraint Manager
Physical domain
Via List cell
(2) via

(2) draw option via viewer color layer

visibility tool tips
2. Via List DRC
(1) Via List Net Classes, Buses, Differential Pairs,
Xnets , Nets via. Via List Region object
via Via List Constraint Manager
Physical Physical Cset PCset
Net objects

(2) Via List DRC

Setup - Constraint Modes - Physical Modes
physical mode Via list DRC off on
ok apply
(3) Via List DRC allegro V-N

3. Exclusive Microvia Stacking (XL)

(1) via microvia microvia

(3) microvia microvia constraint pad-pad

 connect

Microvia_Microvia_Only: microvia microvia ;

Microvia_Microvia_Coincident_Only: microvia microvia

;
( x.y )
4. Elimination of Unused Stacked Vias (XL)
(1) stacked vias, stub

(2) Elimination of Unused Stacked Vias

Route Gloss Parameters.
Glossing Controller
Via eliminate .
Via eliminate
Eliminate unused stacked vias.
ok
E. Design Constraints
1. Analyze/Analysis Modes Design Constraints Negative
plane Soldermask

Negative plane islands Flash

Oversize DRC
Soldermask alignment Pad DRC
Soldermask to soldermask
DRC
Soldermask to pad or cline spacing
DRC
Soldermask to shape spacing
DRC
Testpoint pad to component
Testpoint location to component
Mechanical pin to mechanical pin
Mechanical pin to conductor spacing

2. ______ Analyze/Analysis Modes Physical Modes, Spacing Modes

Same Net Spacing Modes

F. Region
Region ,
1. Defining Constraint Regions
Shape> Polygon/Rectangular/Circular
2. Define and Apply the New Rule Set
Constraint Manager Rule Constraint Region

3. Creating a Region-Class Rule

Region
NetClass
G. Electrical Constraints (performance option)
differential Pair

DiffPair :
Calculator User Impedance .., setup >
constraints> Ecsets > diff pair values
Primary Gap
Line Width
Neck Gap/Width
Coupled Tolerance +/- --
Min Line Spacing
Gather Control Gather Uncoupled Length
Max Uncoupled Length ,

Phase Tolerance
:
Pseudo Segment Uncoupled Length DRC
, :

H. Property

Net Property
(1)

FIXED

HARD_LOCATION Auto Rename

RefDes Rename

NCPIN_TESTED NC Pin

(2) Net

FIXED Net

NO_RAT Net

BUS_NAME Net

TESTPIN_COUNT Net
 MIN_LINE_WIDTH Net

NET_PHYSICAL_TYPE Net Via

MIN_LINE_WIDTH NET_PHYSICAL_TYPE
MIN_LINE_WIDTH

DIFFERENTIAL_PAIR

MAX_VIA_COUNT Net Via

VIA_LIST Net Via

VIA_LIST via30 via40 via50

IMPEDANCE_RULE

IMPEDANCE_RULE A B C D
A Pin
B Pin
Net A B ALL
C
D

1 IMPEDANCE_RULE ALL ALL 50ohm 10ohm

50ohm 10ohm
2 IMPEDANCE_RULE ALL ALL 50ohm 10
50ohm 10
3 IMPEDANCE_RULE U1.1 R1.1 50ohm 10ohm
U1.1 R1.1 50ohm 10ohm
4 IMPEDANCE_RULE U1.1 R1.1 50ohm 20
U1.1 R1.1 50ohm 20
PROPAGATION_DELAY

PROPAGATION_DELAY A B C D
A Pin
B Pin
Net 2 Pin A L B S
C
D
PROPAGATION_DELAY U1.4 U2.8 1000mil 1500mil
U1.4 U2.8 1000mil 1500mil
PROPAGATION_DELAY U1.4 U2.8 1000mil
U1.4 U2.8 1000mil
PROPAGATION_DELAY U1.4 U2.8 1500
U1.4 U2.8 1500mil
PROPAGATION_DELAY L S 1000mil 1500mil
Net 1000mil 1500mil
PROPAGATION_DELAY L S 1000mil
Net 1000mil
PROPAGATION_DELAY L S 1500mil
Net 1500mil
RELATIVE_PROPAGATION_DELAY

RELATIVE_PROPAGATION_DELAY A B C D E F
A BUS_NAME MATCH_GROUP

BUS_NAME AGP MATCH_GROUP AGP

R_AGP

B GLOBAL LOCAL B G L
C Pin
D Pin
Net 2 Pin C L D S
E Target
F

RELATIVE_PROPAGATION_DELAY R_AGP G U4.23 U5.34 0mil

25mil
U4.23 U5.34 R_AGP 25mil
RELATIVE_PROPAGATION_DELAY R_AGP G U4.23 U5.34 0mil
10
U4.23 U5.34 R_AGP 10
RELATIVE_PROPAGATION_DELAY R_AGP G U4.23 U5.34
U4.23 U5.34 R_AGP
Target
RELATIVE_PROPAGATION_DELAY R_AGP G U4.23 U5.34 15mil
25mil U4.23 U5.34 R_AGP Target
15mil 25mil
RELATIVE_PROPAGATION_DELAY R_AGP G U4.23 U5.34
15mil 25mil U4.23 U5.34 R_AGP
Target 15mil 25mil

RELATIVE_PROPAGATION_DELAY R_AGP G L S 0mil 25mil

Net R_AGP 25mil
Pin Pin L
S
Note
1 Net 2 Pin Pin L S
2 Net 2 Pin Pin Pin

3 Match Group Bus Name

Cmgr

I. Waive DRCs
Display/Waive DRCs DRC
.
:
1. AGND DGND DRC

3. Display/Waive DRCs/Waive DRC .

3. Waive DRC 90

4. Display/Waive DRCs/Blank DRC

Drawing Options Waive DRCs

Display/Waive DRCs/Show
DRC Display/Waive DRCs/Show/Restore
DRCs/Show/Restore all

J. Display Constraint
Constraint Display /Constraint
 Routing and Glossing
A.
Setup>Grids
B. Adding Signal Connections and Inserting Vias

Allegro Layout
Route>Connect
Act
Alt
Via Via Padstack
WL working layer
Line lock
45 45
90 90
Off
Miter
Min Fixed
Line width
Default
Bubble

Shove vias vias

Gridless
Clip dangling clines
Smooth
Snap to connect point
Replace etch Loop Net
Pin / Via Cline
1. constraints Physical vias

3.
Act
Alt
Via

Bubble

Via

Add connect Shove preferred

Option Form
Add Connect

Done , Idle
Oops
Cancel
Next ,
Reject , ,
Add Via
Swap Layer (Act Alt ) Drill Pin
Pad or Via
Finish
Neck mode , Physical Rule Set
Target
New Target
No Target
Snap Rat T T
Toggle Pad ( )
Route offset

Option
Route offset 4~18.5
C. Moving Etch with the Slide Option

Slide Etch

Route>Slide Options
Active etch subclass
Active
Net name net name
Min Corner Size 45 2

Min Arc Radius

Vertex Action

Bubble
Shove vias vias
Clip dangling clines dangling clines
Smooth
Allow DRCs DRC
Gridless
Auto Join
Extend Selection

Add connect
 Slide Cut

slide offset

vertex
Auto Join

D. Enhanced Pad Entry

1. Allegro Add Connect Slide

2.

3. pin/via

4. line-lock
E. Custom smooth

Route>Custom smooth

Corner Type
Restrict Seg Entry for Pads of Type Pads
Minimum Pad Entry Length pad

Max Iterations smooth

F. VERTEX ( )

Edit/Vertex or Edit/Delete Vertex

G. Rats
Display>Show Rats 3
1. All
2. Component Net
3. Nets Net
Display>Blank Rats

Note
Net NO_RAT net
Display>Highlight or Display>Dehighlight
Highlight , Highlight

Display Show Rats End In View Only

H. Deleting Etch and Via
Edit>Delete
Ripup etch
ETCH

Delete Net Options

Find Nets ,
Element

net
Delete Find Clines Cut
Cut Done

8 - 18
I. SPECCTRA
Route>SPECCTRA >Route Automatic

Close
Route
Undo
Results
Help
Router Setup Tab
Strategy
Specify Routing Passes Routing Passes

Use Smart Route Smart Router

Do File do
Options
Limit Via Creation Via
Enable Diagonal Routing
Limit Wraparounds Pin
Protect existing routes
Wire Grid
X Grid x
Y Grid y
X Offset x
Y Offset y
Via Grids Via
X Grid x
Y Grid y
X Offset x
Y Offset y

Routing Passes Tab

Pass Type
Fanout pad Vias
Route
Clean
Passes
Smart Router Tab
 Grid

Minimum Via Grid via

Minimum Wire Grid

Fanout

Via Sharing via

Pin Sharing Pin
Generate Testpoints
Off
Top Top
Bottom Bottom
Both
Use Grid
Miter After Route
Selections Tab
 Router Net
BGA Fanout Route>Fanout By Pick :

J. Gloss

Route>Gloss>
Bubbles ( )

Jogs ( )

Dangling line ( )

No-Net Dangling line :( )

Line Segments
Convert 90 s to 45 90o 45o
Extend 45 45o
Maximum 45 Length 45o A
-1
Length Limit

B
 -1
Corner Type
Number of Executions

Copper
routing plane Positive
Negative Shape Plane
Shape
A.
shape Allegro Artwork :

(1) :

: 1. shape
2. PCB Gerber
: 1. thermal flash symbols
2. DRC Check Rule
 (2) :

: 1. Allegro Thermal Relief

anti_pad flash symbols
2. DRC Check : pin
: 1. shape shape
2. Static solid shape

Gerber
shape
Gerber
B.
(1)
Shape shape

a. options Class(ETCH) Subclass

b. , Static solid
c.
Thermal Relief anti_pad

(2) SPLIT
3v(ETCH/VCC)
ANTIETCH/VCC
:

a. Toolbar Add line options Active

class and Subclass ANTI ETCH VCC

b. Edit>Split plane>Parameters , shape

.
b. Edit>Split plane>Create

Vcc shape
C.
(1)
Shape shape
Etch

a. options class(ETCH) subclass

b.

Dynamic copper

Static solid

Static Crosshatch

Unfilled

Defer performing dynamic fill , ,

c.

d. Shape

e. route keeping

D.
Shape/Global shape parameters
(1) Shape fill
Dynamic fill:
Smooth: fill void DRC shape

Rough: void
Disabled: fill, void, DRC, netin, gloss, testprep
add/replace vias

Xhatch Style:
Fill Style

(2) Void controls:

 Artwork format

Minimum aperture for artwork fill .

Suppress shapes less than

Create pin voids pin via void

Distance between pins pin in-line

Snap voids to hatch grid voids hatch

(3) Clearances: Void

Shape PIN LINE CLINE TEXT SHAPE RECTANGLE
 DRC Value setup>constrains spacing Shape

Thermal / Antipad PADSTACK Thermal / Antipad

(3) Thermal relief connects: Thermal

PIN Via Thermal

Orthogonal Orthogonal Shape
Diagonal 45 Shape
Full Contact Shape
8 Way Connect 8

Maximum Connects Thermal 1-8

Minimum connects Thermal .

use fixed thermal width of thermal width

Use thermal width oversize of thermal width

Note : Edit/Properties

DYN_XXXXXX_XXX Dynamic Shape Properties

DYN_CLEARANCE_OVERSIZE = 10 MIL Design Rule
clearance 10mil

E.
(1)

shape/Manual Void

Delete : Void

Element :
 Move : void

Copy : void

(2)
a. Shape/Edit Boundary

b. Select shape or void

shape Highlight shape
(Vertex)
shape
 (3)
Shape /Delete Islands
Delete all on layer: Island
Current Island: Island

(4) Shape/Change shape type

(5) Shape Shape /Merge

(6) Shape Minimum Aperture Gerber
, Shape/Check
(7) Shape /Compos Shape

(8) Shape /Decompose: Shape line

Rename

Rename
Logic/Auto Rename Refdes
 Design

Room ROOM

Window

List List

A.
Logic>Auto Rename Refdes>Rename

User defined grid Place_Grid_Top(Bottom) (

Use default grid

Rename all components

Attach property components

AUTO_RENAME Rename , Auto Rename ,

Rename.
 More ( Rename )

Layer

Starting layer

#Component Origin:

Directions for Top Layer Top

Directions for Bottom Layer Bottom

Reference Designator Format

RefDes Prefix Prefix , *

Top Layer Identifier Top

Bottom Layer Identifier Bottom

Skip Character(s) ( I,O.. )

Renaming Method:
 Sequential:

Grid based:

Grid Based Renaming

1st Direction Designation: ,

2nd Direction Designation: ,

Refdes Digits

Note 1 . User/Preferences fst_ref_des

B.
Edit/Text

Properties Hard Location ,

,

C.
PCB SCH , Backannotation

A.

B.
 (1) PCB Editor Netlist,
OrCAD Tools/Back Annotate, PCB .

(2) Other Netlist

OrCAD Tools/Back Annotate, WAS/IS [Link],

(3)
 AutoSilk & Report

AutoSilk

Allegro Report Report

A. AutoSilk
Manufacture >Silkscreen

Layer

Element
Classes and subclasses

Any Classes

Silk Silk

None

Text

Rotation

Allow under components

Lock autosilk text Update autosilk ,

Detailed text checking Text Block

Maximum displacement ,

Displacement incremen ,
Minimum line length Line Arc

Element to pad clearance PAD

Clear solder mask pad Solder Mask

Audit Silk [Link]

B. Report
allegro report Tools/Reports

a. HTML
b.

c.
Bill of Material Report BOM
Design Rules Check Report DRC

Etch Length by Net Report

Net Loop Report
Net Loop

Net Loop

d. New/Edit
 save
Load
 Gerber
Gerber RS274D (
erber4x00,Gerber6x00) Gerber RS274x BarcoDPF MDA
Gerber6x00 Gerber RS274x
A.
( ) Gerber RS274D ( Gerber6x00 )
Gerber6x00 art_aper.txt

Gerber6x00

1. Manufacture>Artwork General Parameters

Device type --- Gerber 6x00
Format --- Integer places:3 ; Decimal places: 5( inch 5 mil
)
NOTE:

2. OK art_param.txt File
3. Apertures --- Edit Aperture Wheels Edit
 Auto without Rotation( )
with
Rotation Without Rotation
OK art_aper.txt

4. Film Control Artwork

 - , BOTTOM, GND, TOP, VCC

- BOTTOM

ETCH/BOTTOM,PIN/BOTTOM,VIA
CLASS/BOTTOM
5. Film Options

.Rotation ( )
.Offset X: / Y: ( )
.Undefined line width
.Shape bounding box Outline
( )
.Plot mode Positive (Artwork ) Negative (Artwork )
.Film mirrored Gerber
.Full Contact Thermal-Reliefs Thermal
( )
.Draw missing pad apertures Aperture D-Code
Pad Line Draw

.Use aperture rotation Aperture rotation

.Suppress Shape Fill ( )
.Vector based pad behavior
(Gerber RS274X )
6. Artwork (Positive) (Negative)
RS274 :

Ex:
[Link] subclass [Link]
VIA CLASS/TOP
PIN/TOP
MANUFACTURING/PHOTOPLOT_OUTLINE
ETCH/TOP
DRAWING FORMAT/OUTLINE
Gerber
Display Allegro
Allegro
match display
Save

Load
RS274 :
Ex:
[Link] subclass [Link]
VIA CLASS/GND
PIN/GND
MANUFACTURING/PHOTOPLOT_OUTLINE
ETCH/GND
DRAWING FORMAT/OUTLINE
ANTI ETCH/GND
Anti etch ( )
Gerber 6x00 Anti Etch
Gerber RS-274D-X Anti Etch

7. Create Artwork .Art

Check database before artwork artwork

database
8. CAM Tools *.art
[Link]
12 - 7
[Link] :

Note:
[Link] File Thermal
D21 T188X174X40 CAM Tools

( ) Gerber RS274X
Gerber RS274X Gerber6x00 RS274X

Gerber File art_aper.txt

Note : RS274X ,

Gerber RS274X
1. Manufacture>Artwork General Parameters
Device type --- Gerber RS274X
Format --- Integer places: 2 Decimal places: 5 ( inch )

2. OK art_param.txt File
3. Film Control Artwork

4. Artwork (Positive) (Negative)

RS274X
Ex:
[Link] , subclass [Link]
VIA CLASS/TOP
PIN/TOP
MANUFACTURING/PHOTOPLOT_OUTLINE
ETCH/TOP
DRAWING FORMAT/OUTLINE
Gerber
RS274X :

Ex:
 [Link] , subclass [Link] ,
VIA CLASS/GND
PIN/GND
MANUFACTURING/PHOTOPLOT_OUTLINE
ETCH/GND
DRAWING FORMAT/OUTLINE
Gerber6x00 Anti etch ( )
5. Create Artwork .Art

6. CAM Tools *.art Import

[Link]

[Link]
cam tool composite
,
B.
File/Import/Artwork Load File

C. Drill Customization
/Manufacture/NC/ Customization, Drill symbol
 Validate

Merge , ,

Reset to design Library

Reset to Library Library

Auto generate symbols

Write report file

Library drill report

D.
Manufacture/NC/Drill legend
E.
Manufacture/NC/Drill Parameters NC
 NC Parameter Format Gerber
Manufacture/NC/NC
Drill

F.
nc_tools_auto.txt
Manufacture/NC/NC Route NC Route

Separate files for plated/non-plated routing plated non-plated NC

Route
NC Route
PS. 16.6
,
[Link]

CADIn
CAD PowerPCB PCAD
OrCAD Layout PCB

A. PowerPCB to Allegro
:
1. PADS .asc
(1) PowerPCB allegro
(2) File>Export .asc ( Save
)
(3) asc output file name
(4) Select All
(5) Format PowerPCB V3.0 ~ 2007
(6) Units Basic Current.
(7) reuse
(8) OK .ASC
2. ALLEGRO .ASC
(1) ALLEGRO

(2) File>Import> CAD Translators >PADS

(3) PADS ASCII input file Browse pads

.asc
(4) Options File Browse

(5) Output Design

 (6) Run , create solder layers

B. PCAD to Allegro
PCAD PCB ( PDIF )
1. File>Import>CAD Translators>PCAD

2. Run
3. File/Open brd
C. OrCAD Max to Allegro
1. File>Import>CAD Translators>OrCAD Layout

2. *.max (Input Layout file) (Output

Directory) Translate