PRELIMINARY CY7C4122KV12, CY7C4142KV12

144-Mbit QDR™-IV GT SRAM

144-Mbit QDR™-IV SRAM Two-Word Burst Architecture with Bank Switching

Features Configurations
■ 144-Mbit density (8 M ×18, 4 M ×36) CY7C4122KV12 – 8 M ×18
■ Total Random Transaction Rate [1]
of 2133 MT/s CY7C4142KV12 – 4 M ×36

■ Maximum operating frequency of 1066 MHz Functional Description

■ Read latency of 8.0 clock cycles and Write Latency of 5.0 clock
The QDR-IV GT SRAM is a high performance memory device
cycles
optimized to maximize the number of random transactions per
■ 8 bank architecture enables one access per bank per cycle second by the use of two independent bi-directional data ports.
■ Two-word burst on all accesses These ports are equipped with DDR interfaces and designated
as port A and port B respectively. Accesses to these two data
■ Dual independent bi-directional data ports ports are concurrent and completely independent of each other.
❐ DDR (Double data rate) data ports Access to each port is through a common address bus running
❐ Supports concurrent read/write transactions on both ports at double data rate (DDR). The control signals are running at
single data rate (SDR) and determine if a read or write should be
■ Single address port used to control both data ports performed.
❐ DDR (Double data rate) address signaling
There are 3 types of differential clocks:
■ SDR (Single data rate) control signaling ❐ (CK, CK#) for address and command clocking

■ HSTL/SSTL compatible signaling (JESD8-16A compliant) ❐ (DKA, DKA#, DKB, DKB#) for data input clocking
❐ (QKA, QKA#, QKB, QKB#) for data output clocking
❐ I/O VDDQ = 1.2 V ± 50 mV or 1.25 V ± 50 mV
Addresses for port A are latched on the rising edge of the input
■ Pseudo open drain (POD) signaling (JESD8-24 compliant) clock (CK), and addresses for port B are latched on the falling
❐ I/O VDDQ = 1.1 V ± 50 mV or 1.2 V ± 50 mV edge of the input clock (CK).
■ Core voltage This QDR-IV GT SRAM is internally partitioned into 8 internal
❐ VDD = 1.25 V ± 50 mV [Link] bank can be accessed once per clock cycle enabling
the SRAM to operate at high frequencies.
■ On die termination (ODT)
❐ Programmable for clock, address/command and data inputs
The QDR-IV GT SRAM device is offered in a two-word burst
option and is available in ×18 and ×36 bus width configurations.
■ Internal self calibration of output impedance through ZQ pin
For a ×18 bus width configuration, there are 22 address bits, and
■ Bus inversion to reduce switching noise and power for a ×36 bus width configuration, there are 21 address bits
❐ Programmable on/off for address and data respectively.

■ Address bus parity error protection An on-chip ECC circuitry detects and corrects all single-bit
memory errors, including those induced by soft error events such
■ Training sequence for per-bit deskew as cosmic rays, alpha particles, etc. The resulting soft error rate
(SER) of these devices is expected to be less than 0.01 FITs/Mb,
■ On chip error correction (ECC) to reduce SER a four-order-of-magnitude improvement over previous
■ JTAG 1149.1 test access port (JESD8-26 compliant) generation SRAMs.
❐ 1.25 V LVCMOS signaling

■ Available in 361-ball FCBGA Pb-free package (21 x 21mm)

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-68255 Rev. *E Revised April 12, 2013
 PRELIMINARY CY7C4122KV12, CY7C4142KV12

Table 1. Selection Guide

QDR-IV QDR-IV
Description Unit
2133 (MT/s) 1866 (MT/s)
Maximum Operating Frequency 1066 933 MHz
Maximum Operating Current ×18 3600 2900 mA
×36 4000 3300

Note
1. RTR (Random Transaction Rate) is defined as the number of fully random memory accesses (reads or writes) that can be performed on the memory. RTR is measured
in million transactions per second.

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

Figure 1. Logic Block Diagram – CY7C4122KV12 (8 M ×18)

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

Figure 2. Logic Block Diagram – CY7C4142KV12 (4 M ×36)

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

Contents
Pin Configurations ........................................................... 6 TAP Electrical Characteristics ...................................... 25
Pin Definitions .................................................................. 8 TAP AC Switching Characteristics ............................... 25
Functional Overview ...................................................... 10 TAP Timing Diagram ...................................................... 26
Clocking ..................................................................... 10 Identification Register Definitions ................................ 27
Command Cycles ...................................................... 10 Scan Register Sizes ....................................................... 27
Read and Write Data Cycles ..................................... 10 Instruction Codes ........................................................... 27
Banking Operation ..................................................... 10 Boundary Scan Order .................................................... 28
Address and Data Bus Inversion ............................... 10 Maximum Ratings ........................................................... 31
Address Parity ........................................................... 11 Operating Range ............................................................. 31
Port Enable ................................................................ 11 Neutron Soft Error Immunity ......................................... 31
ODT Operation (On-Die Termination) ....................... 11 Electrical Characteristics ............................................... 31
JTAG Operation ........................................................ 11 Capacitance .................................................................... 33
Power Up and Reset ................................................. 11 Thermal Resistance ........................................................ 33
Operation Modes ....................................................... 12 AC Test Loads and Waveforms ..................................... 33
Deskew Training Sequence ...................................... 13 Switching Characteristics .............................................. 34
I/O Signaling Standards ............................................ 13 Switching Waveforms .................................................... 36
Initialization ................................................................ 14 Ordering Information ...................................................... 42
Configuration Registers ............................................. 15 Ordering Code Definitions ......................................... 42
Configuration Registers Description .......................... 16 Package Diagram ............................................................ 43
Configuration Register Definitions ............................. 16 Acronyms ........................................................................ 44
I/OType and Port Enable Bit Definitions .................... 18 Document Conventions ................................................. 44
ODT Termination Bit Definitions ................................ 19 Units of Measure ....................................................... 44
Drive Strength Bit Definitions .................................... 20 Document History Page ................................................. 45
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 21 Sales, Solutions, and Legal Information ...................... 47
Test Access Port ....................................................... 21 Worldwide Sales and Design Support ....................... 47
TAP Registers ........................................................... 21 Products .................................................................... 47
TAP Instruction Set ................................................... 21 PSoC Solutions ......................................................... 47
TAP Controller State Diagram ....................................... 23
TAP Controller Block Diagram ...................................... 24

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

Figure 3. Pin Configurations

Figure 3 (a) - CY7C4122KV12 (8 M × 18)

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

Figure 3. Pin Configurations (continued)

Figure 3 (b) - CY7C4142KV12 (4 M ×36)

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

Table 2. Pin Definitions

Pin Name I/Os Pin Description

CK, CK# Input Clock Address/Command Input [Link] and CK# are differential clock inputs. All control and address
input signals are sampled on both the rising and falling edges of CK. The rising edge of CK samples
the control and address inputs for port A, while the falling edge of CK samples the control and address
inputs for port B. CK# is 180 degrees out of phase with CK.
A[x:0] Input Address [Link] on the rising edge of both CK and CK# clocks during active read and write
operations. These address inputs are used for read and write operations on both ports. The lower
three address pins (A0, A1, and A2) select the bank that will be accessed. These address inputs are
also known as bank address pins.
For (×36) data width - Address inputs A[20:0] are used and A[24:21] are reserved.
For (×18) data width - Address inputs A[21:0] are used and A[24:22] are reserved.
The reserved address inputs are No Connects and may be tied high, tied low, or left floating.
AP Input Address Parity Input. Used to provide even parity across the address pins.
For (×36) data width - AP covers address inputs A[20:0]
For (×18) data width - AP covers address inputs A[21:0]
PE# Output Address Parity Error Flag. Asserted LOW when address parity error is detected. Once asserted,
PE# will remain LOW until cleared by a Configuration Register command.
AINV Input Address Inversion Pin for Address and Address Parity Inputs.
For (×36) data width - AINV covers address inputs A[20:0] and the address parity input (AP).
For (×18) data width - AINV covers address inputs A[21:0] and the address parity input (AP).
DKA[1:0], Input Data Input Clock.
DKA#[1:0], DKA[0] / DKA#[0] controls the DQA[17:0] inputs for ×36 configuration and DQA[8:0] inputs for ×18
DKB[1:0], configuration respectively
DKB#[1:0] DKA[1] / DKA#[1] controls the DQA[35:18] inputs for ×36 configuration and DQA[17:9] inputs for ×18
configuration respectively
DKB[0] / DKB#[0] controls the DQB[17:0] inputs for ×36 configuration and DQB[8:0] inputs for ×18
configuration respectively
DKB[1] / DKB#[1] controls the DQB[35:18] inputs for ×36 configuration and DQB[17:9] inputs for ×18
configuration respectively
QKA[1:0], Output Data Output Clock.
QKA#[1:0], QKA[0] / QKA#[0] controls the DQA[17:0] outputs for ×36 configuration and DQA[8:0] outputs for ×18
QKB[1:0], configuration respectively
QKB#[1:0] QKA[1] / QKA#[1] controls the DQA[35:18] outputs for ×36 configuration and DQA[17:9] outputs for
×18 configuration respectively
QKB[0] / QKB#[0] controls the DQB[17:0] outputs for ×36 configuration and DQB[8:0] outputs for ×18
configuration respectively
QKB[1] / QKB#[1] controls the DQB[35:18] outputs for ×36 configuration and DQB[17:9] outputs for
×18 configuration respectively
DQA[x:0], Input/Output Data Input/[Link] data bus.
DQB[x:0] For (×36) data width  DQA[35:0]; DQB[35:0]
For (×18) data width  DQA[17:0]; DQB[17:0]
DINVA[1:0], Input/Output Data Inversion Pin for DQ Data Bus.
DINVB[1:0] DINVA[0] covers DQA[17:0] for ×36 configuration and DQA[8:0] for ×18 configuration respectively
DINVA[1] covers DQA[35:18] for ×36 configuration and DQA[17:9] for ×18 configuration respectively
DINVB[0] covers DQB[17:0] for ×36 configuration and DQB[8:0] for ×18 configuration respectively
DINVB[1] covers DQB[35:18] for ×36 configuration and DQB[17:9] for ×18 configuration respectively
LDA#, LDB# Input Synchronous Load [Link]# is sampled on the rising edge of the CK clock, while LDB# is sampled
on the falling edge of CK clock. LDA# enables commands for data port A, and LDB# enables
commands for data port B. LDx# enables the commands when LDx# is LOW and disables the
commands when LDx# is HIGH. When the command is disabled, new commands are ignored, but
internal operations continue.

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Table 2. Pin Definitions (continued)

Pin Name I/Os Pin Description
RWA#, Input Synchronous Read/Write Input. RWA# input is sampled on the rising edge of the CK clock, while
RWB# RWB# is sampled on the falling edge of the CK clock. The RWA# input is used in conjunction with the
LDA# input to select a Read or Write Operation. Likewise, the RWB# input is used in conjunction with
the LDB# input to select a Read or Write Operation.
QVLDA[1:0], Output Output Data Valid Indicator. The QVLD pin indicates valid output data. QVLD is edge aligned with
QVLDB[1:0] QKx and QKx#.
ZQ/ZT Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance.
CFG# Input Configuration bit. This pin is used to configure different mode registers.
RST# Input Active Low Asynchronous RST. This pin is active when RST# is LOW, and inactive when RST# is
[Link]# pin has an internal pull down resistor.
LBK0#, Input Loopback mode for control and address/command/clock deskewing.
LBK1#
TMS Input Test Mode Select Input pin for JTAG. This pin may be left unconnected if the JTAG function is not
used in the circuit.
TDI Input Test Data Input pin for JTAG. This pin may be left unconnected if the JTAG function is not used in
the circuit.
TCK Input Test Clock Input pin for JTAG. This pin must be tied to VSS if the JTAG function is not used in the
circuit.
TDO Output Test Data Output pin for JTAG. This pin may be left unconnected if the JTAG function is not used in
the circuit.
TRST# Input Test Reset Input pin for JTAG. This pin must be tied to VDD if the JTAG function is not used in the
system. TRST# input is applicable only in JTAG mode.
DNU N/A Do Not Use. Do Not Use pins.
VREF Reference Reference Voltage Input. Static input used to set the reference level for inputs, outputs, and AC
measurement points.
VDD Power Power Supply Inputs to the Core of the Device.
VDDA Analog Power Analog Power Supply Inputs to the Core of the Device.
VDDQ Power Power Supply Inputs for the Outputs of the Device.
VSS Ground Ground for the Device.

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Functional Overview Write data is supplied to the DQA pins exactly 5 clock cycles from
the rising edge of the CK signal corresponding to the cycle that
The QDR-IV GT SRAM is a two word burst synchronous SRAM the write command was initiated.
equipped with dual independent bidirectional data ports. The Write data is supplied to the DQB pins exactly 5 clock cycles from
following sections describe the operation of QDR-IV GT SRAM. the falling edge of the CK signal corresponding to the cycle that
the write command was initiated.
Clocking
There are three groups of clock signals: CK/CK#, DKx/DKx#, Banking Operation
and QKx/QKx#, where x can be A or B, referring to the respective The QDR-IV GT SRAM is designed with 8 internal banks. The
ports. lower three address pins (A0, A1, and A2) select the bank that
The CK/CK# clock is associated with the address and control will be accessed. These address inputs are also known as bank
pins: A[24:0], LDA#, LDB#, RWA#, RWB#. The CK/CK# address pins.
transitions are centered with respect to the address and control
signal transitions. Bank Access Rules
The DKx/DKx# clocks are associated with write data. The 1. On the rising edge of the input clock, any bank address may
DKx/DKx# clocks are used as source-centered clocks for the be accessed. This is the address associated with port A.
double data rate DQx and DINVx pins, when acting as inputs for 2. On the falling edge of the input clock, any other bank
the write data. address may be accessed. This is the address associated
The QKx/QKx# clocks are associated with read data. The with port B.
QKx/QKx# clocks are used as source-synchronous clocks for 3. If port A did not issue a command on the rising edge of the
the double data rate DQx and DINVx pins, when acting as input clock, then port B may access any bank address on the
outputs for the read data. falling edge of the input clock.
4. From the rising edge of the input clock cycle to the next
Command Cycles rising edge of the input clock, there is no address
The QDR-IV GT read and write commands are driven by the restriction. Port A may access any bank at any time.
control inputs (LDA#, LDB#, RWA#, and RWB#) and the Address To clarify, the banking restriction only applies in a single clock
Bus. cycle. Since the port A address is sampled on the rising edge of
The port A control inputs (LDA# and RWA#) are sampled at the the input clock, there are no restrictions with port A access. And
rising edge of the input clock. The port B control inputs (LDB# because the port B address is sampled on the falling edge of the
and RWB#) are sampled at the falling edge of the input clock. input clock, port B has the restriction that it must use a different
bank than port A.
For port A:
Banking Violations
When LDA# = 0 and RWA# = 1, a read operation is initiated.
1. Accesses for port A cannot cause a banking violation, only
When LDA# = 0 and RWA# = 0, a write operation is initiated.
accesses to port B can.
The Address is sampled on the rising edge of the input clock. 2. If port B tries to access the same bank as port A, then the port
For port B: B access to the memory array is ignored. The port A access
will still occur normally.
When LDB# = 0 and RWB# = 1, a read operation is initiated.
3. If the requested cycle on port B was a write, then there will be
When LDB# = 0 and RWB# = 0, a write operation is initiated. no external indication that a banking violation occurred.
The Address is sampled on the falling edge of the input clock. 4. If the requested cycle on port B was a read, then there will be
no QVLDB signal generated. Outputs will remain tri-stated.
Read and Write Data Cycles
Read Data is supplied to the DQA pins exactly 8 clock cycles Address and Data Bus Inversion
from the rising edge of the CK signal corresponding to the cycle In order to reduce simultaneous switching noise and I/O current,
that the read command was initiated. QVLDA is asserted QDR-IV GT provides the ability to invert all address and data
one-half clock cycle prior to the first data word driven on the bus. pins.
It is de-asserted one-half cycle prior to the last data word driven The AINV pin indicates whether the address bus- A[24:0], and
on the bus. Data outputs are tri-stated in the clock following the the address parity bit, AP, is inverted. The address bus and parity
last data word. bit are considered one group. The function of the AINV is
Read data is supplied to the DQB pins exactly 8 clock cycles from controlled by the memory controller. But, the following rules
the falling edge of the CK signal corresponding to the cycle that should be used in the system design.
the read command was initiated. QVLDB is asserted one-half
clock cycle prior to the first data word driven on the bus. It is ■ For a ×36 configuration part, 21 address pins plus 1 parity bit
de-asserted one-half cycle prior to the last data word driven on are used for a total of 22 signals in the address [Link] the
the bus. Data outputs are tri-stated in the clock following the last number of 0’s in the address group >= 11, AINV is set to 1 by
data word. the controller. As a result, no more than 11 pins may switch in
the same direction during each bit time.

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■ For a ×18 data width part, 22 address pins plus 1 parity bit are During configuration register read and write cycles, the address
used for a total of 23 signals in the address [Link] the number parity input is ignored. Parity is not checked during these cycles.
of 0’s in the address group >= 12, AINV is set to 1 by the
controller. As a result, no more than 12 pins may switch in the Port Enable
same direction during each bit time. The QDR-IV GT has two independent bi-directional data ports.
The DINVA and DINVB pins indicate whether the corresponding However, some system designers may either choose to use only
DQA and DQB pins are inverted. one port, or use one port as read-only and one port as write-only.
■ For a ×36 data width part, the data bus for each port is split into If a port is used in a uni-directional mode, the data clocks
groups of 18 pins. Each 18 pin data group is guaranteed to be (DKx/DKx# or QKx/QKx#) need to be disabled to reduce EMI
driving less than or equal to 10 pins low on any given [Link] effects in the system. Also, the corresponding control input
the number of 0’s in the data group >=10, DINV is set to [Link] (RWx#) needs to be disabled as well.
a result, no more than 10 pins may switch in the same direction Port B may be programmed to be entirely disabled. If port B is
during each bit time. not used, then the following must happen:
■ For a ×18 data width part, the data bus for each port is split ■ The data clocks (DKB/DKB# and QKB/QKB#) and the control
into groups of 9 pins. Each 9 pin data group is guaranteed to inputs (LDB# and RWB#) must be disabled.
be driving less than or equal to 5 pins low on any given [Link]
the number of 0’s in the data group >=5, DINV is set to 1 As a ■ All data bus signals must be tri-stated. This includes
result, no more than 5 pins may switch in the same direction DQB,DINVB and QVLDB.
during each bit time. ■ All input signals related to port B could be left floating or tied
AINV, DINVA[1:0], DINVB[1:0] are all active high. When 1, the off to either 1 or 0 without any adverse effects on the port A
corresponding bus is inverted. If the data inversion feature is operation.
programmed to be OFF, then the DINVA/DINVB output bits will
■ When port B is not used all output signals related to port B will
always be driven to 0.
be inactive.
These functions are programmable through the configuration
A configuration register option is provided to specify if one of the
registers and can be enabled or disabled for the address bus and
ports is not used or operating in a unidirectional mode.
the data bus independently.
During configuration register read and write cycles, the address ODT Operation (On-Die Termination)
inversion input is ignored and the data inversion output is always When enabled, the ODT circuits for the chip will be enabled
driven to 0 when register read data is driven on the data bus. during all NOP and write cycles. Only during read cycles is the
Specifically, the register read data is driven on DQA[7:0] and the ODT temporarily disabled as the read data is driven out.
DINVA[0] bit is driven to 0. All other DQA/DQB data bits and
DINVA/DINVB bits are tri-stated. In addition, the address parity Specifically, ODT is disabled ½ clock cycle before the first beat
input (AP) is ignored. of the read data is driven on the data bus and remains disabled
during the entire read operation. ODT is enabled again ½ clock
Address Parity cycle after the last beat of read data is driven on the data bus.
The QDR-IV GT provides an address parity feature to provide JTAG Operation
integrity on the address bus. Two pins are provided to support
this function: AP and PE#. The JTAG interface uses five signals, TRST#, TCK, TMS, TDI,
and TDO. For normal JTAG operation, the use of TRST# is not
The AP pin is used to provide an even parity across the address optional for this device.
pins. The value of AP is set so that the total number of 1’s
(including the AP bit) is even. The AP pin is a double data rate While in JTAG mode, the following conditions are true:
input. ■ ODT for all pins is disabled.
Internally, when an address parity error is detected, the access If the JTAG function is not used in the system, then TRST# pin
to the memory array is ignored if it was a write cycle. A read must be tied to VDD and TCK input must be driven low or tied to
access will continue normally even if an address parity error is VSS. TMS, TDI, and TDO may be left floating.
detected.
Externally, the PE# pin is used to indicate an address parity error Power Up and Reset
has occurred. This pin is active low and is set to 0 within RL The QDR-IV GT has specific power up and reset requirements
cycles after the address parity error was detected. It remains in order to guarantee reliable operation.
asserted until the error is cleared through the configuration
registers. Power Up Sequence
The address parity function is optional and can be enabled or ■ Apply VDD and VDDA together before VDDQ.
disabled in the configuration registers.
■ Apply VDDQ before VREF or at the same time as VREF.

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Reset Sequence Operation Modes

Refer to Reset Timing Diagram (Figure 16 on page 41). The QDR-IV GT has three unique modes of operation:
1. As the power is coming up, all inputs may be in undefined 1. Configuration
state except for RST# and TRST#, which must be LOW during 2. Loopback
tPWR. 3. Memory Access
2. The first signal that should be driven to the device is the input
These modes are defined by the level of the control signals
clock (CK/CK#), which may be unstable for the duration of
CFG#, LBK0#, LBK1#, LDA#, LDB#.
tPWR.
3. Once the input clock has stabilized, then all control inputs It is intended that these operations are mutually exclusive. In
should be driven to a valid value as follows: other words, one operation mode cannot be performed
simultaneously with another operation mode.
a. RST# = 0
b. CFG# = 1 There is no priority given for inadvertently asserting the control
signals at the wrong time. Internal chip behavior is not defined
c. LBK0# = 1 for improper control signal assertion. The system must
d. LBK1# = 1 strictly adhere to proper mode transitions as defined below,
e. LDA# = 1 otherwise device operation is not guaranteed.
f. LDB# = 1
Configuration
4. Reset should remain asserted, while all other control inputs
de-asserted, for a minimum time of 200 µs (tRSS). A configuration operation mode is entered when the CFG# signal
is asserted. Memory Access or Loopback operations should
5. At the rising edge of reset, the address bits A[13:0] are NOT be performed for a minimum of 32 clocks prior to entering
sampled to load in the ODT values and Port Enable values. this mode.
After reset, internal operations in the device may start. This
may include operations such as PLL initialization, resetting While in this mode, the control signals LDB#, LBK0# and LBK1#
internal registers etc. must NOT be asserted. However, LDA# is used to perform the
actual Register Read and Write operations.
6. However, all external control signals must remain de-asserted
for a minimum time of 400000 clocks (tRSH). During this time Memory Access or Loopback operations should NOT be
all other signals (data and address busses) should be driven performed for a minimum of 32 clocks after exiting this mode.
to a valid level. All inputs to the device should be driven to a
valid level. LoopBack
7. After this, the device is in normal operating mode and ready A loopback operation mode is entered when the LBK0# and/or
to respond to control inputs. LBK1# signals are asserted. Memory Access or Configuration
operations should NOT be performed for a minimum of 32 clocks
Typically, after a reset sequence, the system would start to prior to entering this mode.
perform a training sequence, which would involve the steps
outlined in the next section. Just after entering this mode, an additional 32 clocks are
required before the part is ready to accept toggling valid inputs
However, RST# may be asserted at anytime by the system, and for training.
the system may wish to initiate normal read/write operations after
a reset sequence without going through another training While in this mode, LDA# and LDB# may be toggled for training.
sequence. The chip should be able to accept normal read/write Memory Access or Configuration operations should NOT be
operations immediately following tRSH after the de-assertion of performed for a minimum of 32 clocks after exiting this mode.
RST#.
Data inversion is not used during loopback mode. Even if the
PLL Reset Operation configuration register has this feature enabled, it is temporarily
ignored during loopback mode.
The configuration registers contain a bit to reset the PLL.
Operating the QDR-IV GT device without the PLL enabled is not Memory Access
supported – timing characteristics are not guaranteed when the
PLL is disabled. However, this bit is intended to allow the system If the control signals CFG#, LBK0#, and LBK1# are not asserted,
to reset the PLL locking circuitry. then the device is in the memory access mode. This mode is the
normal operating mode of the device.
Resetting the PLL is accomplished by first programming the PLL
Reset bit to 1 to disable the PLL, and then programming the bit While in this mode, a memory access cycle is performed when
to 0 to enable the PLL. After these steps, the PLL will re-lock to the LDA# and/or LDB# signals are asserted. The control signals
the input clock. A wait time of tPLL is required. CFG#, LBK0# and LBK1# must NOT be asserted when
performing a memory access cycle.
A memory access should not be performed for a minimum of 32
clocks prior to leaving this mode.

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Deskew Training Sequence Once the data pattern is written into the memory, standard read
commands permit the system to deskew with respect to the
The QDR-IV GT provides support that allows a memory
QK/QK# data output clocks the following signals:
controller to deskew signals for high speed operation. The
memory controller provides the deskew function, if deskew is DQA, DINVA, QVLDA, DQB, DINVB, QVLDB
desired. During the deskew operation the QDR-IV GT operates
in a loopback mode. Write Data Deskew
Refer to Loopback Timing Diagram (Figure 15 on page 40). Write data deskew is performed using write commands to the
memory followed by read commands.
Deskew is achieved in 3 steps
The deskewed read data path is used to determine whether or
1. Control/address deskew not the write data was received correctly by the device.
2. Read data deskew
This permits the system to deskew with respect to the DK/DK#
3. Write data deskew input data clocks the following signals:
Control/Address Deskew DQA, DINVA, DQB, DINVB
Assert LBK0# to 0 and/or LBK1# to 0 I/O Signaling Standards
39 Signals Looped Back: Several I/O signaling standards are supported by the QDR-IV,
■ DKA0, DKA0#, DKA1, DKA1# which are programmable by the user. They are:

■ DKB0, DKB0#, DKB1, DKB1# ■ 1.2 V and 1.25 V HSTL/SSTL

■ LDA#, RWA#, LDB#, RWB# ■ 1.1 V and 1.2 V POD

The I/O Signaling Standard is programmed on the rising edge of
■ A[24:0], AINV, AP
Reset by sampling the address bus inputs. Once programmed,
The clock inputs DKA0, DKA0#, DKA1#, DKB0, DKB0#, DKB1, the value cannot be changed. Only the rising edge of another
and DKB1# are free running clock inputs and should be Reset can change the value.
continuously running during the training sequence. Also, a wait
All Address, Control, and Data I/O signals – with the exception
time of tPLL is needed.
of 6 pins (listed below as LVCMOS) – will all program to become
Refer to the Table 3 on page 15 for the loopback signal mapping. HSTL/SSTL, or POD compliant.
For each pin that is looped back, the input pin is sampled on both
HSTL/SSTL Signaling
the rising and falling edges using the input clock (CK/CK#).
HSTL/SSTL is supported at the VDDQ voltages of 1.2 V and
The value output on the rising edge of the output clock
1.25 V nominal.
(QKA/QKA#) will be the value that was sampled on the rising
edge of the input clock. The ODT termination values can be set to:
The value output on the falling edge of the output clock ■ 40, 60, or 120 ohms with a 240 ohm reference resistor
(QKA/QKA#) will be the inverted value that was sampled on the
falling edge of the input clock. ■ 50 or 100 ohms with a 200 ohm reference resistor.
The delay from the input pins to the DQA outputs is tLBL, which The Drive strength can be programmed to:
is 16 clocks. ■ 40 or 60 ohms with a 240 ohm reference resistor
Read Data Deskew ■ 50 ohms with a 200 ohm reference resistor
At this time, the address, control, and data input clocks are A reference resistor of 200 ohms or 240 ohms is supported with
already deskewed. HSTL/SSTL signaling.
Read data deskew requires a training pattern to be written into
POD Signaling
the memory using data held at constant values.
POD is supported at VDDQ voltages of 1.1 V and 1.2 V nominal.
Complex data patterns may be written into the memory using the
non-deskewed DQA and/or DQB signals and the write training The ODT termination values can be set to:
enable bit.
■ 50 or 100 ohms with a 200 ohm reference resistor
Write training enable set to 1:
During Write Data Cycles: ■ 60 or 120 ohms with a 240 ohm reference resistor
The First Data Beat is sampled from the data bus. The Drive strength can be programmed to:
The Second Data Beat is the inverted sample from the data bus.
■ 50 ohms with a 200 ohm reference resistor
Write training enable set to 0:
During Write Data Cycles: ■ 40 or 60 ohms with a 240 ohm reference resistor
Both First and Second Data Beats are sampled from the data A reference resistor of 200 ohms or 240 ohms is supported with
bus, which is the normal operation. POD signaling.
The Write Training Enable bit has no effect on read data cycles.

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

LVCMOS Signaling The following flowchart illustrates the initialization procedure:

Six I/O signals are permanently set to use LVCMOS signaling at Figure 4. Flowchart illustrating initialization procedure
voltage of 1.25 V nominal. These signals are referenced to the
core voltage supply, VDD. They are:
RST#, TRST#, TCK, TMS, TDI, and TDO
All 5 of the JTAG signals as well as the main reset input are
1.25 V LVCMOS.
In addition, ODT is disabled at all times on these LVCMOS
signals.
Initialization
The QDR-IV GT must be initialized before it can operate in
normal functional mode. Initialization will use four special pins:
- RST# pin to Reset the device
- CFG# pin to program the Configuration Registers
- LBK0# and LBK1# pins for the Loopback Function

Power on
Apply Power to the chip as described in the power up sequence
above.

Reset Chip

Apply reset to the QDR-IV GT as described in the reset sequence

above.

Configure the Impedance

Assert Config (CFG# = 0) and program the impedance control
register.

Wait for the PLL to Lock

Since the input impedance has been updated, allow the PLL time
(tPLL) to lock to the input clock.

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

Configure Training Options

At this time, the address and data inversion options need to be Table 3. Loopback Signal Mapping
programmed. In addition, the write training function needs to be
enabled. Input Pin Input Pin Input Pin Output Pin
Assert Config (CFG# = 0) and program: LBK0# = 0 LBK0# = 0 LBK0# = 1
a. Write Training (Turn On) LBK1# = 0 LBK1# = 1 LBK1# = 0
b. Address Inversion Enable A0 A13 DKA0 DQA0
c. Data Inversion Enable A1 A14 DKA0# DQA1
Control/Address Deskew A2 A15 DKA1 DQA2
Control and address deskew can now be performed by the A3 A16 DKA1# DQA3
memory controller. A4 A17 LDA# DQA4
Read Data Deskew A5 A18 RWA# DQA5
After control and address deskew the read data path is A6 A19 DKB0 DQA6
deskewed as previously described in the deskew training A7 A20 DKB0# DQA7
sequence.
A8 A21 DKB1 DQA8
Write Data Deskew A9 A22 DKB1# DQA9
Write data path is deskewed following the read data path A10 A23 LDB# DQA10
deskew.
A11 A24 RWB# DQA11
Configure Runtime Options A12 AINV AP DQA12
Now that training is complete, the write training function needs
to be disabled. Finally, the address parity option should be Configuration Registers
enabled at this time.
The QDR-IV GT contains internal registers that are programmed
Assert Config (CFG# = 0) and program: by the system using a special Configuration cycle. These
a. Write Training (Turn off) registers are used to enable and control several options as
b. Parity Enable described below. All registers are 8-bits wide. The write
operation is performed using only the address pins to define the
Normal Operation register address and register write data. For a read operation,
If the system detects a need to deskew again, the process must the register read data is provided on the data port A output pins.
start again from the configure training options [Link] following Refer to Figure 14 on page 39 for programming details.
table defines the loopback mapping: During the rising edge of RST#, the Address pins A[9:0] are
sampled. The value sampled becomes the reset value of certain
bits in the registers defined below. This is used to set termination,
impedance, and port configuration values immediately upon
reset. These values can be overwritten later at anytime through
a register write operation.
When a parity error occurs, the complete address of the first
error is recorded in Registers 4, 5, 6, and 7 along with the port
A/B error bit. The port A/B error bit will indicate which port the
address parity error came from – 0 for port A and 1 for port B.
This information will remain latched until cleared by writing a 1 to
the address parity error clear bit in register 3.
Two counters are used to indicate if multiple address parity errors
have occurred. Port A error count is a running count of the
number of parity errors on port A addresses, and similarly port B
error count is a running count of the number of parity errors on
port B addresses. They will each independently count to a
maximum value of 3 and then stop counting. These counters are
free running, and they are both reset by writing a 1 to the address
parity error clear bit in register 3.

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

Configuration Registers Description

Table 4. Configuration Register Table
Register Address Description
0 Termination Control Register
1 Impedance Control Register
2 Option Control Register
3 Function Control Register
4 Address Parity Status Register 0
5 Address Parity Status Register 1
6 Address Parity Status Register 2
7 Address Parity Status Register 3

Configuration Register Definitions

Table 5. Address 0: Termination Control Register (Read/Write)
Address / Address / Address /
ODT Global ODT/ZQ Command Command Command Clock Input Clock Input Clock Input
Function Enable Auto Update Input Group Input Group Input Group Group KU[2] Group KU[1] Group KU[0]
IU[2] IU[1] IU[0]
Bit Location 7 6 5 4 3 2 1 0
Reset Value A7 A6 A5 A4 A3 A2 A1 A0
Note: ODT/ZQ Auto Update needs to be turned on if ODT/ZQ configuration is changed

Table 6. Address 1: Impedance Control Register (Read/Write)

Pull Down Pull Down Pull Up Pull Up Data Input Data Input Data Input
Function Unused
Group PD[1] Group PD[0] Group PU[1] Group PU[0] Group QU[2] Group QU[1] Group QU[0]
Bit Location 7 6 5 4 3 2 1 0
Reset Value 1 0 1 0 0 A10 A9 A8

Table 7. Address 2: Option Control Register (Read/Write Bits 7-3) (Read-Only Bits 2-0) [2]
Address
Write Train Data Inv Address Port Port
Function Inv PLL Reset I/O Type
Enable Enable Parity Enable Enable[1] Enable[0]
Enable
Bit Location 7 6 5 4 3 2 1 0
Reset Value 0 0 0 0 0 A13 A12 A11

Table 8. Address 3: Function Control Register (Write Only)

Address
Function Unused Unused Unused Unused Unused Unused Unused Parity Error
Clear
Bit Location 7 6 5 4 3 2 1 0
Reset Value 0 0 0 0 0 0 0 0

Note
2. The Bits 2-0 are read only and can be changed only on the rising edge of reset

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

Table 9. Address 4: Address Parity Status Register 0 (Read Only)

Port B Error Count Port A Error Count
Function Port A/B Error AINV Bit Unused Unused
(1:0) (1:0)
Bit Location 7:6 5:4 3 2 1 0
Reset Value 00 00 0 0 0 0

Table 10. Address 5: Address Parity Status Register 1 (Read Only)

Function Address (23:16)
Bit Location 7:0
Reset Value 00000000
Note: Unused address locations will be read as 0

Table 11. Address 6: Address Parity Status Register 2 (Read Only)

Function Address (15:8)
Bit Location 7:0
Reset Value 00000000

Table 12. Address 7: Address Parity Status Register 3 (Read Only)

Function Address (7:0)
Bit Location 7:0
Reset Value 00000000

Document Number: 001-68255 Rev. *E Page 17 of 47

 PRELIMINARY CY7C4122KV12, CY7C4142KV12

I/OType and Port Enable Bit Definitions

Table 13. I/O Type Bit Definition specified in Address 2: Option Control Register
I/O Type Function
0 HSTL / SSTL
1 POD

Table 14. Port Enable Bit Definition specified in Address 2: Option Control Register
Port B Port A
Port Enable Port B Port A
Function Clocks and Clocks and
[1:0] Mode Mode Controls Controls
DKB - On DKA - Off
QKB - Off QKA - On
0 0 Fixed Port Mode Write Only Read Only LDB# - On LDA# - On
RWB# - Off RWA# - Off
DKB - Off DKA - On
Only Port A QKB - Off QKA - On
0 1 Disabled Enabled
Enable LDB# - Off LDA# - On
RWB# - Off RWA# - On
DKB - Off DKA - Off
QKB - Off QKA - Off
1 0 Not Supported Disabled Disabled LDB# - Off LDA# - Off
RWB# - Off RWA# - Off
DKB - On DKA - On
Both Ports QKB - On QKA - On
1 1 Enabled Enabled
Enabled LDB# - On LDA# - On
RWB# - On RWA# - On

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

ODT Termination Bit Definitions

Table 15. Clock Input Group Bit Definition specified in Address 0: Termination Control Register
ODT Termination Value HSTL/SSTL
Divisor Termination Value POD Mode
Global KU[2:0] Mode
Value
Enable ZT 200 ohm ZT 240 ohm ZT 200 ohm ZT 240 ohm
0 X X X – OFF OFF OFF OFF
1 0 0 0 – OFF OFF OFF OFF
1 0 0 1 8.33% Not Supported Not Supported Not Supported Not Supported
1 0 1 0 12.50% Not Supported Not Supported Not Supported Not Supported
1 0 1 1 16.67% Not Supported 40 ohm Not Supported Not Supported
1 1 0 0 25% 50 ohm 60 ohm 50 ohm 60 ohm
1 1 0 1 50% 100 ohm 120 ohm 100 ohm 120 ohm
1 1 1 0 – Not Supported Not Supported Not Supported Not Supported
1 1 1 1 – Not Supported Not Supported Not Supported Not Supported
Note: Termination values are accurate to +/- 15%
ZQ tolerance is 1%

Table 16. Address/Command Input Group Bit Definition specified in Address 0: Termination Control Register
ODT Termination Value HSTL/ SSTL
Divisor Termination Value POD Mode
Global IU[2:0] Mode
Value
Enable ZT 200 ohm ZT 240 ohm ZT 200 ohm ZT 240 ohm
0 X X X – OFF OFF OFF OFF
1 0 0 0 – OFF OFF OFF OFF
1 0 0 1 8.33% Not Supported Not Supported Not Supported Not Supported
1 0 1 0 12.50% Not Supported Not Supported Not Supported Not Supported
1 0 1 1 16.67% Not Supported 40 ohm Not Supported Not Supported
1 1 0 0 25% 50 ohm 60 ohm 50 ohm 60 ohm
1 1 0 1 50% 100 ohm 120 ohm 100 ohm 120 ohm
1 1 1 0 – Not Supported Not Supported Not Supported Not Supported
1 1 1 1 – Not Supported Not Supported Not Supported Not Supported
Note: Termination values are accurate to +/- 15%
ZQ tolerance is 1%

Table 17. Data Input Group Bit Definition specified in Address 1: Impedance Control Register
ODT Termination Value HSTL/ SSTL
Divisor Termination Value POD Mode
Global QU[2:0] Mode
Value
Enable ZT 200 ohm ZT 240 ohm ZT 200 ohm ZT 240 ohm
0 X X X – OFF OFF OFF OFF
1 0 0 0 – OFF OFF OFF OFF
1 0 0 1 8.33% Not Supported Not Supported Not Supported Not Supported
1 0 1 0 12.50% Not Supported Not Supported Not Supported Not Supported
1 0 1 1 16.67% Not Supported 40 ohm Not Supported Not Supported
1 1 0 0 25% 50 ohm 60 ohm 50 ohm 60 ohm
1 1 0 1 50% 100 ohm 120 ohm 100 ohm 120 ohm
1 1 1 0 – Not Supported Not Supported Not Supported Not Supported
1 1 1 1 – Not Supported Not Supported Not Supported Not Supported
Note: Termination values are accurate to +/- 15%
ZQ tolerance is 1%

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

Drive Strength Bit Definitions

Table 18. Pull-Up Driver Bit Definition specified in Address 1: Impedance Control Register

Divisor Impedance Value HSTL/ SSTL Mode Impedance Value POD Mode
PU[1:0] Value ZT 200 ohm ZT 240 ohm ZT 200 ohm ZT 240 ohm
0 0 14.17% Not Supported Not Supported Not Supported Not Supported
0 1 16.67% Not Supported 40 ohm Not Supported 40 ohm
1 0 25% 50 ohm 60 ohm 50 ohm 60 ohm
1 1 – Not Supported Not Supported Not Supported Not Supported
Note: Termination values are accurate to +/- 15%
ZQ tolerance is 1%

Table 19. Pull-Down Driver Bit Definition specified in Address 1: Impedance Control Register

Divisor Impedance Value HSTL/ SSTL Mode Impedance Value POD Mode
PD[1:0] Value ZT 200 ohm ZT 240 ohm ZT 200 ohm ZT 240 ohm
0 0 14.17% Not Supported Not Supported Not Supported Not Supported
0 1 16.67% Not Supported 40 ohm Not Supported 40 ohm
1 0 25% 50 ohm 60 ohm 50 ohm 60 ohm
1 1 – Not Supported Not Supported Not Supported Not Supported
Note: Termination values are accurate to +/- 15%
ZQ tolerance is 1%

Document Number: 001-68255 Rev. *E Page 20 of 47

 PRELIMINARY CY7C4122KV12, CY7C4142KV12

IEEE 1149.1 Serial Boundary Scan (JTAG) Instruction Register

Three-bit instructions can be serially loaded into the instruction
QDR-IV GT SRAMs incorporate a serial boundary scan test register. This register is loaded when it is placed between the TDI
access port (TAP) in the FCBGA package. This part is fully and TDO pins, as shown in Figure 6 on page 24. Upon power up,
compliant with IEEE Standard #1149.1-2001. In JTAG mode the the instruction register is loaded with the IDCODE instruction. It
ODT feature for all pins is disabled. is also loaded with the IDCODE instruction if the controller is
If the JTAG function is not used in the circuit, then TCK inputs placed in a RST state, as described in the previous section.
must be driven low or tied to VSS. TRST#, TMS, TDI, and TDO When the TAP controller is in the Capture-IR state, the two least
may be left floating. An internal Pull-Up resistor is implemented significant bits are loaded with a binary “01” pattern to allow for
on the TRST#, TMS, and TDI inputs to ensure that these inputs fault isolation of the board level serial test path.
are HIGH during tPWR.
Bypass Register
Test Access Port
To save time when serially shifting data through registers, it is
Test Clock sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
The test clock is used only with the TAP controller. All inputs are and TDO pins. This enables shifting of data through the SRAM
captured on the rising edge of TCK. All outputs are driven from with minimal delay. The bypass register is set LOW (VSS) when
the falling edge of TCK. the BYPASS instruction is executed.
Test Mode Select (TMS) Boundary Scan Register
The TMS input is used to give commands to the TAP controller The boundary scan register is connected to all of the input and
and is sampled on the rising edge of TCK. This pin may be left output pins on the SRAM. Several No Connect (NC) pins are also
unconnected if the TAP is not used. The pin is pulled up included in the scan register to reserve pins for higher density
internally, resulting in a logic HIGH level. devices.
Test Data-In (TDI) The boundary scan register is loaded with the contents of the
The TDI pin is used to serially input information into the registers RAM input and output ring when the TAP controller is in the
and can be connected to the input of any of the registers. The Capture-DR state and is then placed between the TDI and TDO
register between TDI and TDO is chosen by the instruction that pins when the controller is moved to the Shift-DR state. The
is loaded into the TAP instruction register. For information on EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
loading the instruction register, see Figure 5 on page 23. TDI is be used to capture the contents of the input and output ring.
internally pulled up and can be unconnected if the TAP is unused Table 25 on page 28 shows the order in which the bits are
in an application. TDI is connected to the most significant bit connected. Each bit corresponds to one of the bumps on the
(MSB) on any register. SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the Identification (ID) Register
registers. The output is active, depending upon the current state The ID register is loaded with a vendor-specific, 32-bit code
of the TAP state machine (see Table 24 on page 27). The output during the Capture-DR state when the IDCODE command is
changes on the falling edge of TCK. TDO is connected to the loaded in the instruction register. The IDCODE is hardwired into
least significant bit (LSB) of any register. the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
Test Reset (TRST#) information described in Table 22 on page 27.
The TRST# input pin is used to reset the TAP controller.
TAP Instruction Set
Alternatively, a reset may be performed by forcing TMS HIGH
(VDD) for five rising edges of TCK. Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Table 24 on
This reset does not affect the operation of the SRAM and can be page 27. Three of these instructions are listed as RESERVED
performed while the SRAM is operating. At power up, the TAP is and must not be used. The other five instructions are described
reset internally to ensure that TDO comes up in a high Z state. in this section in detail.
TAP Registers Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
Registers are connected between the TDI and TDO pins to scan TDO. During this state, instructions are shifted through the
the data in and out of the SRAM test circuitry. Only one register instruction register through the TDI and TDO pins. To execute
can be selected at a time through the instruction registers. Data the instruction after it is shifted in, the TAP controller must be
is serially loaded into the TDI pin on the rising edge of TCK. Data moved into the Update-IR state.
is output on the TDO pin on the falling edge of TCK.

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

IDCODE The shifting of data for the SAMPLE and PRELOAD phases can
The IDCODE instruction loads a vendor-specific, 32-bit code into occur concurrently when required, that is, while the data
the instruction register. It also places the instruction register captured is shifted out, the preloaded data can be shifted in.
between the TDI and TDO pins and shifts the IDCODE out of the BYPASS
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at When the BYPASS instruction is loaded in the instruction register
power up or whenever the TAP controller is supplied a and the TAP is placed in a Shift-DR state, the bypass register is
Test-Logic-RST state. placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
SAMPLE Z when multiple devices are connected together on a board.
The SAMPLE Z instruction connects the boundary scan register EXTEST
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus The EXTEST instruction drives the preloaded data out through
into a High Z state until the next command is supplied during the the system output pins. This instruction also connects the
Update IR state. Both Port A and Port B are enabled once this boundary scan register for serial access between the TDI and
command has been executed. TDO in the Shift-DR controller [Link] Port A and Port B are
enabled once this command has been executed.
SAMPLE/PRELOAD EXTEST OUTPUT BUS TRISTATE
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When IEEE Standard 1149.1 mandates that the TAP controller be able
the SAMPLE/PRELOAD instructions are loaded into the to put the output bus into a tristate mode.
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured The boundary scan register has output enable control bits
in the boundary scan register. located at Bit #49 and Bit #50. Bit# 49 enables the output pins
for DQB and Bit#50 enables DQA and PE# pins.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock When these scan cells, called the “extest output bus tristate,” are
operates more than an order of magnitude faster. Because there latched into the preload register during the Update-DR state in
is a large difference in the clock frequencies, it is possible that the TAP controller, they directly control the state of the output
during the Capture-DR state, an input or output undergoes a (Q-bus) pins, when the EXTEST is entered as the current
transition. The TAP may then try to capture a signal while in instruction. When HIGH, it enables the output buffers to drive the
transition (metastable state). This does not harm the device, but output bus. When LOW, this bit places the output bus into a
there is no guarantee as to the value that is captured. High Z condition.
Repeatable results may not be possible. These bits can be set by entering the SAMPLE/PRELOAD or
To guarantee that the boundary scan register captures the EXTEST command, and then shifting the desired bit into that cell,
correct value of a signal, the SRAM signal must be stabilized during the Shift-DR state. During Update-DR, the value loaded
long enough to meet the TAP controller’s capture setup plus hold into that shift-register cell latches into the preload register. When
times (tCS and tCH). The SRAM clock input might not be captured the EXTEST instruction is entered, these bits directly controls the
correctly if there is no way in a design to stop (or slow) the clock output Q-bus pins. Note that these bits are pre-set LOW to
during a SAMPLE/PRELOAD instruction. If this is an issue, it is disable the output when the device is powered up, and also when
still possible to capture all other signals and simply ignore the the TAP controller is in the Test-Logic-RST state.
value of the CK and CK captured in the boundary scan register.
Reserved
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary These instructions are not implemented but are reserved for
scan register between the TDI and TDO pins. future use. Do not use these instructions.

PRELOAD places an initial data pattern at the latched parallel

outputs of the boundary scan register cells before the selection
of another boundary scan test operation.

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

TAP Controller State Diagram

Figure 5. TAP Controller State Diagram [3]

1 TEST-LOGIC
RST
0
1
TEST-LOGIC/ 1 SELECT 1 SELECT
0
IDLE DR-SCAN IR-SCAN

0 0
1 1
CAPTURE-DR CAPTURE-IR

0 0

SHIFT-DR 0 SHIFT-IR 0

1 1

1 1
EXIT1-DR EXIT1-IR

0 0

PAUSE-DR 0 PAUSE-IR 0

1 1

0 0
EXIT2-DR EXIT2-IR

1 1

UPDATE-DR UPDATE-IR

1 1
0 0

Note
3. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

TAP Controller Block Diagram

Figure 6. TAP Controller Block Diagram

Bypass Register

2 1 0
Selection Selection
TDI Instruction Register TDO
Circuitry Circuitry
31 30 29 . . 2 1 0

Identification Register

136 . . . . 2 1 0
Boundary Scan Register

TCK
TMS TAP Controller
TRST#

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

TAP Electrical Characteristics

Table 20. TAP Electrical Characteristics
Over the Operating Range

Parameter Description Test Conditions Min Max Unit

VOH LVCMOS High Level Output IOH = 100µA VDD × 0.8 – V
Voltage
VOL LVCMOS Low Level Output IOL = 100 µA – VDD × 0.2 V
Voltage
VIH LVCMOS High Level Input VDD × 0.7 VDD + 0.2 V
Voltage (DC)
VIL LVCMOS Low Level Input –0.2 VDD × 0.3 V
Voltage (DC)
IX LVCMOS Input Leakage Current – 10 A
IOZ LVCMOS Output Leakage – 10 A
Current

TAP AC Switching Characteristics

Table 21. TAP AC Switching Characteristics
Over the Operating Range
Parameter Description Min Max Unit
tTCYC TCK clock cycle time 50 – ns
tTF TCK clock frequency – 20 MHz
tTH TCK clock HIGH 20 – ns
tTL TCK clock LOW 20 – ns
Setup Times
tTMSS TMS setup to TCK clock rise 5 – ns
tTDIS TDI setup to TCK clock rise 5 – ns
tCS Capture setup to TCK rise 5 – ns
Hold Times
tTMSH TMS hold after TCK clock rise 5 – ns
tTDIH TDI hold after clock rise 5 – ns
tCH Capture hold after clock rise 5 – ns
Output Times
tTDOV TCK clock LOW to TDO valid – 10 ns
tTDOX TCK clock LOW to TDO invalid 0 – ns
Note: tCS and tCH refer to setup and hold time requirements of latching data from the boundary scan register.

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

TAP Timing Diagram

Figure 7. TAP Timing Diagram

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Identification Register Definitions

Table 22. Identification Register Definitions
Value
Instruction Field Description
CY7C4122KV12 CY7C4142KV12
Revision Number (31:29) 000 000 Version number.
Cypress Device ID (28:12) 11011010101010011 11011010101100011 Defines the type of SRAM.
Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM
vendor.
ID Register Presence (0) 1 1 Indicates the presence of an ID register.

Scan Register Sizes

Table 23. Scan Register Sizes
Register Name Bit Size
Instruction 3
Bypass 1
ID 32
Boundary Scan 137

Instruction Codes
Table 24. Instruction Codes
Instruction Code Description
EXTEST 000 Captures the input and output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.

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Boundary Scan Order

Table 25. Boundary Scan Order
CY7C4142KV12 CY7C4122KV12
Bit Bump
×36 Device ×18 Device
0 12A DQA<26> DQA<17>
1 13B DQA<19> DQA<10>
2 14A DQA<25> DQA<16>
3 15B DQA<35> NC
4 16A DQA<23> DQA<14>
5 18B DQA<31> NC
6 17C QVLDA<1> QVLDA<1>
7 16C QKA<1> QKA<1>
8 14C DQA<20> DQA<11>
9 12C DQA<18> DQA<9>
10 12D DINVA<1> DINVA<1>
11 13D DQA<22> DQA<13>
12 15D DQA<21> DQA<12>
13 17D QKA#<1> QKA#<1>
14 18E DQA<32> NC
15 15F DQA<24> DQA<15>
16 16F DKA<1> DKA<1>
17 17F DKA#<1> DKA#<1>
18 18G DQA<33> NC
19 16G DQA<34> NC
20 17H DQA<27> NC
21 15H DQA<28> NC
22 16J DQA<30> NC
23 18J DQA<29> NC
24 18K RST# RST#
25 18L DQB<29> NC
26 16L DQB<30> NC
27 15M DQB<28> NC
28 17M DQB<27> NC
29 18N DQB<33> NC
30 16N DQB<34> NC
31 15P DQB<24> DQB<15>
32 16P DKB<1> DKB<1>
33 17P DKB#<1> DKB#<1>
34 18R DQB<32> NC
35 17T QKB#<1> QKB#<1>
36 15T DQB<21> DQB<12>
37 13T DQB<22> DQB<13>
38 12T DINVB<1> DINVB<1>
39 12U DQB<18> DQB<9>
40 14U DQB<20> DQB<11>
41 16U QKB<1> QKB<1>
42 17U QVLDB<1> QVLDB<1>
43 18V DQB<31> NC
44 15V DQB<35> NC
45 13V DQB<19> DQB<10>
46 12W DQB<26> DQB<17>

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Table 25. Boundary Scan Order (continued)

CY7C4142KV12 CY7C4122KV12
Bit Bump
×36 Device ×18 Device
47 14W DQB<25> DQB<16>
48 16W DQB<23> DQB<14>
49 Internal_DQB Internal_DQB
50 Internal_DQA Internal_DQA
51 10W ZQ ZQ
52 10V PE# PE#
53 8P A<15> A<15>
54 7N A<9> A<9>
55 9N NC/1152M NC/576M
56 10P AP AP
57 10N A<2> A<2>
58 11N NC/2304M NC/1152M
59 12P A<16> A<16>
60 13N A<10> A<10>
61 13L A<8> A<8>
62 12M A<12> A<12>
63 11L A<18> A<18>
64 10L RWB# RWB#
65 10M AINV AINV
66 9L A<17> A<17>
67 8M A<11> A<11>
68 7L A<7> A<7>
69 7J A<5> A<5>
70 9J A<19> A<19>
71 10K CK# CK#
72 10J CK CK
73 11J A<20> A<20>
74 13J A<6> A<6>
75 12H LDB# LDB#
76 10H RWA# RWA#
77 8H LDA# LDA#
78 7G A<3> A<3>
79 9G NC/288M A<21>
80 10G A<1> A<1>
81 11G NC/576M NC/288M
82 13G A<4> A<4>
83 12F A<14> A<14>
84 10F A<0> A<0>
85 8F A<13> A<13>
86 10D CFG# CFG#
87 10B LBK#<1> LBK#<1>
88 10A LBK#<0> LBK#<0>
89 8A DQA<8> DQA<8>
90 7B DQA<1> DQA<1>
91 6A DQA<7> DQA<7>
92 5B DQA<17> NC
93 4A DQA<5> DQA<5>
94 2B DQA<13> NC
95 3C QVLDA<0> QVLDA<0>

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Table 25. Boundary Scan Order (continued)

CY7C4142KV12 CY7C4122KV12
Bit Bump
×36 Device ×18 Device
96 4C QKA<0> QKA<0>
97 6C DQA<2> DQA<2>
98 8C DQA<0> DQA<0>
99 8D DINVA<0> DINVA<0>
100 7D DQA<4> DQA<4>
101 5D DQA<3> DQA<3>
102 3D QKA#<0> QKA#<0>
103 2E DQA<14> NC
104 3F DKA#<0> DKA#<0>
105 4F DKA<0> DKA<0>
106 5F DQA<6> DQA<6>
107 4G DQA<16> NC
108 2G DQA<15> NC
109 3H DQA<9> NC
110 5H DQA<10> NC
111 4J DQA<12> NC
112 2J DQA<11> NC
113 2L DQB<11> NC
114 4L DQB<12> NC
115 5M DQB<10> NC
116 3M DQB<9> NC
117 2N DQB<15> NC
118 4N DQB<16> NC
119 5P DQB<6> DQB<6>
120 4P DKB<0> DKB<0>
121 3P DKB#<0> DKB#<0>
122 2R DQB<14> NC
123 3T QKB#<0> QKB#<0>
124 5T DQB<3> DQB<3>
125 7T DQB<4> DQB<4>
126 8T DINVB<0> DINVB<0>
127 8U DQB<0> DQB<0>
128 6U DQB<2> DQB<2>
129 4U QKB<0> QKB<0>
130 3U QVLDB<0> QVLDB<0>
131 2V DQB<13> NC
132 5V DQB<17> NC
133 7V DQB<1> DQB<1>
134 8W DQB<8> DQB<8>
135 6W DQB<7> DQB<7>
136 4W DQB<5> DQB<5>

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Maximum Ratings Operating Range

Exceeding maximum ratings may impair the useful life of the Table 26. Operating Range
device. These user guidelines are not tested.
Case
Storage Temperature ............................... –65 °C to +150 °C Range VDD VDDQ
Temperature (TC)
Ambient Temperature Commercial 0 °C to +70 °C 1.25 ± 50 mV 1.1 V ± 50 mV
with Power Applied .................................. –55 °C to +125 °C
1.2 V ± 50 mV
Maximum Junction Temperature ............................... 125 °C
Supply Voltage on Neutron Soft Error Immunity
VDD Relative to GND .................................–0.3 V to +1.35 V
Table 27. Neutron Soft Error Immunity
Supply Voltage on
VDDQ Relative to GND ...............................–0.3 V to +1.35 V Test
Parameter Description Conditions Typ Max* Unit
DC Input Voltage .......................................–0.3 V to +1.35 V
Current into Outputs (LOW) ........................................ 20 mA LSBU Logical 25 °C 0 0.01 FIT/Mb
single-bit
Static Discharge Voltage upsets
(MIL-STD-883, M. 3015) ......................................... > 2001V
LMBU Logical 25 °C 0 0.01 FIT/Mb
Latch up Current .................................................... > 200 mA multi-bit
upsets
SEL Single event 85 °C 0 0.1 FIT/Dev
latch-up
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to Application
Note, Accelerated Neutron SER Testing and Calculation of Terrestrial Failure
Rates – AN54908.

Electrical Characteristics
Table 28. Electrical Characteristics
Over the Operating Range
Parameter Description Min Typ Max Unit
POD Signaling Mode
VDD[4] Core supply voltage (1.25 V ± 50 mV) 1.2 1.25 1.3 V
VDDA [4] Analog supply voltage (1.25 V ± 30 mV) 1.22 1.25 1.28 V
VDDQ [4] POD I/O supply voltage (1.1 V ± 50 mV) 1.05 1.1 1.15 V
POD I/O supply voltage (1.2 V ± 50 mV) 1.15 1.2 1.25 V
VREF [4, 5] POD Reference voltage VDDQ × 0.69 VDDQ × 0.7 VDDQ × 0.71 V
VOL(DC) [4] POD Low level output voltage (DC) – – 0.5 V
VIH(DC) [4] POD High level input voltage (DC) VREF + 0.08 – VDDQ + 0.15 V
VIL(DC) [4] POD Low level input voltage –0.15 – VREF – 0.08 V
VIH(AC) [4] POD High level input voltage (DC) VREF + 0.15 – – V
VIL(AC) [4] POD Low level input voltage – – VREF – 0.15 V
VMP(DC) POD Differential Input Mid-Point Voltage; Pin and Pin# VREF – 0.08 – VREF + 0.08 V
VID(DC) POD Differential Input Differential Voltage (DC); Pin and Pin# 0.16 – – V
VID(AC) POD Differential Input Differential Voltage (AC); Pin and Pin# 0.30 – – V
VIN POD Single-ended Input Voltage; Pin and Pin# 0.27 – VDDQ + 0.15 V
VINS POD Single-ended Input Voltage Slew Rate; Pin and Pin# 3 – – V/ns
VIX(AC) POD Differential Input Crossing Point Voltage (AC); Pin and VREF – 0.08 – VREF + 0.08 V
Pin#
Notes
4. All voltages referenced to VSS (GND).
5. Peak to Peak AC noise on VREF must not exceed +/–2% VDDQ(DC).

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Table 28. Electrical Characteristics (continued)

Over the Operating Range
Parameter Description Min Typ Max Unit
IX [6] POD Input leakage current – – 200 µA
IOZ [6] POD Output leakage current – – 200 µA
IDD VDD operating supply (1066 MHz, ×18) – – 3600 mA
VDD operating supply (1066 MHz, ×36) – – 4000 mA
VDD operating supply (933 MHz, ×18) – – 2900 mA
VDD operating supply (933 MHz, ×36) – – 3300 mA
IDDA VDDA operating supply – – 500 mA

HSTL/SSTL Signaling Mode

VDD[7] Core supply voltage (1.25 V ± 50 mV) 1.2 1.25 1.3 V
VDDA[7] Analog supply voltage (1.25 V ± 30 mV) 1.22 1.25 1.28 V
VDDQ [7] I/O supply voltage (1.2 V ± 50 mV) 1.15 1.2 1.25 V
I/O supply voltage (1.25 V ± 50 mV) 1.2 1.25 1.3 V
VREF(DC) [7, 8] HSTL/SSTL Reference voltage (DC) VDDQ × 0.48 VDDQ × 0.5 VDDQ × 0.52 V
VREF(AC) [7, 8] HSTL/SSTL Reference voltage (AC) VDDQ × 0.47 VDDQ × 0.5 VDDQ × 0.53 V
VIH(DC) [7] HSTL/SSTL High level input voltage (DC) VREF + 0.08 – VDDQ + 0.15 V
VIL(DC) [7] HSTL/SSTL Low level input voltage (DC) –0.15 – VREF – 0.08 V
VIH(AC) [4] HSTL/SSTL High level input voltage (AC) VREF + 0.15 – VDDQ + 0.24 V
VIL(AC) [4] HSTL/SSTL Low level input voltage (AC) –0.24 – VREF – 0.15 V
VOH(DC) [4] HSTL/SSTL High level output voltage (DC) – VDDQ × 0.712 VDDQ × 0.75 – V
IOH = –0.25 × VDDQ/ROH
VOL(DC) [4] HSTL/SSTL Low level output voltage (DC) – – VDDQ × 0.25 VDDQ × 0.288 V
IOL = 0.25 × VDDQ/ROL
VIX HSTL/SSTL Input Voltage Cross point – VDDQ × 0.5 – V
VDIF(AC) HSTL/SSTL AC Input Differential Voltage 0.30 – VDDQ + 0.48 V
VDIF(DC) HSTL/SSTL DC Input Differential Voltage 0.16 – VDDQ + 0.30 V
VDIF(CM) HSTL/SSTL DC Common Mode Input VDDQ × 0.4 VDDQ × 0.5 VDDQ × 0.6 V
VOX HSTL/SSTL Output voltage cross point – VDDQ × 0.5 – V
VOUT(AC) HSTL/SSTL AC Output Voltage –0.24 – VDDQ + 0.24 V
VOUT(DC) HSTL/SSTL DC Output Voltage –0.15 – VDDQ + 0.15 V
[6]
IX HSTL/SSTL Input leakage current – – 200 µA
IOZ [6] HSTL/SSTL Output leakage current – – 200 µA
IDD VDD operating supply (1066 MHz, ×18) – – 3600 mA
VDD operating supply (1066 MHz, ×36) – – 4000 mA
VDD operating supply (933 MHz, ×18) – – 2900 mA
VDD operating supply (933 MHz, ×36) – – 3300 mA
IDDA VDDA operating supply – – 500 mA

Notes
6. Output driver into High Z with ODT disabled.
7. All voltages referenced to VSS (GND).
8. Peak to Peak AC noise on VREF must not exceed +/–2% VDDQ(DC).

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Capacitance
Table 29. Capacitance
Parameter [9] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VDD = 1.25 V, VDDQ = 1.25 V 4 pF
CO Output capacitance 4 pF

Thermal Resistance
Table 30. Thermal Resistance
361-ball FCBGA
Parameter [9] Description Test Conditions Unit
Package
JA Thermal resistance Test conditions follow standard test methods and 11.4 °C/W
(junction to ambient) procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
JC Thermal resistance 0.04 °C/W
(junction to case)

AC Test Loads and Waveforms

Figure 8. AC Test Loads and Waveforms

Note
9. Tested initially and after any design or process change that may affect these parameters.

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Switching Characteristics
Table 31. Switching Characteristics
Over the Operating Range [10, 11, 12, 13, 14, 15, 16, 17, 18]

Cypress 1066 MHz 933 MHz

Description Unit
Parameter Min Max Min Max
tCK CK, DKx, QKx clock Period 0.938 1.875 1.071 2.143 ns
tCKL CK, DKx LOW time 0.45* – 0.45* – tCK
tCKH CK, DKx HIGH time 0.45* – 0.45* – tCK
tJIT(per) Clock Period Jitter –0.055 0.055 –0.060 0.060 ns
tJIT(cc) Cycle to Cycle Jitter – 0.110 – 0.120 ns
tAS A to CK setup 0.125 – 0.135 – ns
tAH CK to A hold 0.125 – 0.135 – ns
tCS LDx#, RWx# to CK setup 0.150 – 0.180 – ns
tCH CK to LDx#, RWx# hold 0.150 – 0.180 – ns
tCKDK CK to DKx skew –0.15 0.15 –0.172 0.172 ns
tIS DQx, DINVx to DKx setup 0.125 – 0.135 – ns
tIH DKx to DQx, DINVx hold 0.125 – 0.135 – ns
tRise Input/Output Signal Rise time 20%–80% 4 – 3 – V/ns
tFall Input/Output Signal Fall time 20%–80% 4 – 3 – V/ns
tQKL QKx LOW time 0.45* – 0.45* – tCK
tQKH QKx HIGH time 0.45* – 0.45* – tCK
tCKQK CK to QKx skew –0.225 0.225 –0.257 0.257 ns
tQKQ0 QKx[0] to DQx[17:0], DINVx[0] (×36) or – 0.075 – 0.085 ns
QKx[0] to DQx[8:0], DINVx[0] (×18)
tQH0 QKx[0] to DQx[17:0], DINVx[0] (×36) or 0.40* – 0.40* – tCK
QKx[0] to DQx[8:0], DINVx[0] (×18)
tQKQ1 QKx[1] to DQx[35:18], DINVx[1] (×36) or – 0.075 – 0.085 ns
QKx[1] to DQx[17:9], DINVx[1] (×18)
tQH1 QKx[1] to DQx[35:18], DINVx[1] (×36) or 0.40* – 0.40* – tCK
QKx[1] to DQx[17:9], DINVx[1] (×18)
tQKQV0 QKx[0] to QVLDx – 0.112 – 0.128 ns
tQVH0 QKx[0] to QVLDx 0.85* – 0.85* – tCK
tQKQV1 QKx[1] to QVLDx – 0.112 – 0.128 ns
tQVH1 QKx[1] to QVLDx 0.85* – 0.85* – tCK
tPWR VDD (Typical) to the first access 200 – 200 – ms
tRSS RST# pulse width 200 – 200 – µs
tRSH RST# deasserted to first active command 400000* – 400000* – tCK

Notes
10. x refers to Port A and Port B. For example, DQx refers to DQA and DQB.
11. All input hold timing assumes rising edge slew rate of 2 V/ns measured from VIL/VIH (DC) to VREF.
12. All input setup timing assumes falling edge slew rate of 2 V/ns measured from VREF to VIL/VIH (AC).
13. All output timing assumes the load shown in Figure 1
14. Setup/hold windows, tASH, tCSH, tISH are used for de-skew timing budgeting and are based on electrical simulations. These cannot be directly measured without
performing de-skew training.
15. tCK(avg) is the value of tCK averaged over 200 clock cycles.
16. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
17. Frequency drift is not allowed.
18. tQKQ, tQKQX are guaranteed by design.

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Table 31. Switching Characteristics (continued)

Over the Operating Range [10, 11, 12, 13, 14, 15, 16, 17, 18]

Cypress 1066 MHz 933 MHz

Description Unit
Parameter Min Max Min Max
tRDS A to RST# setup 500* – 500* – tCK
tRDH A to RST# hold 500* – 500* – tCK
tTSS TRST# pulse width 200 – 200 – µs
tTSH TRST# deasserted to first JTAG command 200 – 200 – µs
tPLL Time for PLL to stabilize after being reset – 100 – 100 µs
tLBL Loopback Latency 16* 16* 16* 16* tCK
tCD Loopback Output Delay – 5 – 5 ns
tCFGS Active mode to Configuration mode 32* – 32* – tCK
tCFGH Configuration mode to Active mode Register Access 32* – 32* – tCK
without ODT or PLL programming updates
tCFGH Configuration mode to Active mode Register Access with 4096* – 4096* – tCK
ODT programming updates
tCFGH Configuration mode to Active mode Register Access with 100 – 100 – µs
PLL programming updates
tCFGD Configuration command to Configuration command 80* – 80* – tCK
tCLDS CFG# assertion to LDA# assertion 32* – 32* – tCK
tCLDH LDA# deassertion to CFG# deassertion 32* – 32* – tCK
tCLDW LDA# pulse width for Configuration command 16* – 16* – tCK
tCRDL LDA# assertion to Read Data Latency – 32* – 32* tCK
tCRDH CFG# deassertion to Read Data Hold 0* 32* 0* 32* tCK
tDQVLD DQAx to QVLDA<0> in Configuration Mode –2 2 –2 2 tCK

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Switching Waveforms
Figure 9. Input and Output Timing Waveforms

Address and Command Input Timing

Data Input Timing

Data Output Timi ng

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Switching Waveforms (continued)

Figure 10. Waveforms for 8.0 Cycle Read Latency (Read to Write Timing Waveform)

Figure 11. Waveforms for 8.0 Cycle Read Latency (Write to Read Timing Waveform)

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Switching Waveforms (continued)

Figure 12. Configuration Write Timing Waveform

Figure 13. Configuration Read Timing Waveform

Note: DQA[x:8] and DQB data bus is a don’t care in Configuration Mode

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Switching Waveforms (continued)

Figure 14. Configuration Write and Read Timing Waveform
(a) Configuration Multiple Cycle - Write followed by Read Operation

Note: DQA[x:8] and DQB data bus is a don’t care in Configuration Mode

(b) Configuration Multiple Cycle - Back to Back Read Operation

Note: DQA[x:8] and DQB data bus is a don’t care in Configuration Mode

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Switching Waveforms (continued)

Figure 15. Loopback TIming

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Switching Waveforms (continued)

Figure 16. Reset TImings

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Ordering Information
The following table Table 32 contains only the parts that are currently available. If you do not see what you are looking for, contact
your local sales representative. For more information, visit the Cypress website at [Link] and refer to the product
summary page at [Link]
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at [Link]
Table 32. Ordering Information
Speed Package Operating
Ordering Code Package Type
(MHz) Diagram Range
1066 / Contact Sales 001-70319 361-ball FCBGA (21 × 21 × 2.515 mm) Commercial
933

Table 33. Ordering Code Definitions

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 PRELIMINARY CY7C4122KV12, CY7C4142KV12

Package Diagram
Figure 17. 361-ball FCBGA (21 × 21 × 2.515 mm) FR0AA Package Outline, 001-70319

001-70319 *B

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Acronyms Document Conventions

Table 34. Acronyms used in this document Units of Measure
Acronym Description Table 35. Units of Measure
DDR Double Data Rate Symbol Unit of Measure
RTR Random Transaction Rate °C degree Celsius
EIA Electronic Industries Alliance MHz megahertz
EMI Electromagnetic Interference µA microampere
FCBGA Flip-Chip Ball Grid Array µs microsecond
I/O Input/Output mA milliampere
JEDEC Joint Electron Devices Engineering Council mm millimeter
JTAG Joint Test Action Group ms millisecond
LMBU Logical Multiple Bit Upset mV millivolt
LSB Least Significant Bit ns nanosecond
LSBU Logical Single Bit Upset  ohm
MSB Most Significant Bit % percent
ODT On-Die Termination pF picofarad
PLL Phase Locked Loop V volt
QDR Quad Data Rate W watt
SDR Single Data Rate
SEL Single Event Latch-up
SER Soft Error Rate
SRAM Static Random Access Memory
TAP Test Access Port
TCK Test Clock
TDI Test Data-In
TDO Test Data-Out
TMS Test Mode Select

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Document History Page

Document Title: CY7C4122KV12/CY7C4142KV12, 144-Mbit QDR™-IV GT SRAM
Document Number: 001-68255
Submission Orig. of
Rev. ECN Description of Change
Date Change
** 3291924 06/24/2011 JMNO New data sheet.
*A 3643435 07/10/2012 NJY / AVIA Changed status from Advance to Preliminary.
Updated Title (Changed part numbers (from CYQ40422KV12 to
CY7C4122KV12, from CYQ40442KV12 to CY7C4142KV12)).
Updated Features (Changed Read latency from 7 to 8 clock cycles, included
reference to JEDEC JESD8-16A standard).
Updated Configurations (Changed part numbers (from CYQ40422KV12 to
CY7C4122KV12, from CYQ40442KV12 to CY7C4142KV12)).
Updated Functional Description.
Updated Logic Block Diagram – CY7C4122KV12 (Changed part number (from
CYQ40422KV12 to CY7C4122KV12) and updated diagram).
Updated Logic Block Diagram – CY7C4142KV12 (Changed part number (from
CYQ40442KV12 to CY7C4142KV12) and updated diagram).
Updated Pin Configurations (Changed part numbers (from CYQ40422KV12 to
CY7C4122KV12, from CYQ40442KV12 to CY7C4142KV12)).
Updated Pin Definitions (Removed VSSA pin and its details).
Updated Functional Overview (Changed part numbers (from CYQ40422KV12
to CY7C4122KV12, from CYQ40442KV12 to CY7C4142KV12), updated
Configuration Registers Description, updated Configuration Register
Definitions).
Updated TAP Controller Block Diagram (Changed Boundary Scan Register
value from 108 to 136).
Updated Identification Register Definitions (Changed part numbers (from
CYQ40422KV12 to CY7C4122KV12, from CYQ40442KV12 to
CY7C4142KV12), updated Cypress Device ID (28:12) from TBD with their
respective values).
Updated Boundary Scan Order (Changed Bump ID for Bit 130 from 3P to 3U).
Updated Operating Range (Removed Industrial Range related information).
Updated Electrical Characteristics.
Updated Capacitance (Changed maximum value of CIN parameter from 1.5 pF
to 6 pF, changed maximum value of CO parameter from 2.0 pF to 6 pF).
Updated Switching Characteristics.
Updated Switching Waveforms (Changed Read latency from 7 to 8 clock
cycles).Updated Ordering Code Definitions.
Updated Package Diagram (spec 001-70319 (changed revision from ** to *A)).
*B 3708121 08/09/2012 NJY Updated Electrical Characteristics (Changed minimum value of VIH(DC) from
(VREF + 0.8) V to (VREF + 0.08) V, changed maximum value of IX parameter
from 100 µA to 200 µA, changed maximum value of IOZ parameter from 100 µA
to 200 µA).
Updated Package Diagram (spec 001-70319 (Changed revision from *A to *B)).
*C 3811655 11/20/2012 NJY Updated Features (To include maximum frequency).
Updated Functional Description (Included “Training sequence for per-bit
deskew”).
Updated Pin Definitions (Updated description of TRST# pin).
Updated Functional Overview (Updated Read and Write Data Cycles (Changed
read latency from 5 clock cycles to 8 clock cycles and changed write latency
from 8 clock cycles to 5 clock cycles), updated Configuration Registers
Description (Removed Register Address (8–15, 16–31) and their descriptions),
updated Configuration Register Definitions (Updated Address 1: Impedance
Control Register (Read/Write), removed Address 16: Test Mode Register
(Read/Write))).
Added TAP Electrical Characteristics.
Added TAP AC Switching Characteristics.

Document Number: 001-68255 Rev. *E Page 45 of 47

 PRELIMINARY CY7C4122KV12, CY7C4142KV12

Document History Page (continued)

Document Title: CY7C4122KV12/CY7C4142KV12, 144-Mbit QDR™-IV GT SRAM
Document Number: 001-68255
Submission Orig. of
Rev. ECN Description of Change
Date Change
*D 3928881 03/12/2013 PRIT Updated Functional Overview (Updated Configuration Register Definitions
(Added a Note at the bottom of the table “Address 0: Termination Control
Register (Read/Write)”), updated I/OType and Port Enable Bit Definitions
(Updated Port Enable Bit Definition), updated ODT Termination Bit Definitions
(Updated Clock Input Group Bit Definition, Address/Command Input Group Bit
Definition, Data Input Group Bit Definition)).

Updated Pin Configurations.

Updated TAP AC Switching Characteristics (Added a Note “tCS and tCH refer
to setup and hold time requirements of latching data from the boundary scan
register.” at the bottom of the table).

Added TAP Timing Diagram.

Updated Capacitance (Changed value of CIN and CO parameters from 6 pF to

4 pF).

Updated Thermal Resistance (Changed value of JA parameter from TBD to

11.4 °C/W for 361-ball FCBGA Package, changed value of JC parameter from
TBD to 0.04 °C/W for 361-ball FCBGA Package).

Updated Switching Characteristics (Added tDQVLD parameter and its details).

Updated Switching Waveforms (Updated Figure 6, Figure 7, Figure 8,

Figure 9).
*E 3947210 04/12/2013 NJY / PRIT Updated Document Title to read as “CY7C4122KV12/CY7C4142KV12,
144-Mbit QDR™-IV GT SRAM”.
Updated Features.
Added Note 1 and referred the same note in “Total Random Transaction Rate”.
Updated Functional Description.
Updated Pin Definitions (Updated description column).
Updated Functional Overview:
Updated Deskew Training Sequence (Added reference of Figure 15).
Updated I/O Signaling Standards (Updated HSTL/SSTL Signaling (Removed
“20, 30 ohms” in setting of ODT termination values and 34 ohms in setting for
Drive Strength values)).
Updated Configuration Register Definitions(Added Note beneath Table 5 -
Address 0: Termination Control Register ; Changed Bit 3 description from “PLL
Disable” to “PLL Reset” in Table 7-Address 2: Option Control Register;
Corrected typo in Table 9-Address 4: Address Parity Status Register 0 table).
Updated Drive Strength Bit Definitions in Table 18 and Table 19
(To remove 28 ohm, 33 ohm and 34 ohm values respectively).
Updated Ordering Information in Table 32(Replaced TBD in Ordering code with
“Contact Sales“, updated Ordering Code Definitions in Table 33(To reflect
updated Title)).

Document Number: 001-68255 Rev. *E Page 46 of 47

 PRELIMINARY CY7C4122KV12, CY7C4142KV12

Sales, Solutions, and Legal Information

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closest to you, visit us at Cypress Locations.

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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-68255 Rev. *E Revised April 12, 2013 Page 47 of 47

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document
may be the trademarks of their respective holders.