Question bank-COA for remedial (UNIT-1,2,3,4)
(1) Convert 45(decimal) into octal, hexadecimal and binary.
(2) Explain block diagram of computer.
(3) Explain Flynn’s classification of Computer Architecture.
(4) Explain Flynn’s classification based on instruction and data stream.
(5) Explain the difference between Von Neumann and Harvard Architecture.
(6) Explain Amdahl’s law and derive speedup equation.
(7) How are numbers represented in computer system? Explain any number representation in
detail.
(8) CALCULATE CPI AND MIPS FOR CPU WITH 200 MHZ FREQUENCY WHICH IS EXECUTING A
BENCHMARK PROGRAM WITH FOLLOWING INSTRUCTION MIX.
INSTRUCTION CATEGORY PERCENTAGE OF NO. OF CYCLES PER
OCCURRENCE INSTRUCTION
ALU 38 1
LOAD AND STORE 15 3
BRANCH 42 4
OTHERS 5 5
(9) Explain bus architecture and explain 3 types of buses with diagram.
(10) Explain Register and their types.
(11) Explain Types of registers in 8085.
(12) What are the different types of control lines used in computer? Explain its functions.
(13) Compare RISC and CISC.
(14) Explain different types of Addressing modes with diagram.
(15) Explain different types of Addressing modes of 8085 in detail.
(16) Explain block diagram of 8085 microprocessor.
(17) Define flag register and explain 5 flags.
(18) Design the timing diagram for STA 526A. opcode for STA= 32H.
(19) Explain 0 address, 1 address, 2 address, 3 address instructions with x= (A*B) + (C*D)
example.
(20) Explain instructions-PUSH, ADD, JMP, AND, LDA.
(21) Explain memory system in detail.
(22) Difference between Register Stack and Memory Stack.
(23) Explain instruction execution cycle with timing diagram or flow chart.
(24) Explain Types of Instruction Format.
(25) Explain General Register Organization with diagram.
(26) What is Pipelining? Explain different types of pipelining.
(27) Describe the significance of parallel processing with example.
(28) Explain different types of hazards that can occur in a pipeline.
(29) Explain Flynn’s taxonomy for parallel processing.
(30) Define vector processing.
(31) Write the methods for avoiding hazard.
(32) Explain types of Array processors.
(33) Explain 6-stage pipeline with diagram.
(34) Explain 4-stage pipeline with diagram.
(35) Draw timing diagram for micro-operation IN C0H. Opcode for (IN) = DBH.
(36) Compare RAM, ROM and Cash Memory.
(37) Difference between Primary Memory and Secondary Memory.
(38) Write a short note on magnetic tape.
(39) Write a short note on Virtual Memory with diagram.
(40) Explain Demand Paging with diagram.
(41) Explain Locality of Reference in Cash Memory.
(42) Define Cache memory address mapping. Explain 3 types of Cache-Memory mapping
algorithm (Direct mapping, Fully Associative mapping and Set-Associative mapping) with
figure in detail.
(43) Explain Page Replacement algorithm with example (FIFO, LRU and Optimal Page
Replacement).
(44) Cache access Time=20 ns, Memory access Time= 200ns, Hit Ratio=90%. Find Average Access
Time?
(45) A system uses LRU page replacement policy. Assume that all the page frames are initially
empty. What is the total number of page faults that will occur while processing the page
reference string given below?
Total number of references=5,8,7,2,8,7,2,3,8,3=10 and calculate the Hit Ratio and Miss
Ratio.
(46) A system uses FIFO page replacement policy. Assume that all the page frames are initially
empty. What is the total number of page faults that will occur while processing the page
reference string given below?
Total number of references=5,8,7,2,8,7,2,3,8,3=10 and calculate the Hit Ratio and Miss
Ratio.
(47) A system uses Optimal page replacement policy. Assume that all the page frames are initially
empty. What is the total number of page faults that will occur while processing the page
reference string given below?
Total number of references=5,8,7,2,8,7,2,3,8,3=10 and calculate the Hit Ratio and Miss
Ratio.
(48) Consider a pipeline having 4 phases with duration 60, 40, 80 and 70 ns. Given latch delay is
10 ns. Calculate Speedup Ratio, Pipeline Cycle time and Non-pipeline execution time.
