5LIH0: Digital Integrated Circuit Design

Lab assignment: Inverter Design & Analysis

Guru Prasad Murugan
[Link]@[Link] and 2093669
F. Tape-Out and Fabrication:
I. INTRODUCTION • GDSII File Generation: Generate the final GDSII
Full-custom design is an in-depth approach to integrated file, which is a standard format for describing the
circuit (IC) design that gives engineers total control over the layout.
layout of individual transistors and their connections. This • Foundry Submission: Submit the GDSII file to the
high degree of customization enables optimal performance foundry for fabrication.
and area efficiency but requires considerable design effort and
expertise. The subsequent stages in the design flow are as II. LAB DESCRIPTION
follows. A transistor-level schematic has been designed in this
A. System-Level Design: experiment. A CMOS inverter comprises a complementary
• Architectural Design: Define the overall system pair of transistors, a PMOS and an NMOS, arranged in a
architecture by detailing the functional blocks, data stacked configuration. This arrangement enables the circuit to
pathways, and control mechanisms. generate the inverse of the input signal. PMOS and NMOS
• Specification: Develop a detailed specification that are used from the NCSU_Devices_FreePDK45 library while
outlines the circuit's performance criteria (including other components such as DC voltage source, square wave
speed, power consumption, and area), functional generator, and capacitors are used from the analogLib library.
behavior, and interface requirements. Using the wire function the connections are made
B. Logic Design: accordingly.
• RTL Design: Develop an RTL description of the Similarly, for layout design, the layers in the panel are used
circuit using HDL (e.g., Verilog or VHDL) to to draw the layout to realize the inverter. NMOS and PMOS
capture its hierarchical behavior. are created using the active layer, and contacts are placed into
• Synthesis: Utilize synthesis tools to convert the RTL them they are connected using a polysilicon layer. NMOS is
design into a gate-level netlist, detailing the logic placed inside a P-well and PMOS inside an N-well. The metal
gates' types and sizes. layer is used to connect the gate terminals, drain, and source
C. Circuit Design: terminals, followed by input and output. Pins are established.
• Transistor-Level Design: Design and interconnect A. Schematic Entry
individual transistors to implement the logic gates, Describe the schematic entry procedure.
selecting appropriate sizes and topologies to meet
performance and area constraints.
• Layout Design: Create the physical layout by placing
and routing transistors and interconnects on the chip,
considering power distribution, signal integrity, and
timing constraints.
D. Verification and Simulation:
• Functional Simulation: Simulate the RTL design to
verify its functional correctness.
• Timing Simulation: Simulate the gate-level netlist to
analyze timing performance and identify potential
timing violations.
• Static Timing Analysis (STA): Perform STA to
identify and fix timing issues before tape-out.
• Layout Verification: Ensure the layout meets design
rules and design intent.
E. Physical Verification:
• Design Rule Check (DRC): Verify that the layout Fig. 1. The circuit schematic of an inverter.
adheres to the foundry's design rules. NMOS of length 50nm and width 95nm and PMOS of
• Layout vs. Schematic (LVS): Check that the layout length 50nm and width 150nm have been used to create the
accurately represents the schematic. transistor-level design. The W/L ratio of NMOS is 1.9 and
that of PMOS is 3.
 Fig 2. Inverter symbol
B. Layout Edit
Describe the layout editing procedure. Fig. 5. DC analysis output of 0 load capacitance output

Noise margin calculation

Input Input Output Output Input Output

Low High Low High NM NM
VIL VIH VOL VOH
439.19 579.78 49.767 950.55 140.59 900.783
mV mV mV mV mV mV

D. Transient analysis

Load case Rise Fall Rising Falling Average

Time Time Prop. Prop. Prop.
tr tf Delay Delay Delay
tpdr tpdf tpd

0-load 116.977 113.776 12.308 14.768 13.539

Capacitance ps ps ps ps ps
50f F 709.523 721.384 432.812 523.03 480.422
Capacitance ps ps ps ps ps
1 inverter 26.610 26.902 34.268 41.808 38.039 p
Fig. 3. The layout of an inverter. ps ps ps ps
C. DC Analysis FO4 37.095 37.627 61.586 75.136 68.362
Inverters ps ps ps ps ps
DC analysis has been performed for the different loads
mentioned. 500f F 5.772 5.980 2.726 3.325 3.026 ns
Capacitance ns ns ns ns

Fig. 4. Circuit of an inverter with 0 load capacitance

Fig. 6. Rise time of 0-load Capacitance
 Fig. 7. Fall time of 0-load capacitance Fig. 11. Propagation delay of 50f F load

Fig. 12. Rise time of 500f F load capacitance

Fig. 8. Propagation delay of 0-load Capacitance

Fig. 13. Fall time of 500f F load capacitance

Fig. 9. Rise time of 50f F Capacitance

Fig. 14. Propagation delay of 500f F load capacitance

Fig. 10. Fall time of 50f F Capacitance

 F. LVS (Layout vs Schematic)
• An LVS tool ensures precise circuit verification by
measuring the actual device geometries across the
entire chip, providing a comprehensive assessment
of physical parameters.
• LVS is done similar to DRC using calibre function
and loading LVS design rules.
G. PEX
Parasitic extraction (PEX) refers to the process of
calculating the parasitic effects present in both the designed
components and the necessary wiring interconnects of an
Fig. 15. Rise time of 1 inverter load electronic circuit. PEX is run using calibre function and
layout is extracted.
H. Post-layout simulation

Load case Schematic simulation Layout simulation

Rise Time Fall Rise Fall
tr time Time time
tf tr tf
0-load 116.977 113.776 135.785 132.462
Capacitance ps ps ps ps
50f F 709.523 721.384 729.634 742.998
Capacitance ps ps ps ps
1 inverter 26.610 26.902 42.125 42.612
Fig. 16. Fall time of 1 inverter load ps ps ps ps
FO4 37.095 ps 37.627 56.124 61.898
Inverters ps ps ps
500f F 5.772 ns 5.980 ns 6.786 ns 6.992 ns
Capacitance

There is a difference between the rise time and fall time of

the schematic and layout simulation since there is parasitic
capacitance and parasitic resistances are considered during
layout simulation. Therefore, there is a delay caused in the
propagation of the signal.

Fig. 17. Propagation delay of 1 inverter load III. PITFALLS AND TRICKS
When designing the layout DRC needs to be followed
E. DRC (Design Rule Check) according to the DRC rules.
• Once the layout has been drawn, DRC is run by clicking While choosing analysis, instead of choosing from the
calibre → Run nmDRC toolbar from the top, it could also be chosen from the right-
• In the dialogue box, provide the location of the rulesets side menu.
and then click run DRC. This pops up the results.
IV. CONCLUSIONS
An inverter circuit has been designed successfully and
demonstrated that maintains consistent rise and fall times.
Transistor has been sized and biased optimally.
Impact of Load Capacitance: As anticipated, increasing
load capacitance led to slower rise and fall times. However,
the inverter design countered this effect by providing
adequate drive strength.
Transistor Sizing and Biasing: Proper transistor sizing and
precise biasing were essential in achieving the desired
performance. The optimized design ensured efficient
charging and discharging of the load capacitance.

Fig. 6. DRC test results