5SFC0 Advanced CMOS design - Design a fully differential OTA

Guru Prasad Murugan

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[Link] REQUIREMENTS values of Vcm resulted lower gain since there was gain due to
1.1 The input and the output should be differential. first stage however, gain due to second stage was nullified.
Determine realistic input source resistance and load
capacitance. Design CMFB circuit for the output and
a circuit to set the CM for the input (the input signal
should be AC coupled);
The transient response provided below exhibits that
differential inputs (vinn, vinp) were given and differential
outputs (vout_n, vout_p) were obtained. The schematic
depicts circuit with tunable common mode and AC coupled
input. Fig 3. Parametric transient analysis by sweeping common
mode voltage value

Fig 4. Parametric analysis by sweeping Rm value

Fig 1. Schematic

Fig 5. Parametric analysis by sweeping Vcm value

1.4. The unity gain bandwidth should be at least 0.1 GHz;
You can excel here by boosting the bandwidth of the OTA
while minding the power efficiency
Gain of 55 dB was obtained and unity-gain
bandwidth was obtained at 3.03836 GHz.
Fig 2. Transient response
1.2 The output common-mode should be stabilized at an
optimal level. The output common-mode can be tunable in
a range of at least 50mV.
Quantities such as width, length, number of fingers,
miller resistance and capacitance and common mode voltage
were parameterized. Furthermore, DC operating points were
determined, AC analysis was performed and transient
analysis was performed to look for distortions in the output Fig 6. Gain and unity gain bandwidth
and to determine common mode voltage accordingly. From Parameter Value
figure 3 it could be observed that when common mode voltage Gain 55 dB
value is swept below 500 mV gives rise to unstable output. Length 600 nm
Therefore 500 mV is chosen as common mode voltage, V cm. Number of fingers 64
1.3 The gain at low frequencies of the OTA should be Width 600 nm
more than 40dB CL 20 fF
Similarly, Rm and Vcm were parameterized between the Cm 500 fF
values of 100 Ω - 3.2 KΩ and 200 mV – 800 mV respectively. Rm 800 Ω
According to the observations the required gain VDD 1V
characteristics was obtained at 800 Ω. Furthermore, very low
1.5 Optimize SFDR for 1mV peak-to-peak output voltage CMRR is expressed in decibels (dB) as
signal at 10MHz. How good can you get the linearity? 𝐴𝑑
The figure given below shows the spectral response 𝐶𝑀𝑅𝑅 = 20. 𝑙𝑜𝑔10
𝐴𝑐𝑚
of 1 mV output signal.

Fig 8. CMRR plot

5. What is the noise figure of the OTA?
The noise figure (NF) of an OTA quantifies how
Fig 7, Spectral response much the amplifier degrades the signal-to-noise ratio (SNR)
[Link] the architecture and design a solution. How of an input signal. The figure below shows the noise figure.
can you optimize the power consumption?
A two-stage amplifier architecture has been used.
The input is AC coupled and fed into the first stage
comprising of fully differential self-biased inverters. They
are used in self-biasing setup inorder to ensure that they
function at required operating point. At first stage an
amplification of around 40 dB is obtained. Second stage is
composed of fully differential common source amplifier
loaded with PMOS current source. Common Mode Feed- Fig 9. Noise figure plot
Back (CMFB) is used. Power consumption could be 6. How can you reduce the power consumption? What is
reduced by lowering parasitic resistance and capacitances. the lowest power that you can achieve?
2.1 What is the OTA architecture. Why? Power consumption could be lowered by reducing parasitic
An Operational Transconductance Amplifier (OTA) resistance and capacitance. Optimizing the common mode
is a versatile analog building block in electronics. An OTA voltage and miller resistance to their minimal value required
produces a current proportional to the differential input to get output without any noise/ distortions. The least power
voltage compared to a conventional operational amplifier (op- achieved was 15 fW.
amp), which produces a voltage proportional to the input 7. How the performance of your OTA change when you
voltage difference. OTAs can be designed to consume run PVT simulations? Note: PVT - Process, Voltage,
minimal power, as they are typically simpler than op-amps Temperature
and operate efficiently in current mode. OTAs generally 7.1. Process - slow, nominal, fast
require fewer components compared to op-amps, making 7.2. Voltage: Vdd - 10%, Vdd, Vdd + 10%
them ideal for integrated circuit (IC) design. 7.3. Temperature: 30°C, 60°C, 90°C
2.2 What is the CMFB solution. Why?
CMFB senses the common-mode voltage at the
output of a differential amplifier and compares it to a
reference common-mode voltage. The error signal is then
used to adjust the biasing of the amplifier to bring the
common-mode voltage to the desired level. A resistor divider
configuration is opted for sensing common mode. Active
devices require the common-mode voltage to stay within a
specific range to operate in the linear region. Fig 10. PVT analysis
4. What is the CMRR? What determines CMRR? Derive PVT analysis was carried out in fast-fast, fast-slow,
your expectation and validate it via simulations. Optimize nominal-nominal, slow-fast and slow-slow configurations in
for CMRR. temperature ranges of 30°C, 60°C, 90°C. The nominal
The Common-Mode Rejection Ratio (CMRR) is a condition of nominal-nominal and 30°C condition curve has
parameter used to evaluate the ability of a differential been highlighted.
amplifier to reject common-mode signals, identical signals
applied to both inputs while amplifying differential signals,
the difference between two inputs. It is a key performance
metric in applications requiring noise immunity, such as audio
systems, instrumentation, and communication devices.
Fig 11. CMRR testbench Fig 12. ADE XL Window