5SFC0 Advanced CMOS design - Design a current mirror OTA
Guru Prasad Murugan
[email protected] and 2093669
I. INTRODUCTION
Analog circuit design relies heavily on the design and
analysis of current mirror operational transconductance
amplifiers (OTAs), especially for applications that demand
high gain, low power consumption, and accuracy. A current
mirror OTA achieves high input impedance, low output
impedance, and higher linearity by utilizing the concepts of
differential pair operation and current replication. The Fig. 2. Gain value at parameterized gain values
implementation at the transistor level facilitates a thorough
investigation of important design trade-offs, such as stability,
power efficiency, and matching precision. To reduce process
variability and improve the functionality of the existing
mirror structure, strategies such geometric matching,
common centroid layout, and symmetry in device placement
will be used. 45nm technology has been utilized and Fig. 3. Schematic diagram
components from NCSU FreePDK 45 have been used in the
realization of the schematic.
II. LAB DESCRIPTION
Length, width, Miller capacitance and number of fingers
were parameterized. The required gain of 60dB at low
frequency was obtained. The gain curve was obtained by
using the dB20 function. The function is used in frequency
response analysis, plotting the dB20(mag(output voltage))
over a range of frequencies allows visualization of gain/ Fig. 4. Unity gain bandwidth obtained at 500 MHz
attenuation of a circuit as a function of frequency. 1.2. The gain at low frequencies should be more than 60dB;
What do you think will be better a single or two-stage
architecture?
Gain of 60dB has been obtained. A two-stage amplifier is
suited for achieving high gain, as it allows for cascading
multiple stages to amplify the signal. A two-stage amplifier
can also be designed to achieve high bandwidth by careful
selection of components and optimization of the circuit.
1.3. The unity gain bandwidth should be at least 500MHz
Fig. 1. Gain vs Frequency [AC Analysis] Unity gain of 1dB has been obtained at 500MHz by
Parameter Value optimizing the W/L ratio value.
Gain 59.861 dB 2. Synthesize the architecture and design a solution. How can
Length 900 nm you optimize the power consumption? How do you guarantee
Number of fingers 4878 the OTA stability?
Power consumption optimization
Width 1000 nm
• Power consumption could be optimized by scaling
The design has been simulated in such a way that the unity
down transistor widths and lengths to reduce
gain bandwidth is at least 500 MHz. The figure and table
capacitance and power. The W/L ratio has been
below shows the value of gain at 500 MHz at parameterized
chosen in such a way to optimize gm per unit current.
value of number of fingers. Therefore, the number of fingers
is optimized to 4878. • Efficient biasing has been implemented with a
Number of fingers Gain value current reference to minimize quiescent current.
OTA stability
4147 3.74239 mdB
• Feedback technique has been appropriately used to
4976 722.509 mdB
improve stability. The feedback network is designed
in such a way to provide sufficient phase margin.
• Miller compensation of using a compensation
capacitor introduces a dominant pole and pushes
non-dominant poles further out. The compensation
capacitor is also used to achieve the desired phase III. CONCLUSIONS
margin. A current mirror operational transconductance amplifier of
• Components with low parasitic capacitances have given design specifications has been designed, subsequently,
been chosen. AC analysis, Parametric analysis, and Transient analysis were
5. Run transient simulations and investigate: performed to obtain the required gain at low frequency and
5.1. Transient settling for 1V input step signal. What is the unity-gain bandwidth. Entire analysis was implemented in
slew rate? cadence virtuoso tool.
5.2. BONUS: Transient response for 10µV input peak-to-peak
dual-tone signal at center frequency 10MHz and 10kHz tone-
spacing. Show the spectrum. Plot IMD3 vs input frequency.
How can you improve?
Fig. 5. Transient characteristics of 1V step signal
∆𝑉
𝑆𝑙𝑒𝑤 𝑟𝑎𝑡𝑒 =
∆𝑡
209.9211 𝑚𝑉
𝑆𝑙𝑒𝑤 𝑟𝑎𝑡𝑒 =
1.06091 𝑛𝑠
Fig. 7. Input signal of transient response of 10µV pk-pk
signal
Fig. 8. Output signal of transient response of 10µV pk-pk
signal
Fig. 9. Spectrum