5SFC0 Advanced CMOS design - Design a common-source amplifier
Guru Prasad Murugan
[email protected] and 2093669
I. INTRODUCTION
A common source amplifier is an essential component of
analog circuit design and is frequently utilized in filters,
oscillators, and amplifiers, among other uses. 45nm
technology has been utilized and components from NCSU
FreePDK 45 have been used in the realization of the Fig. 4. Input Sine wave
schematic.
II. LAB DESCRIPTION
An amplifier is a circuit that uses an external power source
to produce an output signal that is greater than its input signal.
An amplifier is used in sensor and acoustic applications. Self-
biased inverter could used for realizing an amplifier. Since,
both PMOS and NMOS transistors exhibit voltage gain in
active region. This gain is determined by the transistor's Fig. 5. Amplified output wave
transconductance (gm) and output resistance (Ro). Therefore, Parameter Value
the design involves certain fundamental steps in realization Input signal pk-pk value 19.8107 mV
which are as follows. Output signal pk-pk value 564.4651 mV
Input voltage (Vin), length, width and number of fingers are
parameterized. The required gain of 30dB is obtained and the
output voltage Vout at the instant is measured.
Fig. 6. IDS (Drain-source current) vs Vov (overdrive voltage) plot
2.1 What is the load used? Why?
A capacitive load of 100f F has been used according to
Fig. 1. Gain (Ao) vs Vin
the required design. Capacitors are frequently employed to
Parameter Value
let AC signals through while blocking DC components. To
Gain 30 dB
isolate DC offsets and avoid undesired interactions between
Vbias 330 mV stages, this is essential in many audio and signal processing
Length 4 µm applications.
Number of fingers 120 2.2 How do you bias the circuit?
Width 1.1 µm Transfer characteristics of an inverter show that both
3dB frequency that needs to be achieved is 10M Hz the NMOS and PMOS has to be in saturation mode. Therefore,
design helps us to achieve the mentioned 3dB cut-off biasing is done in such a way that both transistors are in
frequency. saturation mode (VDS>VGS-VTH). Moreover, self-biasing has
been implemented, the feedback between the PMOS and
NMOS transistors helps stabilize the circuit's biasing,
ensuring that the inverter operates correctly.
Fig. 2. 3dB cut-off frequency
Fig. 7. Step response signal
5.1 The settling time of the 1V step signal is 58.08231 ms.
Fig. 3. Schematic diagram
5.2 Transient response for 10mV pk-pk sine-wave
Fig. 8. 10mV pk-pk input sine-wave Fig. 12. AC Response with noise
𝐻12
𝑆𝐻𝐷𝑅 = √
𝐻22 + 𝐻32 + 𝑃𝑛𝑜𝑖𝑠𝑒
𝑆𝐻𝐷𝑅 = 0.0199
III. CONCLUSIONS
Fig. 9. 10mV pk-pk sine-wave output
A common source amplifier of given design specifications
has been designed, subsequently, DC analysis, AC analysis,
Parametric analysis, and Transient analysis were performed
to obtain the transfer characteristics, fix the operating point,
and achieve the required gain, 3dB cut-off frequency, and
amplification. The required transconductance (g m), has also
been obtained and displayed by enabling transient operation
points in the schematic The circuit has been optimized to
reduce distortions. Entire analysis was implemented in
cadence virtuoso tool.
Fig. 10. Spectral analysis to find SDR
Parameter Value
H1 -6.0397 dB
H2 -11.3057 dB
H3 -41.2066 dB
𝐻1
𝐻𝐷2 =
𝐻2
−6.0397
𝐻𝐷2 =
−11.3057
𝐻𝐷2 = 0.5342
𝐻1
𝐻𝐷3 =
𝐻3
−6.0397
𝐻𝐷3 =
−41.2066
𝐻𝐷3 = 0.1465
𝐻12
𝑆𝐷𝑅 = √
𝐻22
+ 𝐻32
𝑆𝐷𝑅 = 0.0199
Fig. 11. AC Response
