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Event Queue

The document discusses Verilog scheduling and event queues, highlighting the concepts of events, event queues, time slots, and scheduling mechanisms. It explains the difference between active and inactive regions within time slots and details various types of events such as evaluation and update events. Additionally, it covers the implications of non-blocking assignments and sensitivity lists in the context of event scheduling.

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Abhishek Agrawal
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0% found this document useful (0 votes)
8 views28 pages

Event Queue

The document discusses Verilog scheduling and event queues, highlighting the concepts of events, event queues, time slots, and scheduling mechanisms. It explains the difference between active and inactive regions within time slots and details various types of events such as evaluation and update events. Additionally, it covers the implications of non-blocking assignments and sensitivity lists in the context of event scheduling.

Uploaded by

Abhishek Agrawal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Introduction  Motivating Example

Verilog Scheduling and Event Queue

Consider

always_ff @( posedge clk ) c = reset ? 0 : c + 1;


always_ff @( posedge clk ) over_th = c + 1’d1 > threshold;

Is over th computed using the new or old c?

(Answer: either one, and so code is unreliable.)

eq-1 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-1
Introduction  Terminology

Terminology

Event:
Sort of a to-do item for simulator. May include running a bit of Verilog code or updating an object’s value.

Event Queue:
Sort of a to-do list for simulator. It is divided into time slots and time slot regions.

Time Slot:
A section of the event queue in which all events have the same time stamp.

Time Slot Region:


A subdivision of a time slot. There are many of these. Important ones: active, inactive, NBA.

Scheduling:
Determining when an event should execute. The when consists of a time slot and a time slot region.

Update Events:
The changing of an object’s value. Will cause *sensitive* objects to be scheduled.

eq-2 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-2
Introduction  Terminology

Time slot t=0 (1) Start this


time slot.
Time Slot Regions
(4) When active Active Execute START
Rationale: region empty, Event
bulk move
Event 9 (2) Execute an
events.
“Do it now!” is too vague. Need to prioritize. active event.
Event 1
SCHED DONE
SystemVerilog divides a time slot into 17 regions.
Inactive
(5) When all regions
Some Regions Event 2 in this time slot empty
advance to next time slot.

Active Region: (3a) Schedule new


events this time slot.
Events that the simulator is currently working on. Only the current Time slot t=7
time slot has this region. (3b) Schedule new
Inactive events in future
time slots.
Inactive Region: Event 12

Contains normally scheduled events. Current and future time slots


have this region.
Time slot t=120
Inactive

Event 103

eq-3 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-3
Introduction  Terminology

Time slot t=0 (1) Start this


time slot.

(4) When active Active Execute START


region empty, Event
bulk move
Event 9 (2) Execute an
events.
active event.
Event 1
SCHED DONE

Inactive
(5) When all regions
Event 2 in this time slot empty
advance to next time slot.

(3a) Schedule new


events this time slot.
Time slot t=7
(3b) Schedule new
Inactive events in future
time slots.
Event 12

Time slot t=120


Inactive

Event 103

eq-4 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-4
Example Showing Active and Inactive Regions

Event Queue Example


initial begin
Step 1 2 Step 3 4 Step 5 6 Step 7 8 Step 9 10 Step 11 12 Step 13
→ t=0 → → t=0 → → t=0 → t=1 // i-a.0
t=0 t=0 t=0
Active Active Active Active Active Active Inactive a = 1;
Inactive % % Inactive % Inactive #3;
i-a.0 i-b.0 c i-b.1
i-a.0 i-b.0 Inactive c Inactive t=1 t=3 // i-a.1
i-b.0 Inactive c t=1 t=1 Inactive Inactive a = 2;
t=3 Inactive Inactive i-b.1 i-a.1 end
Inactive i-b.1 i-b.1 t=3
i-a.1 t=3 t=3 Inactive
Inactive Inactive i-a.1 initial begin
i-a.1 i-a.1 // i-b.0
b = 10;
1: Verilog puts all initial blocks in t = 0’s inactive region.
#1;
2: Active region is empty, and so inactive copied to active. // i-b.1
b = a;
3: Event i-a.0 executes and schedules event c for t = 0 . . . end
. . . and i-a.1 for t = 3.

4: Event i-a.0 removed from active region (it is now not scheduled anywhere). assign c = a + b; // c

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Example Showing Active and Inactive Regions

Event Queue Example


initial begin
Step 1 2 Step 3 4 Step 5 6 Step 7 8 Step 9 10 Step 11 12 Step 13
→ t=0 → → t=0 → → t=0 → t=1 // i-a.0
t=0 t=0 t=0
Active Active Active Active Active Active Inactive a = 1;
Inactive % % Inactive % Inactive #3;
i-a.0 i-b.0 c i-b.1
i-a.0 i-b.0 Inactive c Inactive t=1 t=3 // i-a.1
i-b.0 Inactive c t=1 t=1 Inactive Inactive a = 2;
t=3 Inactive Inactive i-b.1 i-a.1 end
Inactive i-b.1 i-b.1 t=3
i-a.1 t=3 t=3 Inactive
Inactive Inactive i-a.1 initial begin
i-a.1 i-a.1 // i-b.0
b = 10;
5,6: Event i-b.0 executes and schedules i-b.1 for t = 1.
#1;
7,8: Since active region is empty, inactive region is bulk-copied to active region. // i-b.1
b = a;
9: Event c executes. end

10-12: Since all regions in time slot 0 are empty, move to next time slot, t = 1.
assign c = a + b; // c

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Example Showing Active and Inactive Regions  NBA and Postponed Regions

Some More Regions

NBA Region:
Update events from non-blocking assignments.

Postponed Region:
Events scheduled using $watch system task.

eq-7 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-7
Event Scheduling  Event Types

Event Types

Evaluation Event
Indicates that a piece of code is to be executed or resumed.
Sometimes just referred to as events, or resume events.

All events from the previous event queue example were evaluation events.

Update Event
Indicates that the value of an object is to be changed.

Update events are created by executing non-blocking assignments.

eq-8 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-8
Event Scheduling  Event Scheduling

Event Scheduling

Event Scheduling:
The placing of an event in the event queue.

Types of Scheduling

Initially Scheduled Events


Events scheduled when simulation starts, such as for initial blocks.

Time-Delay Scheduled Events


Events scheduled when execution reaches a time delay.

Sensitivity-List Scheduled Events


Events scheduled when certain object values change.

Non-Blocking Assignment (NBA) Scheduled Update Events


Update events scheduled when a non-blocking assignment is reached.

eq-9 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-9
Event Scheduling  Types of Scheduling and Related Events  Time-Delay Scheduled

Event Scheduling

Time-Delay Scheduled

When a delay control, e.g. #12, is encountered. . .


. . . schedule (put) a resume event in inactive region . . .
. . . of future (t+delay) time step.

Time-Delay Scheduled Example:

b++;
// Label L1
#4; // Schedule resume event for L2 at time t+4.
// Label L2;
a = b;

eq-10 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-10
Event Scheduling  Types of Scheduling and Related Events  Sensitivity List Scheduled

Sensitivity List Scheduled

When an object in a sensitivity list changes . . .


. . . schedule a resume or check-and-resume event for code associated with sensitivity list . . .
. . . in the inactive region of current time step.

Explicit Event Examples:

// Label: L0
@( x ); // Put a check-@-condition event in sensitivity list of x ..
// .. event will resume at L1 if condition satisfied ..
// .. meaning any change in x.
// Label: L1
@( posedge clk ); // Put a check-@-condition event in sensitivity list of clk ..
// .. event will resume at L2 if condition satisfied ..
// .. meaning 0->1 transition.
// Label: L2
wait( stop_raining ); // Put a check-wait-condition event in sensitivity list of stop_raining ..
// .. event wil resume at L3 if stop_raining != 0.
// Label: L3

eq-11 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-11
Event Scheduling  Types of Scheduling and Related Events  Sensitivity List Scheduled

Live-In of always comb or always @*:

always_comb x = a + b; // Put an execute event in sensitivity list of a and b.

always_comb begin // Put an execute event in sensitivity list of ..


y = d + e; // d, e, and f, BUT NOT y. (y is not live in).
z = y + f;
end

Continuous assignment:

assign x = a + b; // Put an execute event in sensitivity list of a and b.

eq-12 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-12
Event Scheduling  Types of Scheduling and Related Events  Sensitivity List Scheduled

Primitive ports:

and myAndGate(x,e,f); // Put an execute event in sensitivity list of e and f.

eq-13 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-13
Event Scheduling  Types of Scheduling and Related Events  Permanently Schedule

NBA Scheduled Update Events

When a non-blocking assignment is executed . . .


. . . the value of the right-hand-side is computed . . .
. . . and an update event is scheduled in the NBA region of the current time step . . .
. . . when the update event executes the left-hand-side variable is updated with the value.
always_comb begin
y <= a + b; // Schedule an update-y event in NBA region, keep executing.
e = y + g; // Uses old y.
end

Permanently Scheduled

When a $watch(OBJ) system task is executed . . .


. . . a watch event is scheduled in the postponed region of every time step . . .
. . . when the watch event executes the value of OBJ is printed on the console.

eq-14 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-14
Examples  Example 1  Verilog Code

Example: Non-blocking assignments

Show the state of the event queue for the module below . . .
. . . starting at t = 10 and given the external events described below.

module misc #( int n = 8 )


( output logic [n-1:0] a, g, e,
input uwire [n-1:0] b, c, j, f, input uwire clk );

logic [n-1:0] z;

always_ff @( posedge clk ) begin // Label: alf


a <= b + c;
z = a + j;
g = z;
end

always_comb // Label: alc


e = a * f;
endmodule

eq-15 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-15
Examples  Example 1  Example’s Sensitivity Lists and Update Events

Example’s Sensitivity Lists and Update Events


module misc #( int n = 8 )
( output logic [n-1:0] a, g, e,
Sensitivity List For Example Code
input uwire [n-1:0] b, c, j, f, input uwire clk );
clk: Due to @(posedge clk). If 0 → 1 schedule alf.
logic [n-1:0] z;
a: Due to always comb. Any change, schedule alc.
always_ff @( posedge clk ) begin // Label: alf
a <= b + c;
f: Due to always comb. Any change, schedule alc.
z = a + j;
g = z;
Update Events For Example Code end

Execution of a <= a + c . . . always_comb // Label: alc


e = a * f;
. . . will result in scheduling an update event (for a).
endmodule

eq-16 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-16
Examples  Example 1  Conditions and External Events

Conditions and External Events


module misc #( int n = 8 )
( output logic [n-1:0] a, g, e,
Example Problem Assumptions:
input uwire [n-1:0] b, c, j, f, input uwire clk );
Queue is initially empty at t = 10.
logic [n-1:0] z;
At t = 10 j changes.
always_ff @( posedge clk ) begin // Label: alf
a <= b + c;
At t = 12 clk changes from 0 to 1.
z = a + j;
g = z;
At t = 14 f changes.
end

always_comb // Label: alc


e = a * f;
endmodule

eq-17 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-17
Examples  Example 1  Event Queue Changes

Event Queue Changes


module misc #( int n = 8 )
( output logic [n-1:0] a, g, e,
Step 1: Queue is empty.
input uwire [n-1:0] b, c, j, f, input uwire clk );
Step 2: At t = 10 j changes.
logic [n-1:0] z;
Step 3: No change, because j is not in a sensitivity list.
always_ff @( posedge clk ) begin // Label: alf
a <= b + c;
Step 1 2 Step 3 z = a + j;
t = 10 → t = 10 g = z;
Active Active end
Inactive Inactive
NBA NBA always_comb // Label: alc
e = a * f;
endmodule

eq-18 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-18
Examples  Example 1  Event Queue Changes

Event Queue Changes


module misc #( int n = 8 )
( output logic [n-1:0] a, g, e,
Step 5: At t = 12 clk changes from 0 to 1 . . .
input uwire [n-1:0] b, c, j, f, input uwire clk );
. . . scheduling alf in inactive region in Step 6.
logic [n-1:0] z;
Step 7: Since active region empty . . .
. . . inactive copied to active. always_ff @( posedge clk ) begin // Label: alf
a <= b + c;
Step 8: alf starts execution. z = a + j;
g = z;
Step 10: Execution of a<=a+b . . . end
. . . results in scheduling Upd-a in NBA region.
always_comb // Label: alc
e = a * f;
endmodule

Step 4 5 Step 6 7 Step 8 9 Step 10 11 Step 12 13 Step 14 15 Step 16 17 Step 18 19 Step 20


t = 12 → t = 12 → t = 12 → t = 12 → t = 12 → t = 12 → t = 12 → t = 12 → t = 12
Active Active Active Active Active Active Active Active Active
Inactive Inactive alf% alf% Inactive Upd-a% Inactive alc% Inactive
NBA alf Inactive Inactive NBA Inactive alc Inactive NBA
NBA NBA NBA Upd-a NBA NBA NBA
Upd-a

eq-19 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-19
Examples  Example 1  Event Queue Changes

Event Queue Changes


module misc #( int n = 8 )
( output logic [n-1:0] a, g, e,
Step 11: alf finishes leaving active region empty.
input uwire [n-1:0] b, c, j, f, input uwire clk );
Step 13: Next non-empty region, NBA, copied to active region.
logic [n-1:0] z;
Step 14-16: Upd-a causes alc to be scheduled.
always_ff @( posedge clk ) begin // Label: alf
a <= b + c;
Step 17-20: alc moved to active region, runs, finishes.
z = a + j;
g = z;
end

always_comb // Label: alc


e = a * f;
endmodule

Step 4 5 Step 6 7 Step 8 9 Step 10 11 Step 12 13 Step 14 15 Step 16 17 Step 18 19 Step 20


t = 12 → t = 12 → t = 12 → t = 12 → t = 12 → t = 12 → t = 12 → t = 12 → t = 12
Active Active Active Active Active Active Active Active Active
Inactive Inactive alf% alf% Inactive Upd-a% Inactive alc% Inactive
NBA alf Inactive Inactive NBA Inactive alc Inactive NBA
NBA NBA NBA Upd-a NBA NBA NBA
Upd-a

eq-20 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-20
Examples  Example 1  Event Queue Changes

Event Queue Changes


module misc #( int n = 8 )
( output logic [n-1:0] a, g, e,
Step 22: f changes, scheduling alc.
input uwire [n-1:0] b, c, j, f, input uwire clk );
Step 23-26: alc moved to active region, executes finishes.
logic [n-1:0] z;
Step 27: If nothing else happens simulation ends.
always_ff @( posedge clk ) begin // Label: alf
Step 21 22 Step 23 24 Step 25 26 Step 27 a <= b + c;
t = 14 → t = 14 → t = 14 → t = 14 z = a + j;
Active Active Active Active g = z;
Inactive Inactive Inactive end
alc
NBA alc Inactive NBA
NBA NBA always_comb // Label: alc
e = a * f;
endmodule

eq-21 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-21
Examples  Example: Non-blocking assignments 2  Verilog Code

module eq;
Example: Non-Blocking Assignments 2 logic [7:0] a, b, c, d, x, y;
logic [7:0] x1, x2, y1, y2, z2;
Consider the code to the right.
always_comb begin // C1
x1 = a + b;
y1 = 2 * b;
end

assign x2 = 100 + a + b; // C2
assign y2 = 4 * b; // C3
assign z2 = y2 + 1; // C4

initial begin
// C5a
a = 0;
b = 10;
#2;
// C5b
a = 1;
b <= 11;
#2;
// C5c
a = 2;
b = 12;
end
endmodule
eq-22 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-22
Examples  Example: Non-blocking assignments 2  Verilog Code

module eq;
Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Step 8 Step 9 logic [7:0] a, b, c, d, x, y;
t=0 t=0 t=0 t=0 t=0 t=0 t=0 t=0 t=2 logic [7:0] x1, x2, y1, y2, z2;
Active Active Active Active Active Active Active Active Active
C5a% C1% C2% C3% C4% C5b%
always_comb begin // C1
x1 = a + b;
Inactive Inactive C2 C3 Inactive Inactive Inactive Inactive Inactive y1 = 2 * b;
C1 C3 Inactive C4 end
NBA C2 Inactive NBA NBA NBA NBA NBA
C3 NBA assign x2 = 100 + a + b; // C2
NBA NBA t=2 t=2 t=2 t=2 assign y2 = 4 * b; // C3
Inactive Inactive Inactive Inactive assign z2 = y2 + 1; // C4
t=2
t=2 t=2 Inactive C5b C5b C5b C5b
initial begin
Inactive Inactive C5b // C5a
C5b C5b a = 0;
b = 10;
#2;
// C5b
a = 1;
b <= 11;
#2;
// C5c
a = 2;
b = 12;
end
endmodule
eq-23 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-23
Examples  Example: Non-blocking assignments 2  Verilog Code

module eq;
logic [7:0] a, b, c, d, x, y;
Step 10 Step 11 Step 12 Step 13 Step 14 Step 15 Step 16 Step 17
logic [7:0] x1, x2, y1, y2, z2;
t=2 t=2 t=2 t=2 t=2 t=2 t=2 t=2
Active Active Active Active Active Active Active Active always_comb begin // C1
C1% C2% b← 11% C1% C2% x1 = a + b;
Inactive C2 Inactive Inactive Inactive Inactive C2 C3 y1 = 2 * b;
C1 Inactive C1 Inactive end
C3
C2 NBA NBA NBA C2 Inactive assign x2 = 100 + a + b; // C2
NBA NBA b← 11 b← 11 C3 NBA assign y2 = 4 * b; // C3
b← 11 b← 11 t=4 t=4 t=4 NBA NBA assign z2 = y2 + 1; // C4
t=4 t=4 Inactive Inactive Inactive t=4
Inactive Inactive C5c C5c C5c t=4 t=4 Inactive initial begin
C5c C5c Inactive Inactive C5c // C5a
a = 0;
C5c C5c
b = 10;
#2;
// C5b
a = 1;
b <= 11;
#2;
// C5c
a = 2;
b = 12;
end
endmodule
eq-24 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-24
Examples  Example: Non-blocking assignments 2  Verilog Code

module eq;
Step 18 Step 19 Step 20 Step 21 Step 22 logic [7:0] a, b, c, d, x, y;
t=2 t=2 t=2 t=2 t=4 logic [7:0] x1, x2, y1, y2, z2;
Active Active Active Active Active
C3% C4% C5c%
always_comb begin // C1
x1 = a + b;
Inactive Inactive Inactive Inactive Inactive y1 = 2 * b;
C4 end
NBA NBA NBA NBA NBA
assign x2 = 100 + a + b; // C2
t=4 t=4 t=4 t=4 assign y2 = 4 * b; // C3
Inactive Inactive Inactive Inactive assign z2 = y2 + 1; // C4
C5c C5c C5c C5c
initial begin
// C5a
a = 0;
b = 10;
#2;
// C5b
a = 1;
b <= 11;
#2;
// C5c
a = 2;
b = 12;
end
endmodule
eq-25 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-25
Event Queue Diagrams

Time slot t=7 (1) Start this time slot.


(4) When active region empty,
bulk move events
Active Execute START
from first
non-empty Event 9
(2) Execute an
region. Event 1 active event.

SCHED DONE

(3a) (5) When all


Schedule Inactive
regions in this
new events Event 2
time slot
in this empty advance
time slot. to next
NBA
Event 12 time slot.
(3b)
Schedule
new events
in future
time slots. Time slot t=9
Inactive
Event 72

NBA
Event 162

Time slot t=12

eq-26 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-26
Event Queue Diagrams

Time slot t=7 (1) Start this time slot.

Active Execute START


Event 9
(2) Execute an
Event 1 active event.

SCHED DONE

Inactive
Event 2 Inactive
and NBA
regions
NBA
are empty.
Event 12

Postponed Execute START


Watch Event 9
Watch Event 1 (2) Execute a
postponed event.
Schedule new DONE
events in future
time slots.
Time slot t=19 Initiate next time slot.

eq-27 EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-27
Event Queue Diagrams

Time slot t=7 (1) Start this time slot.

Active Execute START


Event 9
(2) Execute an
Event 1 active event.

SCHED DONE

Inactive Re-inactive
Event 2 and re-NBA
Inactive
empty BUT
and NBA
events in
regions
NBA inactive or
are empty.
Event 12 NBA region.

Reactive Execute START


Event 79
(2) Execute a
Event 81 reactive event.

SCHED DONE

Re-Inactive
Event 712 Inactive,
re-inactive,
NBA, and
Re-NBA re-NBA regions
Event 122 are all empty.

Postponed Execute START


Watch Event 9
Watch Event 1 (2) Execute a
postponed event.
Schedule new DONE
events in future
time slots.

eq-28 Time slot t=19 Initiate next time slot. EE 4755 Lecture Transparency. Formatted 17:46, 11 December 2019 from lsli-event-q-TeXize. eq-28

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