Learn Verilog !

1. Introduction

 What is Verilog?

 Introduction to Verilog

 ASIC Design Flow

 Design Abstraction Layers

Examples

 Verilog Examples

2. Data Types

 Verilog Syntax

 Verilog Data types

 Verilog Scalar/Vector

 Verilog Arrays

 Verilog Net Types

 Verilog Strength

3. Building Blocks

 Verilog Module

 Verilog Port

 Verilog Module Instantiations

 Verilog assign statements

 Verilog assign examples

 Verilog Operators

 Verilog Concatenation

 Verilog always block

 Combo Logic with always

 Sequential Logic with always

 Verilog initial block

 Verilog generate

 Verilog Quick Review

4. Behavioral Modeling

 Verilog Block Statements

 Verilog Assignment Types

 Verilog Blocking/Non-blocking

 Verilog Control Flow

 Verilog for Loop

 Verilog case Statement

 Verilog Conditional Statements

 Verilog if-else-if

 Verilog Functions

 Verilog Tasks

 Verilog Parameters

 Verilog Delay Control

 Verilog Inter/Intra Delay

 Verilog Hierarchical Reference

5. Gate/Switch Modeling

 Gate Level Modeling

 Gate Level Examples

 Gate Delays

 Switch Level Modeling

 User-Defined Primitives

6. RTL Simulation

 Verilog Simulation Basics

 Verilog Testbench

 Verilog Timescale

 Verilog Scheduling Regions

 Verilog Clock Generator

7. Gate Level Simulation

 Gate Level Simulations

 Verilog Timing Checks

 Verilog Specify Block

 Standard Delay Format (SDF)

 Verilog sdf_annotate

8. Synthesis

 Verilog Synthesis

 Verilog Coding Style Effect

9. Verilog Macros

 Verilog Compiler Directives

 Verilog Macros

 Verilog `ifdef `elsif

10. System Tasks and Functions

 Verilog $random

 Verilog $stop and $finish

 Verilog Display tasks

 Verilog Math Functions

 Verilog Conversion Functions

 Verilog Timeformat

 Verilog Timescale Scope

 Verilog File Operations

 Verilog Command Line Input

11. Miscellaneous

 Verilog Namespace

 Value Change Dump (VCD)

 Verilog VCD Dump

Verilog Net Types

1. Net Types
2. Wire and tri nets
3. Wired Nets
4. trireg Net
5. tri0 and tri1 Nets
6. Unresolved Nets
7. Supply Nets

Net Types

In Verilog, net types are used to model physical connections

between components in digital circuits. They do not store values,
its value is determined by the values of its drivers and the default
value of a net is typically 'z' (high impedance) when left
unconnected.

Net
Description
Type

wire Connects elements with continuous assignment

tri Connects elements with multiple drivers

wor Creates wired OR configurations

wand Creates wired AND configurations

trior Creates wired OR configurations with multiple drivers

triand Creates wired AND configurations with multiple drivers

tri0 Models nets with resistive pulldown devices

 tri1 Models nets with resistive pullup devices

trireg Stores a value and is used to model charge storage nodes

Models nets that can should be driven only by a single

uwire
driver

supply0 Models power supply with a low level of strength

supply1 Models power supply with a high level of strength

Wire and tri nets

Wire and tri are two types of nets in Verilog that serve as
connections between elements in a digital circuit model. While
they are functionally identical and share the same syntax, they
are given different names to help designers convey the intended
purpose of the net within the model.

Wire nets:

Typically used for connections driven by a single source

Ideal for representing nets controlled by one gate or one
continuous assignment
The name "wire" suggests a simple, unidirectional connection

Tri (short for tristate) nets:

Commonly used for nets that may have multiple drivers

Suitable for modeling buses or other shared connections
where different components might drive the net at different
times
The name tri implies the possibility of multiple drivers and
the potential use of high-impedance states

When multiple drivers of the same strength drive conflicting

values on a wire or tri net in Verilog, the result is indeed an
unknown (x) value.
Wired Nets

Wired nets are of type wor , wand , trior and triand and
are used to model wired logic configurations.

The wor and trior nets are designed to implement wired OR

configurations, ensuring that the net's value becomes 1 whenever
any of the drivers outputs a 1.
The wand and triand nets are designed to implement wired
AND configurations, ensuring that the net's value becomes 0
whenever any of the drivers outputs a 0.

The simulation shown below illustrates how these net types are
different compared to a normal wire when there are multiple
drivers on the same net.
 1 module tb;
2 wor wor_net;
3 wand wand_net;
4 trior trior_net;
5 triand triand_net;
6
7 wire normal_net;
8
9 reg driver_1;
10 reg driver_2;
11 reg [3:0] values;
12
13 assign wor_net = driver_1;
14 assign wor_net = driver_2;
15
16 assign trior_net = driver_1;
17 assign trior_net = driver_2;
18
19 assign wand_net = driver_1;
20 assign wand_net = driver_2;
21
22 assign triand_net = driver_1;
23 assign triand_net = driver_2;
24
25 assign normal_net = driver_1;
26 assign normal_net = driver_2;
27
28 initial
29 $monitor("[%0t] driver_1=%0b driver_2=%0b nor
30
31 initial begin
32 values = {1'bZ, 1'bX, 1'b1, 1'b0};
33
34 for (integer i = 0; i < 4; i+=1) begin
35 for (integer j = 0; j < 4; j+=1) begin
36
37 driver_1 = values[i];
38 driver_2 = values[j];
39 #10;
40 end
41 end
42 end
43
44 endmodule

Observe that a standard net resulted in an X value, while the

other net types displayed either 0 or 1.

 Simulation Log
 xcelium> run
[0] driver_1=0 driver_2=0 normal=0 wor=0 wand=0
[10] driver_1=0 driver_2=1 normal=x wor=1 wand=
[20] driver_1=0 driver_2=x normal=x wor=x wand=
[30] driver_1=0 driver_2=z normal=0 wor=0 wand=
[40] driver_1=1 driver_2=0 normal=x wor=1 wand=
[50] driver_1=1 driver_2=1 normal=1 wor=1 wand=
[60] driver_1=1 driver_2=x normal=x wor=1 wand=
[70] driver_1=1 driver_2=z normal=1 wor=1 wand=
[80] driver_1=x driver_2=0 normal=x wor=x wand=
[90] driver_1=x driver_2=1 normal=x wor=1 wand=
[100] driver_1=x driver_2=x normal=x wor=x wand
[110] driver_1=x driver_2=z normal=x wor=x wand
[120] driver_1=z driver_2=0 normal=0 wor=0 wand
[130] driver_1=z driver_2=1 normal=1 wor=1 wand
[140] driver_1=z driver_2=x normal=x wor=x wand
[150] driver_1=z driver_2=z normal=z wor=z wand
xmsim: *W,RNQUIE: Simulation is complete.

trireg Net

The trireg net in Verilog is a special type of net that is used to

model charge storage nodes. Unlike standard nets that do not
store values, a trireg net can hold its last driven value when
no drivers are active. This makes it suitable for modeling storage
elements like capacitors.

A trireg net can be in one of two states:

Driven State: When at least one driver outputs a value (either

0, 1, or x), the trireg net takes on that value.
Capacitive State: When all drivers are in a high-impedance
state (z), the trireg retains its last driven value.

The strength of the value held by a trireg net in the capacitive

state can be specified as small , medium , or medium . This
strength is determined at the time of declaration.
tri0 and tri1 Nets

tri0 and tri1 are specialized net types used to model nets
with specific pull strengths.

The tri0 net is equivalent to a wire net that has a continuous

resistive pulldown device connected to it. When no driver is
connected to a tri0 net, its value is 0, reflecting the continuous
pull-down effect. If any driver outputs a 1, the value of the tri0
net will be 1, but if all drivers are inactive or in high-impedance
state (z), it will hold at 0.

The tri1 net is similar to a wire net but includes a continuous

resistive pullup device. When no driver is connected to a tri1 net,
its value is 1 due to the pull-up effect. If any driver outputs a 0,
the value of the tri1 net will change to 0, but if all drivers are
inactive or in high-impedance state (z), it will remain at 1.

The simulation shown below illustrates how these net types are
different compared to a normal wire when there are multiple
drivers on the same net.
1 module tb;
2 tri0 tri0_net;
3 tri1 tri1_net;
4
5 wire normal_net;
6
7 reg driver_1;
8 reg driver_2;
9 reg [3:0] values;
10
11 assign tri0_net = driver_1;
12 assign tri0_net = driver_2;
13
14 assign tri1_net = driver_1;
15 assign tri1_net = driver_2;
16
17 assign normal_net = driver_1;
18 assign normal_net = driver_2;
19
20 initial
21 $monitor("[%0t] driver_1=%0b driver_2=%0b nor
22
23 initial begin
24 values = {1'bZ, 1'bX, 1'b1, 1'b0};
25
26 for (integer i = 0; i < 4; i+=1) begin
27 for (integer j = 0; j < 4; j+=1) begin
28
29 driver_1 = values[i];
30 driver_2 = values[j];
31 #10;
32 end
33 end
34 end
35 endmodule

 Simulation Log
 xcelium> run
[0] driver_1=0 driver_2=0 normal=0 tri0=0 tri1=
[10] driver_1=0 driver_2=1 normal=x tri0=x tri1
[20] driver_1=0 driver_2=x normal=x tri0=x tri1
[30] driver_1=0 driver_2=z normal=0 tri0=0 tri1
[40] driver_1=1 driver_2=0 normal=x tri0=x tri1
[50] driver_1=1 driver_2=1 normal=1 tri0=1 tri1
[60] driver_1=1 driver_2=x normal=x tri0=x tri1
[70] driver_1=1 driver_2=z normal=1 tri0=1 tri1
[80] driver_1=x driver_2=0 normal=x tri0=x tri1
[90] driver_1=x driver_2=1 normal=x tri0=x tri1
[100] driver_1=x driver_2=x normal=x tri0=x tri
[110] driver_1=x driver_2=z normal=x tri0=x tri
[120] driver_1=z driver_2=0 normal=0 tri0=0 tri
[130] driver_1=z driver_2=1 normal=1 tri0=1 tri
[140] driver_1=z driver_2=x normal=x tri0=x tri
[150] driver_1=z driver_2=z normal=z tri0=0 tri
xmsim: *W,RNQUIE: Simulation is complete.

Unresolved Nets

A uwire net is an unresolved or unidriver wire used to model

nets that allow only a single driver. If more than one driver
attempts to drive a uwire, it results in a compile-time error. This
restriction helps prevent contention and ambiguity in signal
assignment.

Supply Nets

The supply0 and supply1 nets can be used to model the

power supplies in a circuit. These nets shall have supply strengths.

Interview Questions
 Verilog Interview Set 1

 Verilog Interview Set 2

 Verilog Interview Set 3

 Verilog Interview Set 4

 Verilog Interview Set 5

 Verilog Interview Set 6

 Verilog Interview Set 7

 Verilog Interview Set 8

 Verilog Interview Set 9

 Verilog Interview Set 10

 Verilog Interview Set 11

 Verilog Interview Set 12

 Verilog Interview Set 13

 Verilog Interview Set 14

 Verilog Interview Set 15

Related Topics

 Digital Fundamentals

 Verilog Tutorial

 Verification

 SystemVerilog Tutorial

 UVM Tutorial

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SystemVerilog Interview Questions Set 10

SystemVerilog Interview Questions Set 9

SystemVerilog Interview Questions Set 8

SystemVerilog Interview Questions Set 7

Latest in UVM

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UVM Root [uvm_root]

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