CH A PTE R

ARM PROCESSOR 2
FUNDAMENTALS

ARMprocessor. In this chapter we will focus

Chapter l covered embedded systems with an
an overview of the processor core and
on the actual processor itself. First, we will provide describe the programmer's
describe how data moves between its different parts. We will
which will show you the
model from asoftware developer's view of the ARM processor, also take a look at
interact. We will
functions of the processor core and how different parts
speed up and organize
the core extensions that form an ARM processor. Core extensions cover the revisions to the
instruction set. We will then
main memory as well as extend the
conventions used to identify
ARM core architecture by describing the ARM core naming
The final
them and the chronological changes to the ARM instruction set architecture.
specific
section introduces the architecture implementations by subdividing them into
ARM processor core families.
data buses,
A programmer can think of an ARM core as functional units connected by
as shown in Figure 2.1,where, the arrows represent the flow of data, the lines represent the
buses, and the boxes represent either an operation unit or a storage area. The figure shows
not only the flow of data but also the abstract components that make up an ARM core.
Data enters the processor core through the Data bus. The data may be an instruction to
execute or a data item. Figure 2.1 shows a Von Neumann implementation of the ARM
data items and instructions share the same bus. In contrast, Harvard implementations of
the ARM use two different buses.
The instruction decoder translates instructions before they are executed. Each
instruction executed belongs to a particular instruction set.
The ARM processor, like all RISC processors, uses a load-store architecture. This
means it has two instruction types for transferring data in and out of the processor: load
instructions copy data from memory to registers in the core, and conversely the store
19
20 Chapter
2 ARM( Processor Fundamentals

Data
Instruction
decoder
Sign extend
Write Read

rl5 Rd
Register file
10-r15 Result
pc
RnA Rn B
ABAcc
Barrel shilter
MAC

ALU

Address register
Incrementer

Address

Figure 2.1 ARM Core dataflow model.

instructions copy data from registers to memory. There are no data processing instructions
that directly manipulate data in memory. Thus, data processing is carried out solely in
registers.
Data items are placed in the register file-a storage bank made up of 32-bit registers.
Since the ARM core is a 32-bit processor, most instructions treat the registers as holding
signed or unsigned 32-bit values. The sign extend hardware converts signed 8-bit and 16-bit
numbers to 32-bit values as they are read from memory and placed in aregister.
ARM instructions typically have two source registers, Rn and Rm, anda single result or
destination register, Rd. Source operands are read from the register file using the internal
buses Aand B, respectively.
The ALU (arithmetic logic unit) or MACc (multiply-accumulate unit) takes the regis
ter values Rn and Rm from the Aand Bbuses and computes a result. Data processing
instructions write the result in Rd directly to the register file. Load and store instructions
use the ALU to generate an address to be held in the address register and broadcast on the
Address bus.
 2.1 Registers 2l

One important feature of the ARM is that register Rm alternatively can be preprocessed
in the barel shifter before it enters the addresses.
ALU. Together the barrel shifter and ALU Can
calculate a wide range of expressions and reista.
After passing through the functional units, the result in Rdis written back to the acdree
fle using the Result bus. For load and store instructions the incrementer updates the
rerister beforethe core reads or writes the next register value from or to the next sequential
until an exception er
memory location. The processor continues executing instructions
flow.
interrupt changes the normal execution take a more detailed look
Now that you have an overview of the processor core we'll current program status
the registers, the
at some of the key components of the processor:
register (cpsr), and the pipeline.

2.1 REGISTERS
either data or an address. They are identified with the
General-purpose registers hold
number. For example, register 4 is given the label r4.
letter r prefixed to the register
registers available in user mode-a protected
mode normally
Figure 2.2 shows the active

rl
r2
r3
r4
r5

r7
r8
r9
rl0
rll
rl2
rl3 sp
rl4 lr
rl5pc

cpsr

Figure 2.2 Registers available in user mode.

 22 Chapter 2 ARMI Processor Fundamentals

nd when executing applications. The

processor can operate in seven different modes.
which we will introduce shortly. Allthe registers shown are 32 bits in size.
There are up to 18 active registers: 16 data registers and 2
processor status registers. The
data registers are visible to the programmer as ro to r15.
The ARM processor has three registers assigned to a particular task or special
function:
rl3, rl4, and r1s. They are frequently given different labels to differentiate themfrom h
other registers.
In Figure 2.2, the shaded registers identify the assigned special-purpose registers:
Register rl3 is traditionally used as the stack pointer (sp) and stores the head of the stack
in the current processor mode.
Register rl4 is called the link register (lr) and is where the core puts the return address
whenever it calls a subroutine.
I Register rl5 is the program counter (pc) and contains the address of the next instruction
to be fetched by the processor.

Depending upon the context, registers rl3 and rl4 can also be used as general-purpose
registers, which can be particularly useful since these registers are banked during a processor
mode change. However, it is dangerous to use r13 as a general register when the processor
r13
is running any form of operating system because operating systems often assume that
always points to a valid stack frame.
In ARM state the registers ro to rl3 are orthogona -any instruction that you can apply
instructions
to rOyou can equally well apply to any of theother registers. However, there are
that treat rl4 and rl5 in a special way.
In addition to the 16 data registers, there are two program status registers: cpsr and spsr
(the current and saved program status registers, respectively).
The register file contains all the registers available to a programmer. Which registers are
visible to the programmer depend upon the current mode of the processor.

2.2 CURRENT PROGRAM STATUS REGISTER

The cpsr is a
The ARM core uses the cpsr to monitor and control internal operations.
dedicated 32-bit register and resides in the register file. Figure 2.3 shows the basic layout
parts are reserved for future
of a generic program status register. Note that the shaded
expansion.
The cpsr is divided into four fields, each 8 bits wide: flags, status, extension, and control.
future use. The control
In current designs the extension and status fields are reserved for
field contains
field contains the processor mode, state, and interrupt mask bits. The flags
the condition flags. which can
Some ARM processor cores have extra bits allocated. For example, the J bit,
execute
be found in the flags field, is only available on Jazelle-enabled processors, which
 2.2 Current Program Status
Register 23

Flags Status Extension Control

Fields
Bit 3130 29 28 76 5 4

Mode
Nzlc|v|

Function Interrupt Processor

Condition
Masks mode
flags Thumb
state

Figure 2.3 Ageneric program status register (psr).

Section 2.2.3.It is highly probable that
8-bit instructions. We will discuss Jazelle more in
monitoring and control of new features.
future designs willassign extra bits for the
B.
For a full description of the cpsT, refer to Appendix

2.2.1 PROCESSOR MODES

active and the access rights to the cpsr
The processor mode determines which registers are
or nonprivileged: Aprivileged mode
register itself. Each processor mode is either privilegednonprivileged
a mode only allows read
allows full read-write access to the cpsr. Conversely, read-write access to the condition flags.
access to the control field in the cpsr but stillallows
privileged modes (abort, fast interrupt
There are seven processor modes in total: six nonprivileged mode
request, interrupt request, supervisor, system, and undefined) and one
(user). attempt to access memory. Fast
The processor enters abort mode when there is a failed
modes correspond to the two interrupt levels available
interrupt request and interrupt request that the processor is in after reset and
on the ARM processor. Supervisor mode is the mode operates in. System mode is a special
is generally the mode that an operating system kernel cpsr. Undefined mode is used
version of user mode that allows full read-write access to the
or not supported by the
when the processor encounters an instruction that is undefined
implementation, User mode is used for programs and applications.

2.2.2 BANKED REGISTERS

are hidden from
Figure 2.4 shows all 37 registers in the register file. Of those, 20 registersand are identified
banked registers
a program at different times. These registers are called a particular
by the shading in the diagram. They are available only when the processor is in
 Fundamentals
4 Chapter 2 ARM Processor

User and
System

rl
r2
r3

Fast
r5
r
interrupt
request
r7
r8 r&_fig
r9fiq
rlo rl0_fiqg
Interrupt Abort
rl! rll_fiq request Supervisor Undefined
r12 |r12_fiq r13_undef r13_abt
rl3_irg rl3_svc
rl3 sp r13_fiq rl4_undef rl4 abt
rl4 lr rl4_fig rl4_irq |rl4_svc
rl5 pc

cpsT spsr_abt
spsr_fig| spsr_irq |spsr_svc| spsr_undef

Figure 2.4 Complete ARM register set.

rl3_abt, rl4_abt and spsr_abt. Banked

mode; for example, abort mode has banked registers character post-fixed to the mode
particular mode are denoted by an underline
registers of a
mnemonic or_mode.
processor mode except user mode can change mode by writing directly to the
Every mode have a set of associated
system
mode bits of the cpsr. All processor modes except banked register maps one-to
banked registers that are a subset of the main 16 registers. A
mode, a banked register from the
one onto a user mode register. If you change processor
new mode will replace an existing register. the instructions you
For example, when the processor is in the interrupt request mode,
registers are the banked
execute still access registers named rl3 and rl4. However, these
rl4_usT are not affected
registers rl3_irq and rl4_irq. The user mode registers rl3_usr and access to the other
normal
by the instruction referencing these registers. Aprogram still has
registers rO to rl2.
The processor mode can be changed by a program that writes directly to the cpsr (the
processor core has to be in privileged mode) or by hardware when the core responds to
 2.2 Current Program Status Register 25

User mode

rl
r2
3
r4
r5

r8

r10 Interrupt
rll request
mode
rl2
rl3 sp rl3_irq
rl4 lr rl4_irg
rl5pc

cpsr
spsr_irq

Figure 2.5 Changing mode on an exception.

an exception or interrupt. The following exceptions and interrupts cause a mode change:
reset, interrupt request, fast interrupt request, software interrupt, data abort, prefetch abort,
and undefined instruction. Exceptions and interrupts suspend the normal execution of
sequential instructions and jump to a specific location.
Figure 2.5 illustrates what happens when an interrupt forces a mode change. The figure
shows the core changing from user mode to interrupt request mode, which happens when an
interrupt request occurs due to an external device raising an interrupt to the processor core.
This change causes user registers rl3 and rl4 to be banked. The user registers are replaced
with registers rl3_irq and rl4_irq, respectively. Note rl4_irq contains the return address
and r13_irq contains the stack pointer for interrupt request mode.
Figure 2.5 also shows anew register appearing in interrupt request mode: the saved
program status register (spsr), which stores the previous mode's cpsr. You can see in the
diagram the cpsr being copied into spsr_iq. To return back to user mode, a special return
instruction is used that instructs the core to restore the original cpsr from the spsr_irq and
bank in the user registers r13 and rl4. Note that the spsr can only be modifed and read in a
privileged mode. There is no spsr available in user mode.
 Processor Fundamentals
26 Chapter2 ARM

Table 2.l Processor mode.

Abbreviation Privileged Mode[4:0]

Mode
abt yes 10111
Abort yes 10001
Fast interrupt request fiq
yes 10010
Interrupt request irq 10011
SVC yes
Supervisor yes 11111
sys
System und yes 11011
Undefined usr
no 10000
User

whena
feature to note is that the cpsr is not copied into the spsr
Another important directly to the cpsr. The saving of the
psr
due to a program writing
mode change is forced
or interrupt is raised.
only occurs when an exception active processor mode occupies the five least significant
Figure 2.3 shows that the current which is
power is applied to the core, it starts in supervisor mode, access
bits of the cpsr. When mode is useful since initialization code can
use full
privileged. Starting in a privileged modes.
the stacks for each of the other of
associated binary patterns. The last column
to the çpSr to set up
the various modes and the
Table 2.1 lists of the processor modes in the çpsr.
bit patterns that represent each
the table gives the

SETS
2.2.3 STATE AND INSTRUCTION
three
determines which instruction set is being executed. There are
The state of the core is only active when
instruction sets: ARM, Thumb, and Jazelle. The ARM instruction set when
in ARM state. Similarly the Thumb instruction set is only active
the processor is executing purely
processor is in Thumb, state. Once in Thumb state the processor is
the intermingle sequential ARM, Thumb, and Jazelle
Thumb l6-bit instructions. You cannot
instructions. both
Jazelle J and Thumb Tbits in the cpsr reflect the state of the processor. When the
The instructions. This is
ARM state and executes ARM
Jand Tbits are 0, the processor is in the T bit is 1, then the processor is in
applied to the processor. When
case when power is executes a specialized branch instruction. Table 2.2
Thumb state. To change states the core
set features.
comparesthe ARM and Thumb instruction
instruction set called Jazelle. Jazelle executes
The ARM designers introduced a third
and hardware designed to speed up the
8-bit instructions and is a hybrid mix of software
execution of Java bytecodes. modified
technology plus a specially
To execute Java bytecodes, you require the Jazelleto note that the hardware portion of
version of the Java virtual machine. It is important
bytecodes; the rest are emulated in software.
Jazelle only supports a subset of the Java
 2.2
Current Program Status
Register 27
Table 2.2 ARM and Thumb instruction set features.

ARM (Cpsr T=0)

Instruction size 32-bit
Thumb (cpsr T= 1)
16-bit
Core instructions 58
30
Conditional execution? most
access to barrel shifter and
only branch instructions
Data processing separate barrel shifter and
instructions ALU
ALU instructions
Program status register read-write in privileged mode no direct access
Register usage 15 general-purpose registers 8general-purpose registers
+pc +7 high registers +pc
a See Section 2.2.6.

Table 2.3 Jazelle instruction set features.

Jazelle (cpsr T= 0,J=1)

Instruction size 8-bit
Core instructions Over 60% of the Java bytecodes are implemented in hardware;
the rest of the codes are implemented in software.

The Jazelle instruction set is a closed instruction set and is not openly available. Table 2.3
gives the Jazelle instruction set features.

2.2.4 INTERRUPT MASKS

Interrupt masks are used to stop specific interrupt requests from interrupting the processor.
There are two interrupt request levels available on the ARM processor core-interrupt
request (IRQ) and fast interrupt request (FIQ).
The cpsr has two interrupt mask bits, 7 and 6 (or I and F), which control the masking
of IRQ and FIQ, respectively. The I bit masks IRQ when set to binary 1, and similarly the
F bit masks FIQ when set to binary 1.

2.2.5 CONDITION FLAGs

Condition flags are updated by comparisons and the result of ALU operations that specify
the Sinstruction suffix. For example, ifa SUBS Subtract instruction results in aregister value
of zero, then the Zflag in the cpsr is set. This particular subtract instruction speciñcaly
updates the cpsr.
 Processor Fundamentals
28 Chapter 2 ARM

Table 2.4 Condition flags.

Flag name Set when

Flag
Saturation the result causes an overflow and/or saturation
oVerflow the result causes a signed overflow
Carry the result causes an unsigned carry
Zero
the result is zero, frequently used to indicate equality
Z
bit 31 of the result is a binary 1
N Negative

the Qbit indicates if an overflow

With processor cores that include the DSP extensions,
instruction. The flag is "sticky" in the
or saturation has occurred in an enhanced DSP
flag you need to write to the cpsr
sense that the hardware only sets this flag. To clear the
directly. the core; if it is set, the core is
In Jazelle-enabled processors, the Jbit reflects the state of
on some processor cores.
in Jazelle state. The Jbit is not generally usable and is only available both ARM Limited and
licensed from
To take advantage of Jazelle, extra software has to be
Sun Microsystems. the value of the condition
Most ARM instructions can be executed conditionally on
be
what causes them to
flags. Table 2.4 lists the condition flags and a short description on
bits are used for
set. These flags are located in the most significant bits in the cpsr. These
conditional execution.
In
Figure 2.6 shows a typical value for the cpsr with both DSP extensions and Jazelle.
form.
human readable
this book we use a notation that presents the cpsr data in a more
When a bit is a binary l we use a capital letter; when a bit is a binary 0, we use a lowercase
letter. For the condition flags a capital letter shows that the flag has been set. For interrupts
a capital letter shows that an interrupt is disalbled.
In the cpsr example shown in Figure 2.6, the Cflag is the only condition flag set. The rest
nzvq flags are all clear. The processor is in ARM state because neither the Jazelle jor Thumb t
bits are set. The IRQ interrupts are enabled, and FIQ interrupts are disabled. Finally, you

31 30 29 28 27 24 76 5 4 0

olol1lolo| ollo 10011

nzCvq j iF t SVC

Figure 2.6 Example: cpsr = nzCvqjiPt_SVC.

 2.3 Pipeline 29

Table 2.5 Condition mnemonics.

Mnemonic Name
Condition flags
EQ equal Z
NE not equal
559z| CS HS
3CC LO
carry set/unsigned higher or same
carry clear/unsigned lower C
C

MI minus/negative N
PlL plus/positive or zero
VS overflow
no overflow
unsigned higher zC
LS unsigned lower or same Zor c
GE signed greater than or equal NVor ny
signed less than Nv or nV
LT
GT signed greater than NzVor nzv
LE signed less than or equal Zor Ny ornV
AL always (unconditional) ignored

can see from the figure the processor is in supervisor (SVC) mode since the mode(4:0] is
equal to binary 10011.

2.2.6 CONDITIONAL EXECUTION

Conditional execution controls whether or not the core will execute an instruction.
Most instructions have a condition attribute that determines if the core will execute it
based on the setting of the condition flags. Prior to execution, the processor compares the
condition attribute with the condition flags in the cpsr. If they match, then the instruction
is executed; otherwise the instruction is ignored.
The condition attribute is postfixed to the instruction mnemonic, which is encoded
into the instruction. Table 2.5 lists the conditional execution code mnemonics. When a
condition mnemonic is not present, the default behavior is to set it to always (AL) execute.

2.3 PIPELINE
Apipeline is the mechanism a RISC processor uses to execute instructions. Using a pipeline
speeds up execution by fetching the next instruction while other instructions are being
decoded and executed. One way to view the pipeline is to think of it as an automobile
assembly line, with each stage carrying out aparticular task to manufacture the vehicle.